JP2021535594A - 量子計算チップのためのワイヤボンド・クロストーク減少 - Google Patents
量子計算チップのためのワイヤボンド・クロストーク減少 Download PDFInfo
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- G—PHYSICS
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- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
Abstract
Description
Claims (25)
- 量子計算チップにおけるクロストークを減少させるためのワイヤボンドの構成であって、
量子計算回路の第1の導体を外部回路の第1の導体と連結する第1のワイヤボンドと、
前記量子計算回路の第2の導体を前記外部回路の第2の導体と連結する第2のワイヤボンドであって、前記第1のワイヤボンドと前記第2のワイヤボンドとが、前記第1の導体の長さ方向に第1の垂直距離だけ分離される、前記第2のワイヤボンドと、
を備える、構成。 - 前記第2のワイヤボンドの向きが、前記第1のワイヤボンドの向きから角度が付けられている、請求項1に記載の構成。
- 前記第2のワイヤボンドの前記向きが、前記第1のワイヤボンドの前記向きに略直交する、請求項2に記載の構成。
- 前記第2のワイヤボンドの前記向きが、前記第1のワイヤボンドの前記向きに略平行である、請求項2に記載の構成。
- 前記量子計算回路の第3の導体を前記外部回路の第3の導体と連結する第3のワイヤボンドであって、前記第2のワイヤボンドと前記第3のワイヤボンドとが、第2の垂直距離だけ分離される、前記第3のワイヤボンドをさらに備える、請求項1ないし4のいずれかに記載の構成。
- 前記第1の垂直距離と前記第2の垂直距離とが等しい、請求項5に記載の構成。
- 前記第3のワイヤボンドの向きが、前記第2のワイヤボンドの向きから角度が付けられている、請求項5に記載の構成。
- 前記第3のワイヤボンドの前記向きが、前記第1のワイヤボンドの向きと実質的に類似している、請求項5ないし7のいずれかに記載の構成。
- 前記量子計算回路の第4の導体を前記外部回路の第4の導体と連結する第4のワイヤボンドであって、前記第3のワイヤボンドと前記第4のワイヤボンドとが、第3の垂直距離だけ分離される、前記第4のワイヤボンドをさらに備える、請求項5に記載の構成。
- 前記第3の垂直距離が、前記第1の垂直距離および前記第2の垂直距離の合計と等しい、請求項9に記載の構成。
- 前記第3の垂直距離が、前記第1の垂直距離と等しい、請求項9に記載の構成。
- 前記第3の垂直距離が、前記第2の垂直距離と等しい、請求項9に記載の構成。
- 前記第4のワイヤボンドの向きが、前記第3のワイヤボンドの向きから角度が付けられている、請求項9に記載の構成。
- 前記第4のワイヤボンドの向きが、前記第2のワイヤボンドの向きに略平行である、請求項9に記載の構成。
- 前記第2の導体が、前記外部回路の前記第1の導体の隣接導体である、請求項1ないし14のいずれかに記載の構成。
- 前記第3の導体が、前記外部回路の前記第2の導体の隣接導体である、請求項5ないし15のいずれかに記載の構成。
- 前記第4の導体が、前記外部回路の前記第3の導体の隣接導体である、請求項9ないし16のいずれかに記載の構成。
- 方法であって、
量子計算回路の第1の導体を外部回路の第1の導体と連結するように第1のワイヤボンドを構成することと、
前記量子計算回路の第2の導体を前記外部回路の第2の導体と連結するように第2のワイヤボンドを構成することであって、前記第1のワイヤボンドと前記第2のワイヤボンドとが、前記第1の導体の長さ方向に第1の垂直距離だけ分離される、前記第2のワイヤボンドを構成することと、
を含む、方法。 - 前記量子計算回路の第3の導体を前記外部回路の第3の導体と連結するように第3のワイヤボンドを構成することであって、前記第2のワイヤボンドと前記第3のワイヤボンドとが、第2の垂直距離だけ分離される、前記第3のワイヤボンドを構成することをさらに含む、請求項18に記載の方法。
- 前記量子計算回路の第4の導体を前記外部回路の第4の導体と連結するように第4のワイヤボンドを構成することであって、前記第3のワイヤボンドと前記第4のワイヤボンドとが、第3の垂直距離だけ分離される、前記第4のワイヤボンドを構成することをさらに含む、請求項19に記載の方法。
- 前記第3の垂直距離が、前記第1の垂直距離および前記第2の垂直距離の合計と等しい、請求項20に記載の方法。
- 前記第3の垂直距離が、前記第1の垂直距離と等しい、請求項20に記載の方法。
- 前記第2の導体が、前記外部回路の前記第1の導体の隣接導体である、請求項18ないし22のいずれかに記載の方法。
- 前記第3の導体が、前記外部回路の前記第2の導体の隣接導体である、請求項19ないし23のいずれかに記載の方法。
- 前記第4の導体が、前記外部回路の前記第3の導体の隣接導体である、請求項20ないし24のいずれかに記載の方法。
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US16/114,124 | 2018-08-27 | ||
US16/114,124 US10833238B2 (en) | 2018-08-27 | 2018-08-27 | Wirebond cross-talk reduction for quantum computing chips |
PCT/EP2019/071755 WO2020043489A1 (en) | 2018-08-27 | 2019-08-13 | Wirebond cross-talk reduction for quantum computing chips |
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EP (1) | EP3844685A1 (ja) |
JP (1) | JP7410125B2 (ja) |
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US11762733B2 (en) * | 2020-11-23 | 2023-09-19 | Electronics And Telecommunications Research Institute | Quantum computing system and operation method thereof |
CN115409181B (zh) * | 2021-05-28 | 2024-02-06 | 本源量子计算科技(合肥)股份有限公司 | 量子芯片的校准方法和装置、量子测控系统、量子计算机 |
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EP1436870A2 (en) | 2001-10-09 | 2004-07-14 | Infinera Corporation | TRANSMITTER PHOTONIC INTEGRATED CIRCUITS (TxPIC) AND OPTICAL TRANSPORT NETWORKS EMPLOYING TxPICs |
JP4533173B2 (ja) | 2004-02-24 | 2010-09-01 | キヤノン株式会社 | 半導体集積回路装置 |
US7533068B2 (en) | 2004-12-23 | 2009-05-12 | D-Wave Systems, Inc. | Analog processor comprising quantum devices |
JP5062508B2 (ja) * | 2006-05-30 | 2012-10-31 | 公益財団法人国際超電導産業技術研究センター | 超電導素子とその製造方法 |
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Non-Patent Citations (1)
Title |
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S.BLANVILLAIN ET AL.: "Suppressing on-chip electromagnetic crosstalk for spin qubit devices", JOURNAL OF APPLIED PHYSICS, vol. 112, no. 6, JPN7023000878, 20 September 2012 (2012-09-20), US, pages 64315 - 1, ISSN: 0005007112 * |
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US20200066961A1 (en) | 2020-02-27 |
CN112585626A (zh) | 2021-03-30 |
EP3844685A1 (en) | 2021-07-07 |
JP7410125B2 (ja) | 2024-01-09 |
WO2020043489A1 (en) | 2020-03-05 |
US20210151656A1 (en) | 2021-05-20 |
US10833238B2 (en) | 2020-11-10 |
US11038093B2 (en) | 2021-06-15 |
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