JP2021521626A - 超伝導デバイスにおけるpcbからダイへの遷移部のクロストーク軽減 - Google Patents
超伝導デバイスにおけるpcbからダイへの遷移部のクロストーク軽減 Download PDFInfo
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- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
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Abstract
Description
Claims (20)
- デバイスであって、
超伝導体からなるチップと、
1組のワイヤボンドによって前記チップに取り付けられた少なくとも1つの超伝導データ線と、
前記1組のワイヤボンドをそれぞれ分離する磁気遮蔽壁とを含むデバイス。 - 前記磁気遮蔽壁のうちの少なくとも1つの磁気遮蔽壁が、少なくとも1つのワイヤボンド伸長部の高さの2倍以上の高さを有する、請求項1に記載のデバイス。
- 前記磁気遮蔽壁のうちの少なくとも1つの磁気遮蔽壁が、少なくとも1つのワイヤボンド伸長部の高さの約5倍以上の長さを有する、請求項1または2に記載のデバイス。
- 前記磁気遮蔽壁のうちの少なくとも1つの磁気遮蔽壁が、ほぼ表皮厚さ以上の厚さを有する、請求項1に記載のデバイス。
- 1組の磁気遮蔽壁が、前記少なくとも1つの超伝導データ線をクロストークから遮蔽する、請求項1に記載のデバイス。
- 前記少なくとも1つの超伝導データ線の各端を2対の磁気遮蔽壁がそれぞれ遮蔽する、請求項5に記載のデバイス。
- 前記少なくとも1つの超伝導データ線が第一種超伝導体を含み、1組の前記遮蔽壁がロンドン侵入の関数である厚さを有する、請求項1に記載のデバイス。
- 前記磁気遮蔽壁のうちの少なくとも1つの前記磁気遮蔽壁が前記量子チップセットの遷移部にはんだ付けされた、請求項1に記載のデバイス。
- 前記磁気遮蔽壁がクロストークを−50dB未満に減衰させる、請求項1に記載のデバイス。
- 前記磁気遮蔽壁がクロストークを−60dB未満に減衰させる、請求項1に記載のデバイス。
- 前記磁気遮蔽壁がクロストークを−70dB未満に減衰させる、請求項1に記載のデバイス。
- 量子コンピューティング・デバイスである、請求項1に記載のデバイス。
- デバイスを製作する方法であって、
超伝導体からなるチップセットを形成する動作と、
1組のワイヤボンドによってチップセット・ダイに少なくとも1つの超伝導データ線を取り付ける動作と、
それぞれのワイヤボンドをそれぞれ分離する磁気遮蔽壁を形成する動作とを含む方法。 - 前記磁気遮蔽壁のうちの少なくとも1つの磁気遮蔽壁を、少なくとも1つのワイヤボンド伸長部の高さの約2倍以上の高さを有するように形成することをさらに含む、請求項13に記載の方法。
- 前記磁気遮蔽壁のうちの少なくとも1つの磁気遮蔽壁を、少なくとも1つのワイヤボンド伸長部の高さの約5倍以上の長さを有するように形成することをさらに含む、請求項13に記載の方法。
- 前記少なくとも1つの超伝導データ線をクロストークから遮蔽するように1組の磁気遮蔽壁を形成する、請求項13に記載の方法。
- 前記磁気遮蔽壁を、超伝導データ線間のクロストークを−50dB未満に減衰させるように形成することをさらに含む、請求項13に記載の方法。
- デバイスであって、
超伝導体からなるチップセットと、
1組のワイヤボンドによってチップセット・ダイに取り付けられた少なくとも1つの超伝導データ線と、
それぞれのワイヤボンドをそれぞれ分離する磁気遮蔽壁とを含むデバイスであって、
前記磁気遮蔽壁のうちの少なくとも1つの磁気遮蔽壁が、少なくとも1つのワイヤボンド伸長部の高さの約2倍以上の高さを有し、
前記磁気遮蔽壁のうちの少なくとも1つの磁気遮蔽壁が、少なくとも1つのワイヤボンド伸長部の高さの約5倍以上の長さを有し、
2対の磁気遮蔽壁が、前記少なくとも1つの超伝導データ線の各端をそれぞれ遮蔽するデバイス。 - 前記磁気遮蔽壁がクロストークを−50dB未満に減衰させる、請求項18に記載のデバイス。
- 前記磁気遮蔽壁が、クロストークを−60dB未満に減衰させる、請求項18に記載のデバイス。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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US15/974,302 | 2018-05-08 | ||
US15/974,302 US10390423B1 (en) | 2018-05-08 | 2018-05-08 | Crosstalk mitigation for PCB to die transition in superconducting devices |
PCT/EP2019/060479 WO2019214943A1 (en) | 2018-05-08 | 2019-04-24 | Crosstalk mitigation for pcb to die transition in superconducting devices |
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JP2021521626A true JP2021521626A (ja) | 2021-08-26 |
JP7267297B2 JP7267297B2 (ja) | 2023-05-01 |
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US (2) | US10390423B1 (ja) |
JP (1) | JP7267297B2 (ja) |
CN (1) | CN112074951A (ja) |
WO (1) | WO2019214943A1 (ja) |
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WO2021148621A1 (en) | 2020-01-24 | 2021-07-29 | Qdevil Aps | A multi channel filter for low electron temperatures |
WO2021148626A1 (en) | 2020-01-24 | 2021-07-29 | Qdevil Aps | A rolled or folded filter |
CN111430853B (zh) * | 2020-04-13 | 2021-06-08 | 卢姝欣 | 一种超导滤波器封装屏蔽装置 |
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2018
- 2018-05-08 US US15/974,302 patent/US10390423B1/en active Active
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2019
- 2019-04-24 JP JP2020551456A patent/JP7267297B2/ja active Active
- 2019-04-24 CN CN201980030573.XA patent/CN112074951A/zh active Pending
- 2019-04-24 WO PCT/EP2019/060479 patent/WO2019214943A1/en active Application Filing
- 2019-07-17 US US16/513,957 patent/US10716202B2/en active Active
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US8664774B1 (en) * | 2010-04-09 | 2014-03-04 | Lattice Semiconductor Corporation | Bondwire configuration for reduced crosstalk |
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Publication number | Publication date |
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WO2019214943A1 (en) | 2019-11-14 |
US20190350074A1 (en) | 2019-11-14 |
US10716202B2 (en) | 2020-07-14 |
CN112074951A (zh) | 2020-12-11 |
US10390423B1 (en) | 2019-08-20 |
JP7267297B2 (ja) | 2023-05-01 |
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