JP2021184507A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2021184507A JP2021184507A JP2021144540A JP2021144540A JP2021184507A JP 2021184507 A JP2021184507 A JP 2021184507A JP 2021144540 A JP2021144540 A JP 2021144540A JP 2021144540 A JP2021144540 A JP 2021144540A JP 2021184507 A JP2021184507 A JP 2021184507A
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- film
- oxide semiconductor
- transistor
- conductive film
- insulating film
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Abstract
Description
本実施の形態においては、本発明の一態様の半導体装置及び半導体装置の作製方法について、図1乃至図20を用いて以下説明する。
図1(A)は、本発明の一態様の半導体装置であるトランジスタ100の上面図である。また、図1(B)は、図1(A)に示す一点鎖線X1−X2間における切断面の断面図に相当し、図1(C)は、図1(A)に示す一点鎖線Y1−Y2間における切断面の断面図に相当する。なお、図1(A)においては明瞭化のため、トランジスタ100の構成要素の一部(基板102及び絶縁膜等)を省略して図示している。
次に、図1(A)(B)(C)に示すトランジスタ100と異なる構成例について、図2乃至図11を用いて説明する。なお、以下の図2乃至図11において、トランジスタ100と同様の機能を有する場合には、ハッチパターンを同じくし、特に符号を付さない場合がある。
図2に示すトランジスタ100Aにおける酸化物半導体膜108は、第1のゲート絶縁膜と、第2のゲート絶縁膜とを間に挟んで、導電膜104と、導電膜120bとに挟持される。導電膜104のチャネル長方向の長さ及びチャネル幅方向の長さは、酸化物半導体膜108のチャネル長方向の長さ及びチャネル幅方向の長さよりもそれぞれ長い。また、導電膜120bのチャネル長方向の長さ及びチャネル幅方向の長さは、酸化物半導体膜108のチャネル長方向の長さ及びチャネル幅方向の長さよりもそれぞれ長い。そのため、酸化物半導体膜108の全体は、第1のゲート絶縁膜及び第2のゲート絶縁膜を間に挟んで導電膜104及び導電膜120bに覆われている。
図7(A)(B)は、本発明の一態様の半導体装置であるトランジスタ100Gの断面図であり、トランジスタ100Gの上面図は、図1(A)に示すトランジスタ100と同様であり、図7(A)は、図1(A)に示す一点鎖線X1−X2間における切断面の断面図に相当し、図7(B)は、図1(A)に示す一点鎖線Y1−Y2間における切断面の断面図に相当する。
図12(A)は、トランジスタ100Pの上面図であり、図12(B)は、図12(A)に示す一点鎖線X1−X2間における切断面の断面図に相当し、図12(C)は、図12(A)に示す一点鎖線Y1−Y2間における切断面の断面図に相当する。
以下に本実施の形態の半導体装置に含まれる構成要素について、詳細に説明する。
基板102の材質などに大きな制限はないが、少なくとも、後の熱処理に耐えうる程度の耐熱性を有している必要がある。例えば、ガラス基板、セラミック基板、石英基板、サファイア基板等を、基板102として用いてもよい。また、シリコンや炭化シリコンを材料とした単結晶半導体基板、多結晶半導体基板、シリコンゲルマニウム等の化合物半導体基板、SOI基板等を適用することも可能であり、これらの基板上に半導体素子が設けられたものを、基板102として用いてもよい。
第1のゲート電極として機能する導電膜104、ソース電極として機能する導電膜112a、ドレイン電極として機能する導電膜112b、接続電極として機能する導電膜112c、第2のゲート電極として機能する導電膜120b、及び画素電極として機能する導電膜120aとしては、クロム(Cr)、銅(Cu)、アルミニウム(Al)、金(Au)、銀(Ag)、亜鉛(Zn)、モリブデン(Mo)、タンタル(Ta)、チタン(Ti)、タングステン(W)、マンガン(Mn)、ニッケル(Ni)、鉄(Fe)、コバルト(Co)から選ばれた金属元素、または上述した金属元素を成分とする合金か、上述した金属元素を組み合わせた合金等を用いてそれぞれ形成することができる。
トランジスタ100の第1のゲート絶縁膜として機能する絶縁膜106、107としては、プラズマ化学気相堆積(PECVD:(Plasma Enhanced Chemical Vapor Deposition))法、スパッタリング法等により、酸化シリコン膜、酸化窒化シリコン膜、窒化酸化シリコン膜、窒化シリコン膜、酸化アルミニウム膜、酸化ハフニウム膜、酸化イットリウム膜、酸化ジルコニウム膜、酸化ガリウム膜、酸化タンタル膜、酸化マグネシウム膜、酸化ランタン膜、酸化セリウム膜および酸化ネオジム膜を一種以上含む絶縁層を、それぞれ用いることができる。なお、絶縁膜106、107の積層構造とせずに、上述の材料から選択された単層の絶縁膜、または3層以上の絶縁膜を用いてもよい。
酸化物半導体膜108としては、先に示す材料を用いることができる。
絶縁膜114、116は、トランジスタ100の第2のゲート絶縁膜として機能する。また、絶縁膜114、116は、酸化物半導体膜108に酸素を供給する機能を有する。すなわち、絶縁膜114、116は、酸素を有する。また、絶縁膜114は、酸素を透過することのできる絶縁膜である。なお、絶縁膜114は、後に形成する絶縁膜116を形成する際の、酸化物半導体膜108へのダメージ緩和膜としても機能する。
絶縁膜118は、トランジスタ100の保護絶縁膜として機能する。
次に、本発明の一態様の半導体装置であるトランジスタ100Jの作製方法について、図14乃至図17を用いて説明する。なお、図14乃至図17は、半導体装置の作製方法を説明する断面図であり、図14(A)(C)(E)、図15(A)(C)(E)、図16(A)(C)(E)、図17(A)(C)(E)は、X1−X2に示すチャネル長方向であり、図14(B)(D)(F)、図15(B)(D)(F)、図16(B)(D)(F)、図17(B)(D)(F)は、Y1−Y2に示すチャネル幅方向の断面図である。
まず、基板102上に導電膜を形成し、該導電膜をリソグラフィ工程及びエッチング工程を行い加工して、第1のゲート電極として機能する導電膜104を形成する。次に、導電膜104上に第1のゲート絶縁膜として機能する絶縁膜106、107を形成する(図14(A)(B)参照)。
次に、絶縁膜107上に酸化物半導体膜108b及び酸化物半導体膜108cを形成する(図14(C)(D)参照)。
次に、絶縁膜107及び酸化物半導体膜108上に、後にソース電極及びドレイン電極となる、導電膜112をスパッタリング法によって形成する(図15(A)(B)参照)。
次に、酸化物半導体膜108、及び導電膜112a、112b上に絶縁膜114、及び絶縁膜116を形成する(図16(C)(D)参照)。
次に、開口部152cを覆うように、絶縁膜116上に導電膜120a、120bを形成する(図17(A)(B)(C)(D)参照)。
次に、絶縁膜116、及び導電膜120a、120b上に絶縁膜118を形成する(図17(E)(F)参照)。
次に、本発明の一態様の半導体装置であるトランジスタ100Mの作製方法について、図18乃至図20を用いて説明する。なお、図18乃至図20は、半導体装置の作製方法を説明する断面図であり、図18(A)(C)(E)、図19(A)(C)、図20(A)は、X1−X2に示すチャネル長方向であり、図18(B)(D)(F)、図19(B)(D)、図20(B)は、Y1−Y2に示すチャネル幅方向の断面図である。
本実施の形態においては、本発明の一態様に用いることのできる、酸化物半導体の組成、及び酸化物半導体の構造等について、図21乃至図28を参照して説明する。
まず、酸化物半導体の組成について説明する。
続いて、上記酸化物半導体をトランジスタに用いる場合について説明する。
続いて、該酸化物半導体を2層構造、または3層構造とした場合について述べる。酸化物半導体S1、酸化物半導体S2、および酸化物半導体S3の積層構造に接する絶縁体のバンド図と、酸化物半導体S2および酸化物半導体S3の積層構造に接する絶縁体のバンド図と、について、図23を用いて説明する。
以下では、酸化物半導体の構造について説明する。
まずは、CAAC−OSについて説明する。
次に、nc−OSについて説明する。
a−like OSは、nc−OSと非晶質酸化物半導体との間の構造を有する酸化物半導体である。
次に、酸化物半導体のキャリア密度について、以下に説明を行う。
本実施の形態においては、先の実施の形態で例示したトランジスタを有する表示装置の一例について、図29乃至図35を用いて以下説明を行う。
図30及び図32に示す表示装置700は、引き回し配線部711と、画素部702と、ソースドライバ回路部704と、FPC端子部708と、を有する。また、引き回し配線部711は、信号線710を有する。また、画素部702は、トランジスタ750及び容量素子790を有する。また、ソースドライバ回路部704は、トランジスタ752を有する。
図30に示す表示装置700は、液晶素子775を有する。液晶素子775は、導電膜772、導電膜774、及び液晶層776を有する。導電膜774は、第2の基板705側に設けられ、対向電極としての機能を有する。図30に示す表示装置700は、導電膜772と導電膜774に印加される電圧によって、液晶層776の配向状態が変わることによって光の透過、非透過が制御され画像を表示することができる。
図32に示す表示装置700は、発光素子782を有する。発光素子782は、導電膜772、EL層786、及び導電膜788を有する。図32に示す表示装置700は、発光素子782が有するEL層786が発光することによって、画像を表示することができる。なお、EL層786は、有機化合物、または量子ドットなどの無機化合物を有する。
また、図32及び図33に示す表示装置700に入出力装置を設けてもよい。当該入出力装置としては、例えば、タッチパネル等が挙げられる。
本実施の形態では、本発明の一態様の半導体装置を有する表示装置について、図36を用いて説明を行う。
図36(A)に示す表示装置は、表示素子の画素を有する領域(以下、画素部502という)と、画素部502の外側に配置され、画素を駆動するための回路を有する回路部(以下、駆動回路部504という)と、素子の保護機能を有する回路(以下、保護回路506という)と、端子部507と、を有する。なお、保護回路506は、設けない構成としてもよい。
本実施の形態では、上述の実施の形態で説明したトランジスタの適用可能な回路構成の一例について、図37乃至図40を用いて説明する。
図37(A)には、駆動回路が有するシフトレジスタやバッファ等に適用することができるインバータの回路図を示す。インバータ800は、入力端子INの論理を反転した信号を出力端子OUTに出力する。インバータ800は、複数のOSトランジスタを有する。信号SBGは、OSトランジスタの電気特性を切り替えることができる信号である。
本実施の形態では、上述の実施の形態で説明した酸化物半導体を有するトランジスタ(OSトランジスタ)を、複数の回路に用いる半導体装置の一例について、図41乃至図44を用いて説明する。
図41(A)は、半導体装置900のブロック図である。半導体装置900は、電源回路901、回路902、電圧生成回路903、回路904、電圧生成回路905および回路906を有する。
本実施の形態では、本発明の一態様の半導体装置を有する表示モジュール及び電子機器について、図45乃至図48を用いて説明を行う。
図45に示す表示モジュール7000は、上部カバー7001と下部カバー7002との間に、FPC7003に接続されたタッチパネル7004、FPC7005に接続された表示パネル7006、バックライト7007、フレーム7009、プリント基板7010、バッテリ7011を有する。
次に、図46(A)乃至図46(E)に電子機器の一例を示す。
次に、図46(A)乃至図46(E)に示す電子機器と、異なる電子機器の一例を図47(A)乃至図47(G)に示す。
本実施の形態では、電力が供給されない状況でも記憶内容の保持が可能で、かつ、書き込み回数にも制限が無い半導体装置(記憶装置)、およびそれを含むCPUについて図49乃至図51を用いて説明する。本実施の形態で説明するCPUは、例えば、先の実施の形態で説明する電子機器に用いる事が出来る。
電力が供給されない状況でも記憶内容の保持が可能で、かつ、書き込み回数にも制限が無い半導体装置(記憶装置)の一例を図49に示す。なお、図49(B)は図49(A)を回路図で表した図である。
以下で、上記の記憶装置を含むCPUについて説明する。
本実施の形態では、本発明の一態様の半導体装置を用いることができる撮像装置について図52及び図53を用いて説明する。
図52(A)に示す回路を有する撮像装置610は、光電変換素子601、トランジスタ602、トランジスタ604、および容量素子606を有する。トランジスタ602のソースまたはドレインの一方は光電変換素子601と電気的に接続される。トランジスタ602のソースまたはドレインの他方はノード607(電荷蓄積部)を介してトランジスタ604のゲートと電気的に接続されている。
トランジスタ602として、例えば先の実施の形態に例示したトランジスタなどを用いることができる。なお、トランジスタ604にOSトランジスタを用いてもよい。
試料A1としては、720mm×600mmサイズのガラス基板上に、厚さが35nmの窒化タンタルと、厚さが200nmの銅とを、スパッタリング装置を用いて順に成膜した。
上記作製した試料A1及び試料A2を、STEMにより断面形状の観察を行った。図54(A)は、試料A1の断面STEM写真であり、図54(B)は、試料A2の断面STEM写真である。
次に、試料A2の表面のXPS分析を行った。表1に、XPSで求めた組成を示す。なお、表面のXPSにおける検出深さは、5nm程度である。
次に、試料B1及び試料B2に相当するトランジスタの作製方法について説明する。なお、トランジスタの作製方法は、実施の形態1を参酌すればよい。
基板102上に導電膜104を形成した。基板102としては、ガラス基板を用いた。また、導電膜104としては、厚さが10nmのチタン膜と、厚さが100nmの銅膜と、厚さが50nmの窒化タンタル膜とを、スパッタリング装置を用いて順に形成した。
基板102上に導電膜104を形成した。基板102としては、ガラス基板を用いた。また、導電膜104としては、厚さが100nmのタングステン膜を、スパッタリング装置を用いて形成した。
上記作製した試料B1及び試料B2に相当するトランジスタの電気特性の評価を行った。トランジスタの電気特性としては、ドレイン電流(Id)−ゲート電圧(Vg)特性、およびId−Vg特性における電界効果移動度(μFE)とした。試料B1及び試料B2のトランジスタの電気特性を図57及び図58に示す。また、図57(A)及び図58(A)はチャネル長が2μm且つチャネル幅が50μmのトランジスタ特性を、図57(B)及び図58(B)はチャネル長が3μm且つチャネル幅が50μmのトランジスタ特性を、図57(C)乃至図58(C)はチャネル長が6μm且つチャネル幅が50μmのトランジスタ特性を、それぞれ示す。
試料C1としては、720mm×600mmサイズのガラス基板上に、厚さが100nmの酸化窒化シリコン(SiON)膜を、PECVD装置を用いて成膜した。次に、酸化窒化シリコン膜上に導電膜を形成し、該導電膜上にレジストマスクを形成し、所望の領域をエッチングした。該導電膜としては、厚さ5nmのタングステン(W)膜と、厚さ200nmの銅(Cu)膜と、厚さ5nmのタングステン(W)膜とを、スパッタリング装置を用いて真空中で連続して形成した。なお、該導電膜の形成後レジストマスクを除去した。
上記作製した試料C1及び試料C2を、STEMにより断面形状の観察を行った。図59(A)は、試料C1の断面STEM写真であり、図59(B)は、試料C2の断面STEM写真である。
I2 絶縁体
S1 酸化物半導体
S2 酸化物半導体
S3 酸化物半導体
100 トランジスタ
100A トランジスタ
100B トランジスタ
100C トランジスタ
100D トランジスタ
100E トランジスタ
100F トランジスタ
100G トランジスタ
100H トランジスタ
100J トランジスタ
100K トランジスタ
100L トランジスタ
100M トランジスタ
100N トランジスタ
100P トランジスタ
100Q トランジスタ
102 基板
104 導電膜
106 絶縁膜
107 絶縁膜
108 酸化物半導体膜
108a 酸化物半導体膜
108b 酸化物半導体膜
108c 酸化物半導体膜
112 導電膜
112_1 導電膜
112_2 導電膜
112_3 導電膜
112a 導電膜
112a_1 導電膜
112a_2 導電膜
112a_2a 領域
112a_2b 領域
112a_3 導電膜
112b 導電膜
112b_1 導電膜
112b_2 導電膜
112b_2a 領域
112b_2b 領域
112b_3 導電膜
112c 導電膜
112c_1 導電膜
112c_2 導電膜
112c_2a 領域
112c_2b 領域
112c_3 導電膜
114 絶縁膜
116 絶縁膜
118 絶縁膜
120a 導電膜
120b 導電膜
141a マスク
141b マスク
142a マスク
142b マスク
151 開口部
151a 開口部
151b 開口部
152a 開口部
152b 開口部
152c 開口部
152d 開口部
191 ターゲット
192 プラズマ
193 ターゲット
194 プラズマ
195 プラズマ
501 画素回路
502 画素部
504 駆動回路部
504a ゲートドライバ
504b ソースドライバ
506 保護回路
507 端子部
550 トランジスタ
552 トランジスタ
554 トランジスタ
560 容量素子
562 容量素子
570 液晶素子
572 発光素子
601 光電変換素子
602 トランジスタ
603 トランジスタ
604 トランジスタ
605 トランジスタ
606 容量素子
607 ノード
608 配線
609 配線
610 撮像装置
611 配線
641 基板
681 光電変換層
682 透光性導電層
686 電極
700 表示装置
701 基板
702 画素部
704 ソースドライバ回路部
705 基板
706 ゲートドライバ回路部
708 FPC端子部
710 信号線
711 配線部
712 シール材
716 FPC
730 絶縁膜
732 封止膜
734 絶縁膜
736 着色膜
738 遮光膜
750 トランジスタ
752 トランジスタ
760 接続電極
770 平坦化絶縁膜
772 導電膜
773 絶縁膜
774 導電膜
775 液晶素子
776 液晶層
777 導電膜
778 構造体
780 異方性導電膜
782 発光素子
786 EL層
788 導電膜
790 容量素子
791 タッチパネル
792 絶縁膜
793 電極
794 電極
795 絶縁膜
796 電極
797 絶縁膜
800 インバータ
810 OSトランジスタ
820 OSトランジスタ
831 信号波形
832 信号波形
840 破線
841 実線
850 OSトランジスタ
860 CMOSインバータ
900 半導体装置
901 電源回路
902 回路
903 電圧生成回路
903A 電圧生成回路
903B 電圧生成回路
903C 電圧生成回路
904 回路
905 電圧生成回路
906 回路
911 トランジスタ
912 トランジスタ
912A トランジスタ
912B トランジスタ
921 制御回路
922 トランジスタ
1220 ウェル
1221 p型半導体
1223 n型半導体
2189 ROMインターフェース
2190 基板
2191 ALU
2192 ALUコントローラ
2193 インストラクションデコーダ
2194 インタラプトコントローラ
2195 タイミングコントローラ
2196 レジスタ
2197 レジスタコントローラ
2198 バスインターフェース
2199 ROM
2200 記憶素子
2201 回路
2202 回路
2203 スイッチ
2204 スイッチ
2206 論理素子
2207 容量素子
2208 容量素子
2209 トランジスタ
2210 トランジスタ
2213 トランジスタ
2214 トランジスタ
2220 回路
3101 配線
3102 配線
3103 配線
3104 配線
3105 配線
3200 トランジスタ
3300 トランジスタ
3400 容量素子
7000 表示モジュール
7001 上部カバー
7002 下部カバー
7003 FPC
7004 タッチパネル
7005 FPC
7006 表示パネル
7007 バックライト
7008 光源
7009 フレーム
7010 プリント基板
7011 バッテリ
8000 カメラ
8001 筐体
8002 表示部
8003 操作ボタン
8004 シャッターボタン
8006 レンズ
8100 ファインダー
8101 筐体
8102 表示部
8103 ボタン
8200 ヘッドマウントディスプレイ
8201 装着部
8202 レンズ
8203 本体
8204 表示部
8205 ケーブル
8206 バッテリ
8300 ヘッドマウントディスプレイ
8301 筐体
8302 表示部
8304 固定具
8305 レンズ
9000 筐体
9001 表示部
9003 スピーカ
9005 操作キー
9006 接続端子
9007 センサ
9008 マイクロフォン
9050 操作ボタン
9051 情報
9052 情報
9053 情報
9054 情報
9055 ヒンジ
9100 テレビジョン装置
9101 携帯情報端末
9102 携帯情報端末
9200 携帯情報端末
9201 携帯情報端末
9500 表示装置
9501 表示パネル
9502 表示領域
9503 領域
9511 軸部
9512 軸受部
Claims (2)
- トランジスタを有する半導体装置であって、
前記トランジスタは、
ゲート電極と、
前記ゲート電極上の第1の絶縁膜と、
前記第1の絶縁膜を間に挟んで前記ゲート電極と重なる領域を有する酸化物半導体膜と、
前記酸化物半導体膜と電気的に接続されるソース電極と、
前記酸化物半導体膜と電気的に接続されるドレイン電極と、
前記酸化物半導体膜上、前記ソース電極上、及び前記ドレイン電極上の第2の絶縁膜と、を有し、
前記酸化物半導体膜は、第1の酸化物半導体膜と、前記第1の酸化物半導体膜上に接する第2の酸化物半導体膜と、を有し、
前記第2の酸化物半導体膜の膜厚は、前記第1の酸化物半導体膜の膜厚よりも大きく、
前記ソース電極及び前記ドレイン電極は、それぞれ第1の導電膜と、前記第1の導電膜上に接する第2の導電膜と、を有し、
前記第1の導電膜の端部は、前記第2の導電膜の端部より外側に位置する領域を有し、
前記第1の導電膜は、チタンを有し、
前記第2の導電膜は、銅を有し、
前記第2の導電膜の端部は、銅を含む化合物を有する領域を有する半導体装置。 - 請求項1において、
前記第1の酸化物半導体膜及び前記第2の酸化物半導体膜は、それぞれ、Inと、Znと、M(Mは、Al、Ga、Y、またはSnを表す)と、を有する半導体装置。
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JP7246442B2 (ja) | 2023-03-27 |
US20240088303A1 (en) | 2024-03-14 |
CN114093890A (zh) | 2022-02-25 |
US11107930B2 (en) | 2021-08-31 |
JP6941567B2 (ja) | 2021-09-29 |
US20200295195A1 (en) | 2020-09-17 |
CN108475700B (zh) | 2022-01-14 |
CN114093890B (zh) | 2023-07-04 |
WO2017130073A1 (ja) | 2017-08-03 |
JP2023078278A (ja) | 2023-06-06 |
US10734529B2 (en) | 2020-08-04 |
JPWO2017130073A1 (ja) | 2018-11-15 |
KR20180107117A (ko) | 2018-10-01 |
CN108475700A (zh) | 2018-08-31 |
US20190035935A1 (en) | 2019-01-31 |
US11830950B2 (en) | 2023-11-28 |
DE112017000551T5 (de) | 2018-10-18 |
CN114068723A (zh) | 2022-02-18 |
US20210305433A1 (en) | 2021-09-30 |
CN114068724A (zh) | 2022-02-18 |
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