JP2021043975A - インターフェース回路並びにメモリ装置及びその動作方法 - Google Patents

インターフェース回路並びにメモリ装置及びその動作方法 Download PDF

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Publication number
JP2021043975A
JP2021043975A JP2020152603A JP2020152603A JP2021043975A JP 2021043975 A JP2021043975 A JP 2021043975A JP 2020152603 A JP2020152603 A JP 2020152603A JP 2020152603 A JP2020152603 A JP 2020152603A JP 2021043975 A JP2021043975 A JP 2021043975A
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Japan
Prior art keywords
data processing
command
memory
memory device
circuit
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Pending
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JP2020152603A
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English (en)
Japanese (ja)
Inventor
大 フン 羅
Daehoon Na
大 フン 羅
將 雨 李
Jang Woo Lee
將 雨 李
政 燉 任
Jeong-Don Ihm
政 燉 任
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of JP2021043975A publication Critical patent/JP2021043975A/ja
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0602Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061Improving I/O performance
    • G06F3/0613Improving I/O performance in relation to throughput
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1642Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1615Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using a concurrent pipeline structrure
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1647Handling requests for interconnection or transfer for access to memory bus based on arbitration with interleaved bank access
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • G06F13/1673Details of memory controller using buffers
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • G06F13/1684Details of memory controller using multiple buses
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/382Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0602Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061Improving I/O performance
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0628Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659Command handling arrangements, e.g. command buffers, queues, command scheduling
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0668Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671In-line storage system
    • G06F3/0673Single storage device
    • G06F3/0679Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0668Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671In-line storage system
    • G06F3/0683Plurality of storage devices
    • G06F3/0688Non-volatile semiconductor memory arrays
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/06Address interface arrangements, e.g. address buffers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/12Group selection circuits, e.g. for memory block selection, chip selection, array selection

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System (AREA)
  • Dram (AREA)
JP2020152603A 2019-09-11 2020-09-11 インターフェース回路並びにメモリ装置及びその動作方法 Pending JP2021043975A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2019-0113012 2019-09-11
KR1020190113012A KR20210031266A (ko) 2019-09-11 2019-09-11 인터페이스 회로, 메모리 장치, 저장 장치 및 메모리 장치의 동작 방법

Publications (1)

Publication Number Publication Date
JP2021043975A true JP2021043975A (ja) 2021-03-18

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US (2) US11199975B2 (de)
EP (1) EP3792775A1 (de)
JP (1) JP2021043975A (de)
KR (1) KR20210031266A (de)
CN (1) CN112486866A (de)
SG (1) SG10202006754WA (de)

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KR20220001370A (ko) * 2020-06-29 2022-01-05 에스케이하이닉스 주식회사 액티브동작을 수행하기 위한 전자장치
CN114550775A (zh) * 2020-11-24 2022-05-27 瑞昱半导体股份有限公司 内存控制器及其控制方法
US12020771B2 (en) * 2021-08-13 2024-06-25 Micron Technology, Inc. Die location detection for grouped memory dies

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US5136582A (en) * 1990-05-29 1992-08-04 Advanced Micro Devices, Inc. Memory management system and method for network controller
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US6778436B2 (en) 2001-10-10 2004-08-17 Fong Piau Apparatus and architecture for a compact flash memory controller
KR101429869B1 (ko) * 2006-02-09 2014-08-12 구글 인코포레이티드 메모리 회로 시스템 및 방법
WO2007116486A1 (ja) 2006-03-31 2007-10-18 Fujitsu Limited メモリ装置、その制御方法、その制御プログラム、メモリ・カード、回路基板及び電子機器
KR100851545B1 (ko) 2006-12-29 2008-08-11 삼성전자주식회사 커맨드 및 어드레스 핀을 갖는 낸드 플래시 메모리 및그것을 포함한 플래시 메모리 시스템
US8972627B2 (en) * 2009-09-09 2015-03-03 Fusion-Io, Inc. Apparatus, system, and method for managing operations for data storage media
US8966208B2 (en) * 2010-02-25 2015-02-24 Conversant Ip Management Inc. Semiconductor memory device with plural memory die and controller die
KR101893176B1 (ko) 2010-12-03 2018-08-29 삼성전자주식회사 멀티 칩 메모리 장치 및 그것의 구동 방법
US20120239874A1 (en) * 2011-03-02 2012-09-20 Netlist, Inc. Method and system for resolving interoperability of multiple types of dual in-line memory modules
US9645758B2 (en) * 2011-07-22 2017-05-09 Sandisk Technologies Llc Apparatus, system, and method for indexing data of an append-only, log-based structure
US9335952B2 (en) 2013-03-01 2016-05-10 Ocz Storage Solutions, Inc. System and method for polling the status of memory devices
US9684622B2 (en) * 2014-06-09 2017-06-20 Micron Technology, Inc. Method and apparatus for controlling access to a common bus by multiple components
US9933950B2 (en) * 2015-01-16 2018-04-03 Sandisk Technologies Llc Storage operation interrupt
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JP2017123208A (ja) * 2016-01-06 2017-07-13 ルネサスエレクトロニクス株式会社 半導体記憶装置
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SG10202006754WA (en) 2021-04-29
US11960728B2 (en) 2024-04-16
CN112486866A (zh) 2021-03-12
US20210072902A1 (en) 2021-03-11
US20220083237A1 (en) 2022-03-17
KR20210031266A (ko) 2021-03-19
US11199975B2 (en) 2021-12-14
EP3792775A1 (de) 2021-03-17

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