JP2020535643A5 - - Google Patents
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- Publication number
- JP2020535643A5 JP2020535643A5 JP2020516898A JP2020516898A JP2020535643A5 JP 2020535643 A5 JP2020535643 A5 JP 2020535643A5 JP 2020516898 A JP2020516898 A JP 2020516898A JP 2020516898 A JP2020516898 A JP 2020516898A JP 2020535643 A5 JP2020535643 A5 JP 2020535643A5
- Authority
- JP
- Japan
- Prior art keywords
- temperature
- niobium
- forming
- layer
- traces
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910052758 niobium Inorganic materials 0.000 claims 36
- 239000010955 niobium Substances 0.000 claims 36
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 claims 36
- 239000003989 dielectric material Substances 0.000 claims 22
- 238000000034 method Methods 0.000 claims 18
- 239000000758 substrate Substances 0.000 claims 12
- 239000004642 Polyimide Substances 0.000 claims 8
- 229920001721 polyimide Polymers 0.000 claims 8
- 238000009987 spinning Methods 0.000 claims 7
- 239000007788 liquid Substances 0.000 claims 4
- 229920000642 polymer Polymers 0.000 claims 4
- 239000002184 metal Substances 0.000 claims 3
- 229910052751 metal Inorganic materials 0.000 claims 3
- 230000002411 adverse Effects 0.000 claims 2
- 238000001459 lithography Methods 0.000 claims 2
- 239000000463 material Substances 0.000 claims 2
- 238000000059 patterning Methods 0.000 claims 2
- 230000000694 effects Effects 0.000 claims 1
- 239000012528 membrane Substances 0.000 claims 1
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15/715,521 | 2017-09-26 | ||
| US15/715,521 US10651362B2 (en) | 2017-09-26 | 2017-09-26 | Method of forming superconducting apparatus including superconducting layers and traces |
| PCT/US2018/039214 WO2019067039A1 (en) | 2017-09-26 | 2018-06-25 | DEVICE MANUFACTURE COMPRISING SUPERCONDUCTING WIRING LAYERS AND INTERCONNECTIONS |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2020535643A JP2020535643A (ja) | 2020-12-03 |
| JP2020535643A5 true JP2020535643A5 (https=) | 2021-07-26 |
| JP7170036B2 JP7170036B2 (ja) | 2022-11-11 |
Family
ID=63077939
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2020516898A Active JP7170036B2 (ja) | 2017-09-26 | 2018-06-25 | 超伝導配線層およびインターコネクトを有する機器の製作 |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US10651362B2 (https=) |
| EP (1) | EP3688796B1 (https=) |
| JP (1) | JP7170036B2 (https=) |
| AU (1) | AU2018341994B2 (https=) |
| WO (1) | WO2019067039A1 (https=) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10651362B2 (en) * | 2017-09-26 | 2020-05-12 | Microsoft Technology Licensing, Llc | Method of forming superconducting apparatus including superconducting layers and traces |
| US10615223B2 (en) | 2018-06-12 | 2020-04-07 | International Business Machines Corporation | Vertical silicon-on-metal superconducting quantum interference device |
| US20200083154A1 (en) | 2018-09-10 | 2020-03-12 | At&S Austria Technologie & Systemtechnik Aktiengesellschaft | Component Carrier With a Photoimageable Dielectric Layer and a Structured Conductive Layer Being Used as a Mask for Selectively Exposing the Photoimageable Dielectric Layer With Electromagnetic Radiation |
| US11417819B2 (en) * | 2020-04-27 | 2022-08-16 | Microsoft Technology Licensing, Llc | Forming a bumpless superconductor device by bonding two substrates via a dielectric layer |
| FR3114443B1 (fr) * | 2020-09-21 | 2022-12-23 | Commissariat Energie Atomique | Structure d’intégration à routage bifonctionnel et assemblage comprenant une telle structure |
| US11742326B2 (en) * | 2020-12-28 | 2023-08-29 | Microsoft Technology Licensing, Llc | Stacked superconducting integrated circuits with three dimensional resonant clock networks |
| FR3129772B1 (fr) * | 2021-11-30 | 2024-10-04 | Commissariat Energie Atomique | Structure d’intégration destinée à connecter une pluralité de dispositifs semi-conducteurs, procédés, assemblage et système associés |
| FI20245823A1 (en) * | 2024-06-27 | 2025-12-28 | Teknologian Tutkimuskeskus Vtt Oy | Superconducting longitudinal connection and method for producing the same |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA1329952C (en) * | 1987-04-27 | 1994-05-31 | Yoshihiko Imanaka | Multi-layer superconducting circuit substrate and process for manufacturing same |
| JP2875093B2 (ja) * | 1992-03-17 | 1999-03-24 | 三菱電機株式会社 | 半導体装置 |
| US5476719A (en) | 1994-08-17 | 1995-12-19 | Trw Inc. | Superconducting multi-layer microstrip structure for multi-chip modules and microwave circuits |
| JPH09260378A (ja) * | 1996-03-22 | 1997-10-03 | Canon Inc | 埋め込み配線形成方法 |
| JP3457851B2 (ja) * | 1997-06-30 | 2003-10-20 | 京セラ株式会社 | 電子回路部品 |
| US6420251B1 (en) * | 1999-01-05 | 2002-07-16 | Trw Inc. | Method for fabricating a microelectronic integrated circuit with improved step coverage |
| JP4711249B2 (ja) | 2002-08-01 | 2011-06-29 | 独立行政法人産業技術総合研究所 | 超伝導集積回路及びその作製方法 |
| EP3098865B1 (en) * | 2009-02-27 | 2018-10-03 | D-Wave Systems Inc. | Method for fabricating a superconducting integrated circuit |
| US8735326B2 (en) * | 2010-05-19 | 2014-05-27 | Northrop Grumman Systems Corporation | Methods of forming superconductor circuits |
| WO2013180780A2 (en) * | 2012-03-08 | 2013-12-05 | D-Wave Systems Inc. | Systems and methods for fabrication of superconducting integrated circuits |
| JP6435860B2 (ja) | 2012-11-05 | 2018-12-19 | 大日本印刷株式会社 | 配線構造体 |
| US9741918B2 (en) * | 2013-10-07 | 2017-08-22 | Hypres, Inc. | Method for increasing the integration level of superconducting electronics circuits, and a resulting circuit |
| EP3195377B1 (en) * | 2014-08-13 | 2021-12-15 | D-Wave Systems Inc. | Method of forming superconducting wiring layers with low magnetic noise |
| US9653398B1 (en) * | 2015-12-08 | 2017-05-16 | Northrop Grumman Systems Corporation | Non-oxide based dielectrics for superconductor devices |
| US10003005B2 (en) * | 2016-08-23 | 2018-06-19 | Northrop Grumman Systems Corporation | Superconductor device interconnect |
| US10276504B2 (en) * | 2017-05-17 | 2019-04-30 | Northrop Grumman Systems Corporation | Preclean and deposition methodology for superconductor interconnects |
| US10651362B2 (en) * | 2017-09-26 | 2020-05-12 | Microsoft Technology Licensing, Llc | Method of forming superconducting apparatus including superconducting layers and traces |
-
2017
- 2017-09-26 US US15/715,521 patent/US10651362B2/en active Active
-
2018
- 2018-06-25 EP EP18749196.4A patent/EP3688796B1/en active Active
- 2018-06-25 WO PCT/US2018/039214 patent/WO2019067039A1/en not_active Ceased
- 2018-06-25 AU AU2018341994A patent/AU2018341994B2/en active Active
- 2018-06-25 JP JP2020516898A patent/JP7170036B2/ja active Active
-
2020
- 2020-04-07 US US16/842,431 patent/US11114602B2/en active Active
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