AU2018341994B2 - Fabrication of apparatus including superconducting wiring layers and interconnects - Google Patents

Fabrication of apparatus including superconducting wiring layers and interconnects Download PDF

Info

Publication number
AU2018341994B2
AU2018341994B2 AU2018341994A AU2018341994A AU2018341994B2 AU 2018341994 B2 AU2018341994 B2 AU 2018341994B2 AU 2018341994 A AU2018341994 A AU 2018341994A AU 2018341994 A AU2018341994 A AU 2018341994A AU 2018341994 B2 AU2018341994 B2 AU 2018341994B2
Authority
AU
Australia
Prior art keywords
niobium
layer
superconducting
temperature
traces
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
AU2018341994A
Other languages
English (en)
Other versions
AU2018341994A1 (en
Inventor
Richard P. Rouse
David B. Tuckerman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microsoft Technology Licensing LLC
Original Assignee
Microsoft Technology Licensing LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microsoft Technology Licensing LLC filed Critical Microsoft Technology Licensing LLC
Publication of AU2018341994A1 publication Critical patent/AU2018341994A1/en
Application granted granted Critical
Publication of AU2018341994B2 publication Critical patent/AU2018341994B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00Superconducting devices
    • H10N60/01Manufacture or treatment
    • H10N60/0268Manufacture or treatment of devices comprising copper oxide
    • H10N60/0661Processes performed after copper oxide formation, e.g. patterning
    • H10N60/0688Etching
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00Superconducting devices
    • H10N60/01Manufacture or treatment
    • H10N60/0156Manufacture or treatment of devices comprising Nb or an alloy of Nb with one or more of the elements of group IVB, e.g. titanium, zirconium or hafnium
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00Superconducting devices
    • H10N60/01Manufacture or treatment
    • H10N60/0856Manufacture or treatment of devices comprising metal borides, e.g. MgB2
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00Superconducting devices
    • H10N60/80Constructional details
    • H10N60/805Constructional details for Josephson-effect devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00Superconducting devices
    • H10N60/80Constructional details
    • H10N60/85Superconducting active materials
    • H10N60/855Ceramic superconductors
    • H10N60/857Ceramic superconductors comprising copper oxide
    • H10N60/858Ceramic superconductors comprising copper oxide having multilayered structures, e.g. superlattices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/031Manufacture or treatment of conductive parts of the interconnections
    • H10W20/064Manufacture or treatment of conductive parts of the interconnections by modifying the conductivity of conductive parts, e.g. by alloying
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/071Manufacture or treatment of dielectric parts thereof
    • H10W20/093Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts
    • H10W20/097Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts by thermally treating
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44Conductive materials thereof
    • H10W20/4403Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H10W20/4437Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being a transition metal
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44Conductive materials thereof
    • H10W20/4484Superconducting materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/66Conductive materials thereof
    • H10W70/668Superconducting materials
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B05SPRAYING OR ATOMISING IN GENERAL; APPLYING FLUENT MATERIALS TO SURFACES, IN GENERAL
    • B05DPROCESSES FOR APPLYING FLUENT MATERIALS TO SURFACES, IN GENERAL
    • B05D1/00Processes for applying liquids or other fluent materials
    • B05D1/002Processes for applying liquids or other fluent materials the substrate being rotated
    • B05D1/005Spin coating
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B05SPRAYING OR ATOMISING IN GENERAL; APPLYING FLUENT MATERIALS TO SURFACES, IN GENERAL
    • B05DPROCESSES FOR APPLYING FLUENT MATERIALS TO SURFACES, IN GENERAL
    • B05D5/00Processes for applying liquids or other fluent materials to surfaces to obtain special surface effects, finishes or structures
    • B05D5/12Processes for applying liquids or other fluent materials to surfaces to obtain special surface effects, finishes or structures to obtain a coating with specific electrical properties
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B05SPRAYING OR ATOMISING IN GENERAL; APPLYING FLUENT MATERIALS TO SURFACES, IN GENERAL
    • B05DPROCESSES FOR APPLYING FLUENT MATERIALS TO SURFACES, IN GENERAL
    • B05D7/00Processes, other than flocking, specially adapted for applying liquids or other fluent materials to particular surfaces or for applying particular liquids or other fluent materials
    • B05D7/50Multilayers
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00Manufacture or treatment of nanostructures
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227Other objects, e.g. metallic pieces
    • H05K2201/10378Interposers
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4602Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H05K3/4605Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated made from inorganic insulating material
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/467Adding a circuit layer by thin film methods
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00Superconducting devices
    • H10N60/01Manufacture or treatment
    • H10N60/0912Manufacture or treatment of Josephson-effect devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01Manufacture or treatment
    • H10W70/05Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68Shapes or dispositions thereof
    • H10W70/685Shapes or dispositions thereof comprising multiple insulating layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
AU2018341994A 2017-09-26 2018-06-25 Fabrication of apparatus including superconducting wiring layers and interconnects Active AU2018341994B2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/715,521 2017-09-26
US15/715,521 US10651362B2 (en) 2017-09-26 2017-09-26 Method of forming superconducting apparatus including superconducting layers and traces
PCT/US2018/039214 WO2019067039A1 (en) 2017-09-26 2018-06-25 DEVICE MANUFACTURE COMPRISING SUPERCONDUCTING WIRING LAYERS AND INTERCONNECTIONS

Publications (2)

Publication Number Publication Date
AU2018341994A1 AU2018341994A1 (en) 2020-02-20
AU2018341994B2 true AU2018341994B2 (en) 2022-09-29

Family

ID=63077939

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2018341994A Active AU2018341994B2 (en) 2017-09-26 2018-06-25 Fabrication of apparatus including superconducting wiring layers and interconnects

Country Status (5)

Country Link
US (2) US10651362B2 (https=)
EP (1) EP3688796B1 (https=)
JP (1) JP7170036B2 (https=)
AU (1) AU2018341994B2 (https=)
WO (1) WO2019067039A1 (https=)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10651362B2 (en) * 2017-09-26 2020-05-12 Microsoft Technology Licensing, Llc Method of forming superconducting apparatus including superconducting layers and traces
US10615223B2 (en) 2018-06-12 2020-04-07 International Business Machines Corporation Vertical silicon-on-metal superconducting quantum interference device
US20200083154A1 (en) 2018-09-10 2020-03-12 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Component Carrier With a Photoimageable Dielectric Layer and a Structured Conductive Layer Being Used as a Mask for Selectively Exposing the Photoimageable Dielectric Layer With Electromagnetic Radiation
US11417819B2 (en) * 2020-04-27 2022-08-16 Microsoft Technology Licensing, Llc Forming a bumpless superconductor device by bonding two substrates via a dielectric layer
FR3114443B1 (fr) * 2020-09-21 2022-12-23 Commissariat Energie Atomique Structure d’intégration à routage bifonctionnel et assemblage comprenant une telle structure
US11742326B2 (en) * 2020-12-28 2023-08-29 Microsoft Technology Licensing, Llc Stacked superconducting integrated circuits with three dimensional resonant clock networks
FR3129772B1 (fr) * 2021-11-30 2024-10-04 Commissariat Energie Atomique Structure d’intégration destinée à connecter une pluralité de dispositifs semi-conducteurs, procédés, assemblage et système associés
FI20245823A1 (en) * 2024-06-27 2025-12-28 Teknologian Tutkimuskeskus Vtt Oy Superconducting longitudinal connection and method for producing the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5930674A (en) * 1992-03-17 1999-07-27 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with improved planarization properties

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1329952C (en) * 1987-04-27 1994-05-31 Yoshihiko Imanaka Multi-layer superconducting circuit substrate and process for manufacturing same
US5476719A (en) 1994-08-17 1995-12-19 Trw Inc. Superconducting multi-layer microstrip structure for multi-chip modules and microwave circuits
JPH09260378A (ja) * 1996-03-22 1997-10-03 Canon Inc 埋め込み配線形成方法
JP3457851B2 (ja) * 1997-06-30 2003-10-20 京セラ株式会社 電子回路部品
US6420251B1 (en) * 1999-01-05 2002-07-16 Trw Inc. Method for fabricating a microelectronic integrated circuit with improved step coverage
JP4711249B2 (ja) 2002-08-01 2011-06-29 独立行政法人産業技術総合研究所 超伝導集積回路及びその作製方法
EP3098865B1 (en) * 2009-02-27 2018-10-03 D-Wave Systems Inc. Method for fabricating a superconducting integrated circuit
US8735326B2 (en) * 2010-05-19 2014-05-27 Northrop Grumman Systems Corporation Methods of forming superconductor circuits
WO2013180780A2 (en) * 2012-03-08 2013-12-05 D-Wave Systems Inc. Systems and methods for fabrication of superconducting integrated circuits
JP6435860B2 (ja) 2012-11-05 2018-12-19 大日本印刷株式会社 配線構造体
US9741918B2 (en) * 2013-10-07 2017-08-22 Hypres, Inc. Method for increasing the integration level of superconducting electronics circuits, and a resulting circuit
EP3195377B1 (en) * 2014-08-13 2021-12-15 D-Wave Systems Inc. Method of forming superconducting wiring layers with low magnetic noise
US9653398B1 (en) * 2015-12-08 2017-05-16 Northrop Grumman Systems Corporation Non-oxide based dielectrics for superconductor devices
US10003005B2 (en) * 2016-08-23 2018-06-19 Northrop Grumman Systems Corporation Superconductor device interconnect
US10276504B2 (en) * 2017-05-17 2019-04-30 Northrop Grumman Systems Corporation Preclean and deposition methodology for superconductor interconnects
US10651362B2 (en) * 2017-09-26 2020-05-12 Microsoft Technology Licensing, Llc Method of forming superconducting apparatus including superconducting layers and traces

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5930674A (en) * 1992-03-17 1999-07-27 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with improved planarization properties

Also Published As

Publication number Publication date
JP2020535643A (ja) 2020-12-03
EP3688796A1 (en) 2020-08-05
US20190097118A1 (en) 2019-03-28
JP7170036B2 (ja) 2022-11-11
US10651362B2 (en) 2020-05-12
US20200243743A1 (en) 2020-07-30
US11114602B2 (en) 2021-09-07
WO2019067039A1 (en) 2019-04-04
AU2018341994A1 (en) 2020-02-20
EP3688796B1 (en) 2021-12-22

Similar Documents

Publication Publication Date Title
US11114602B2 (en) Method of forming superconducting layers and traces
AU2018413356B2 (en) Computing system with superconducting and non-superconducting components located on a common substrate
US10658424B2 (en) Superconducting integrated circuit
US10134972B2 (en) Qubit and coupler circuit structures and coupling techniques
US4996584A (en) Thin-film electrical connections for integrated circuits
EP3718166A1 (en) Bumped resonator structure
EP0190490B1 (en) Thin-film electrical connections for integrated circuits
CN112272811B (zh) 具有使用金属预成型件的热管理的低温计算系统
WO2020027779A1 (en) Signal distribution for a quantum computing system
CN105261551B (zh) 多层电路组件的制造
US20190252243A1 (en) Method of manufacturing airbridges for high performance semiconductor device
EP3488475B1 (en) Superconducting device with stress reducing dummy elements
CN114692882B (zh) 一种超导量子芯片制备方法
CN117276246B (zh) 芯片封装结构及封装方法
CN118159121A (zh) 一种单磁通量子脉冲器件及其制备方法
HK40032665A (en) Computing system with superconducting and nonsuperconducting components located on a common substrate
HK40032665B (en) Computing system with superconducting and nonsuperconducting components located on a common substrate

Legal Events

Date Code Title Description
FGA Letters patent sealed or granted (standard patent)