JP2020528493A5 - - Google Patents

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Publication number
JP2020528493A5
JP2020528493A5 JP2020501310A JP2020501310A JP2020528493A5 JP 2020528493 A5 JP2020528493 A5 JP 2020528493A5 JP 2020501310 A JP2020501310 A JP 2020501310A JP 2020501310 A JP2020501310 A JP 2020501310A JP 2020528493 A5 JP2020528493 A5 JP 2020528493A5
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JP
Japan
Prior art keywords
substrate
gas
layer
plasma process
sectional
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JP2020501310A
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English (en)
Japanese (ja)
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JP7414708B2 (ja
JP2020528493A (ja
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Priority claimed from US16/028,855 external-priority patent/US10535527B2/en
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Publication of JP2020528493A5 publication Critical patent/JP2020528493A5/ja
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JP2020501310A 2017-07-13 2018-07-10 半導体膜を堆積させるための方法 Active JP7414708B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201762532335P 2017-07-13 2017-07-13
US62/532,335 2017-07-13
US16/028,855 US10535527B2 (en) 2017-07-13 2018-07-06 Methods for depositing semiconductor films
US16/028,855 2018-07-06
PCT/US2018/041379 WO2019014170A1 (en) 2017-07-13 2018-07-10 METHODS OF DEPOSITING SEMICONDUCTOR FILMS

Publications (3)

Publication Number Publication Date
JP2020528493A JP2020528493A (ja) 2020-09-24
JP2020528493A5 true JP2020528493A5 (enExample) 2021-08-19
JP7414708B2 JP7414708B2 (ja) 2024-01-16

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ID=64999830

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JP2020501310A Active JP7414708B2 (ja) 2017-07-13 2018-07-10 半導体膜を堆積させるための方法

Country Status (6)

Country Link
US (1) US10535527B2 (enExample)
JP (1) JP7414708B2 (enExample)
KR (1) KR102536884B1 (enExample)
CN (1) CN110998791B (enExample)
TW (1) TWI791029B (enExample)
WO (1) WO2019014170A1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020009742A1 (en) * 2018-07-05 2020-01-09 Applied Materials, Inc. Silicide film nucleation
US11955381B2 (en) 2020-06-22 2024-04-09 Applied Materials, Inc. Low-temperature plasma pre-clean for selective gap fill
US12191151B2 (en) * 2021-03-26 2025-01-07 Taiwan Semiconductor Manufacturing Co., Ltd. Gate-all-around transistor with reduced source/drain contact resistance
JP7715466B2 (ja) 2021-09-27 2025-07-30 東京エレクトロン株式会社 基板処理方法及び基板処理システム

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US5975912A (en) * 1994-06-03 1999-11-02 Materials Research Corporation Low temperature plasma-enhanced formation of integrated circuits
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JP2003203867A (ja) * 2001-12-28 2003-07-18 Shin Etsu Handotai Co Ltd 気相成長方法及び気相成長装置
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JP4451097B2 (ja) * 2002-10-17 2010-04-14 東京エレクトロン株式会社 成膜方法
KR100476482B1 (ko) * 2002-12-14 2005-03-21 동부전자 주식회사 반도체 소자의 장벽 금속층 형성 방법
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