JP2020523800A - 半導体チップを基板の上に固定する方法および電子構成素子 - Google Patents
半導体チップを基板の上に固定する方法および電子構成素子 Download PDFInfo
- Publication number
- JP2020523800A JP2020523800A JP2020518567A JP2020518567A JP2020523800A JP 2020523800 A JP2020523800 A JP 2020523800A JP 2020518567 A JP2020518567 A JP 2020518567A JP 2020518567 A JP2020518567 A JP 2020518567A JP 2020523800 A JP2020523800 A JP 2020523800A
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- Prior art keywords
- layer
- indium
- tin
- gold
- substrate
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 77
- 239000000758 substrate Substances 0.000 title claims abstract description 76
- 238000000034 method Methods 0.000 title claims abstract description 66
- 229910052751 metal Inorganic materials 0.000 claims abstract description 150
- 239000002184 metal Substances 0.000 claims abstract description 150
- 239000011135 tin Substances 0.000 claims abstract description 122
- 229910001128 Sn alloy Inorganic materials 0.000 claims abstract description 108
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 99
- 229910052718 tin Inorganic materials 0.000 claims abstract description 99
- 239000010931 gold Substances 0.000 claims abstract description 89
- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical compound [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 claims abstract description 81
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 79
- 229910052737 gold Inorganic materials 0.000 claims abstract description 79
- 230000004888 barrier function Effects 0.000 claims abstract description 74
- 229910000679 solder Inorganic materials 0.000 claims abstract description 41
- 239000000126 substance Substances 0.000 claims abstract description 26
- 239000011095 metalized laminate Substances 0.000 claims abstract description 23
- 238000000151 deposition Methods 0.000 claims abstract description 12
- 238000010438 heat treatment Methods 0.000 claims abstract description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 145
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 86
- 229910052738 indium Inorganic materials 0.000 claims description 85
- 229910052759 nickel Inorganic materials 0.000 claims description 72
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 54
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 40
- 150000001875 compounds Chemical class 0.000 claims description 34
- 239000010936 titanium Substances 0.000 claims description 33
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 claims description 30
- 230000003647 oxidation Effects 0.000 claims description 30
- 238000007254 oxidation reaction Methods 0.000 claims description 30
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 29
- 229910052719 titanium Inorganic materials 0.000 claims description 29
- 229910052697 platinum Inorganic materials 0.000 claims description 27
- 229910052763 palladium Inorganic materials 0.000 claims description 20
- 150000003609 titanium compounds Chemical class 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 386
- 239000007788 liquid Substances 0.000 description 39
- 238000002844 melting Methods 0.000 description 20
- 230000008018 melting Effects 0.000 description 20
- 238000006243 chemical reaction Methods 0.000 description 18
- 239000012071 phase Substances 0.000 description 16
- 239000000463 material Substances 0.000 description 15
- 238000001465 metallisation Methods 0.000 description 11
- 150000002739 metals Chemical class 0.000 description 9
- 238000009736 wetting Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 6
- 229910045601 alloy Inorganic materials 0.000 description 5
- 239000000956 alloy Substances 0.000 description 5
- 238000007707 calorimetry Methods 0.000 description 5
- 238000005476 soldering Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 4
- 239000000155 melt Substances 0.000 description 4
- 238000001816 cooling Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000005693 optoelectronics Effects 0.000 description 3
- 238000010587 phase diagram Methods 0.000 description 3
- 239000007790 solid phase Substances 0.000 description 3
- 238000005496 tempering Methods 0.000 description 3
- 229910000846 In alloy Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- LUEOXCMCHCWXHI-UHFFFAOYSA-N [In].[Sn].[Au] Chemical compound [In].[Sn].[Au] LUEOXCMCHCWXHI-UHFFFAOYSA-N 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 2
- 238000005324 grain boundary diffusion Methods 0.000 description 2
- 239000002346 layers by function Substances 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000012876 carrier material Substances 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 230000005525 hole transport Effects 0.000 description 1
- 238000010309 melting process Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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Abstract
Description
A)半導体チップを準備するステップ。
B)はんだ金属積層体を半導体チップの上に被着するステップ。
C)基板を準備するステップ。好適には、この基板はリードフレームである。
D)金属化積層体を基板の上に被着するステップ。
E)半導体チップをはんだ金属積層体と金属化積層体とを介して基板の上に被着するステップ。特に、この被着は、当該被着後、金属化積層体とはんだ金属積層体とが基板と半導体チップとの間に位置するように行われる。
F)半導体チップを基板の上に固定するために、方法ステップE)で生成されたアレイを加熱するステップ。特に、方法ステップF)では、金属化積層体とはんだ金属積層体とから化合物積層体が形成される。
2 はんだ金属積層体
3 基板またはリードフレーム
4 金属化積層体
5 化合物積層体
2a 第1の金属層
2b バリア層
2c 第2の金属層
2d 第2のバリア層
2e 酸化保護層
4a 第1の層
4b 第2の層
4c 第3の層
5a 第1の金属間層
5b 第2の金属間層
5c 第3の金属間層
100 電子構成素子
T 温度
℃ 摂氏温度
at% 原子パーセント
Gew% 重量パーセント
Claims (15)
- 半導体チップ(1)を基板(3)の上に固定する方法であって、
以下の方法ステップ、すなわち、
A)半導体チップ(1)を準備するステップと、
B)はんだ金属積層体(2)を前記半導体チップ(1)の上に被着するステップと、
C)基板(3)を準備するステップと、
D)金属化積層体(4)を前記基板(3)の上に被着するステップと、
E)前記半導体チップ(1)を前記はんだ金属積層体(2)と前記金属化積層体(4)とを介して前記基板(3)の上に被着するステップと、
F)前記半導体チップ(1)を前記基板(3)の上に固定するために、前記方法ステップE)で生成されたアレイを加熱するステップと、を含み、
前記はんだ金属積層体(2)は、
−インジウムスズ合金を含む第1の金属層(2a)と、
−前記第1の金属層(2a)の上方に配置されたバリア層(2b)と、
−前記バリア層(2b)と前記半導体チップ(1)との間に配置された金を含む第2の金属層(2c)と、を含み、
前記第2の金属層(2c)の金の物質量は、前記第1の金属層(2a)のスズの物質量よりも多い、方法。 - 前記第2の金属層(2c)の金の物質量は、前記第1の金属層(2a)のスズの物質量よりも少なくとも2倍多い、請求項1記載の方法。
- 前記金属化積層体(4)は、前記基板(3)の上方に配置されたニッケルを含む第1の層(4a)を含む、請求項1または2記載の方法。
- 前記バリア層(2b)は、ニッケル、チタン、白金またはチタン化合物を含む、請求項1から3までのいずれか1項記載の方法。
- 前記方法ステップF)において、前記基板(3)と前記半導体チップ(1)との間に化合物積層体(5)が形成され、該化合物積層体(5)は、
−インジウム、スズ、およびニッケルを含む第1の金属間層(5a)と、
−インジウム、スズ、およびニッケルを含むか、インジウム、スズ、およびチタンを含むか、インジウム、スズ、およびチタン化合物を含むか、またはインジウム、スズ、および白金を含む第2の金属間層(5b)と、
−インジウム、スズ、および金を含む第3の金属間層(5c)と、を含む、請求項1から4までのいずれか1項記載の方法。 - 前記金属化積層体(4)は、前記基板(3)の上方に配置されたニッケルを含む第1の層(4a)と、該第1の層(4a)の上方に配置されたパラジウムを含む第2の層(4b)と、該第2の層(4b)の上方に配置された金を含む第3の層(4c)と、を含む、請求項1から5までのいずれか1項記載の方法。
- 前記方法ステップE)において、前記半導体チップ(1)は、前記はんだ金属積層体(2)の前記第1の金属層(2a)が前記金属化積層体(4)の前記第3の層(4c)の上に被着されるように、前記基板(3)の上に被着される、請求項6記載の方法。
- 前記バリア層(2b)は、5nm以上〜200nm以下の間の層厚さを有する、請求項1から7までのいずれか1項記載の方法。
- 前記インジウムスズ合金は、式InxSn1−xを有し、ただし0.04≦x≦0.2、好適には0.06≦x≦0.18、特に好適には0.08≦x≦0.16である、請求項1から8までのいずれか1項記載の方法。
- 前記第1の金属層(2a)は、750nm以上〜3μmの間の層厚さを有する、請求項1から9までのいずれか1項記載の方法。
- 前記第2の金属層(2c)は、500nm以上〜2μmの間の層厚さを有する、請求項1から10までのいずれか1項記載の方法。
- 前記はんだ金属積層体(2)は、金および第2のバリア層(2d)を含む酸化保護層(2e)を含み、前記第1の金属層(2a)は、前記第2のバリア層(2d)の上方に配置され、該第2のバリア層(2d)は、前記酸化保護層(2e)の上方に配置されている、請求項1から11までのいずれか1項記載の方法。
- 前記半導体チップ(1)は、ケイ素を含む支持体を含む、請求項1から12までのいずれか1項記載の方法。
- 基板(3)と、該基板(3)の上方に配置された半導体チップ(1)とを含む電子構成素子(100)であって、
前記基板(3)と前記半導体チップ(1)との間に化合物積層体(5)が配置されており、
前記化合物積層体(5)は、
−インジウム、スズ、およびニッケルを含む第1の金属間層(5a)と、
−インジウム、スズおよびチタン化合物を含むか、インジウム、スズ、およびニッケルを含むか、インジウム、スズ、および白金を含むか、またはインジウム、スズ、およびチタンを含む第2の金属間層(5b)と、
−インジウム、スズ、および金を含む第3の金属間層(5c)と、を含み、
前記第3の金属間層(5c)内で、金の物質量は、スズの物質量よりも多い、電子構成素子(100)。 - 前記第3の金属間層(5c)は、ゼータ層の金スズ合金を含む、請求項14記載の電子構成素子(100)。
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