CN110770894B - 用于将半导体芯片固定在基板上的方法和电子器件 - Google Patents
用于将半导体芯片固定在基板上的方法和电子器件 Download PDFInfo
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- CN110770894B CN110770894B CN201880039332.7A CN201880039332A CN110770894B CN 110770894 B CN110770894 B CN 110770894B CN 201880039332 A CN201880039332 A CN 201880039332A CN 110770894 B CN110770894 B CN 110770894B
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- indium
- tin
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- gold
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 80
- 239000000758 substrate Substances 0.000 title claims abstract description 79
- 238000000034 method Methods 0.000 title claims abstract description 63
- 229910052751 metal Inorganic materials 0.000 claims abstract description 150
- 239000002184 metal Substances 0.000 claims abstract description 150
- 229910001128 Sn alloy Inorganic materials 0.000 claims abstract description 101
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 99
- 229910052718 tin Inorganic materials 0.000 claims abstract description 99
- 239000010931 gold Substances 0.000 claims abstract description 92
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 82
- 229910052737 gold Inorganic materials 0.000 claims abstract description 82
- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical compound [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 claims abstract description 82
- 230000004888 barrier function Effects 0.000 claims abstract description 71
- 238000001465 metallisation Methods 0.000 claims abstract description 52
- 229910000679 solder Inorganic materials 0.000 claims abstract description 40
- 238000010438 heat treatment Methods 0.000 claims abstract description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 143
- 239000011135 tin Substances 0.000 claims description 123
- 229910052738 indium Inorganic materials 0.000 claims description 86
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 86
- 229910052759 nickel Inorganic materials 0.000 claims description 71
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 56
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 38
- 239000010936 titanium Substances 0.000 claims description 32
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 28
- 230000003647 oxidation Effects 0.000 claims description 28
- 238000007254 oxidation reaction Methods 0.000 claims description 28
- 229910052697 platinum Inorganic materials 0.000 claims description 28
- 229910052719 titanium Inorganic materials 0.000 claims description 28
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 claims description 20
- 229910052763 palladium Inorganic materials 0.000 claims description 19
- 150000003609 titanium compounds Chemical class 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 488
- 239000007788 liquid Substances 0.000 description 38
- 238000002844 melting Methods 0.000 description 23
- 230000008018 melting Effects 0.000 description 22
- 238000006243 chemical reaction Methods 0.000 description 18
- 239000000463 material Substances 0.000 description 17
- 239000012071 phase Substances 0.000 description 16
- 238000009736 wetting Methods 0.000 description 10
- 150000002739 metals Chemical class 0.000 description 9
- 239000011241 protective layer Substances 0.000 description 7
- 229910045601 alloy Inorganic materials 0.000 description 5
- 239000000956 alloy Substances 0.000 description 5
- 150000001875 compounds Chemical class 0.000 description 5
- 238000005476 soldering Methods 0.000 description 5
- 238000010587 phase diagram Methods 0.000 description 4
- 238000001816 cooling Methods 0.000 description 3
- 230000005670 electromagnetic radiation Effects 0.000 description 3
- 239000000155 melt Substances 0.000 description 3
- 230000005693 optoelectronics Effects 0.000 description 3
- 239000007790 solid phase Substances 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 2
- 238000001382 dynamic differential scanning calorimetry Methods 0.000 description 2
- 238000005324 grain boundary diffusion Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 239000002346 layers by function Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000012876 carrier material Substances 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 230000005525 hole transport Effects 0.000 description 1
- 230000000977 initiatory effect Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000010309 melting process Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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- H—ELECTRICITY
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Abstract
提出一种用于将半导体芯片(1)固定在基板(3)上的方法。方法包括如下方法步骤:A)提供半导体芯片(1),B)将焊料金属层序列(2)施加到半导体芯片(1)上,C)提供基板(3),D)将金属化层序列(4)施加到基板(3)上,E)将半导体芯片(1)经由焊料金属层序列(2)和金属化层序列(4)施加到基板(3)上,F)加热通过E)产生的用于将半导体芯片(1)固定在基板(3)上的装置,其中焊料金属层序列(2)包括:‑包含铟锡合金的第一金属层(2a),‑在第一金属层(2a)之上设置的阻挡层(2b)和‑设置在阻挡层(2b)和半导体芯片(1)之间的包括金的第二金属层(2c),其中在第二金属层中的金的物质量比在第一金属层中的锡的物质量更大。
Description
技术领域
本发明涉及一种用于将半导体芯片固定在基板上的方法和一种电子器件。
背景技术
为了将半导体芯片与基板、例如导线框架连接,在制造电子器件时通常将半导体芯片焊接到基板上。由于半导体芯片和基板的材料之间在热膨胀特性的差异,在从焊接温度冷却至室温时在由半导体芯片和基板构成的复合件中产生应力。所述应力可以在电子器件的机械负荷下造成例如在半导体芯片的载体材料中引发裂纹。例如,将金锡焊料用于将半导体芯片焊接到基板上。在所述焊料中,焊接温度处于300℃的范围内。由于高的焊接温度和不同的热膨胀性能,在冷却由基板和半导体芯片构成的复合件时产生显著的热感应的机械应力。所述机械应力在器件进一步的机械负荷下可能造成焊接连接的失效或造成在基板或焊接连接中引发裂纹。
发明内容
本发明的至少一个实施方式的目的是,提出一种用于将半导体芯片固定在基板上的方法,所述方法相对于现有技术改进。另一目的在于提供一种电子器件。
所述目的尤其通过具有本发明的特征的用于将半导体芯片固定在基板上的方法和电子器件来实现。优选的改进方案是下面描述的主题。
提出一种用于将半导体芯片固定在基板上的方法。所述方法包括如下步骤,优选以给出的顺序:
A)提供半导体芯片。
B)将焊料金属层序列施加到半导体芯片上。
C)提供基板。优选基板是导线框架。
D)将金属化层序列施加到基板上。
E)将半导体芯片经由焊料金属层序列和金属化层序列施加到基板上。尤其施加进行成,使得在施加之后,金属化层序列和焊料金属层序列位于基板和半导体芯片之间。
F)加热通过E)产生的用于将半导体芯片固定在基板上的装置。尤其在步骤F)中由金属化层序列和焊料金属层序列形成连接层序列。
将一个层或一个元件设置或施加在另一层或另一元件“上”或“之上”在此情况下,在此和在下文中可以意味着,将一个层或一个元件直接地以直接机械和/或电接触的方式设置在另一层或另一元件上。此外,这也可以意味着,一个层或一个元件间接地设置在另一层或另一元件上或之上。在此,其他层和/或元件于是可以设置在一个层或另一层之间或者设置在一个元件或另一元件之间。
一个层或一个元件设置在两个另外的层或元件“之间”,在此和在下文中可以意味着,一个层或一个元件设置成直接地与两个另外的层或元件中的一个直接机械和/或电接触或者间接接触,并且与两个另外的层或元件中的另一个直接机械和/或电接触或者间接接触。在此,在间接接触时于是可以在一个层和两个另外的层中的至少一个之间或在一个元件和两个另外的元件中的至少一个之间设置其他层和/或元件。
根据至少一个实施方式,焊料金属层序列包括第一金属层、在第一金属层之上设置的阻挡层和在阻挡层和半导体芯片之间设置的第二金属层。焊料金属层序列也可以由第一金属层、阻挡层和第二金属层构成。
根据至少一个实施方式,焊料金属层序列包括:包含铟锡合金的第一金属层;在第一金属层之上设置的阻挡层和设置在阻挡层和半导体芯片之间的第二金属层,所述第二金属层包括金。优选地,在方法步骤E)之后,第一金属层在金属化层序列之上设置,阻挡层在第一金属层之上设置并且第二金属层在阻挡层之上设置。优选地,第一金属层由铟锡合金构成。优选地,第二金属层由金构成。
根据至少一个实施方式,为了产生第二金属层可以施加铟锡合金或者铟和锡可以单独地沉积。例如,首先沉积由锡构成的层,随后沉积由铟构成的层并且随后再次沉积由锡构成的层。铟和锡在室温下已经发生反应以形成合金。由此,在单独地沉积锡和铟时,在室温下从而直接在沉积之后已经至少部分地,优选完全地形成铟锡合金。如果铟锡合金仅部分地形成,那么在第二金属层中除了所述铟锡合金以外也还存在铟和锡。第二金属层也可以由铟锡合金或者铟锡合金和铟和锡构成。
根据至少一个实施方式,第二金属层的金的物质量大于第一金属层的锡的物质量。这证实为对于将半导体芯片接合在基板上而言是特别有利的。因此,在所产生的电子器件中,可以确保半导体芯片在基板上的固定的且持续的接合。尤其,在方法步骤F)中在连接层序列之内形成第三金属间层,所述第三金属间层包括至少一种式为Au1-ySny的金锡合金,其中0.10≤y≤0.185。更尤其优选地,第三金属间层包括Zeta(ζ)相的金锡合金。因此,形成第三金属间层,在所述第三金属间层中金的物质量大于铟的物质量。这种第三金属间层在其机械特性方面证实为是特别有利的并且与具有较高锡含量的金锡合金相比尤其是更能承受负荷的、更延展的且脆性明显更小。例如,Zeta相的金锡合金与Delta(δ)相的金锡合金相比是明显更能承受负荷的且更延展的。
用n表示的物质量间接地说明物质部分的粒子数。物质量n能由n=M/m计算,其中M说明以g/mol为单位的摩尔质量并且m说明以g为单位的重量。物质量是本领域技术人员已知的。
根据至少一个实施方式,在第二金属层中的金的物质量是在第一金属层中的锡的物质量的至少两倍、优选至少三倍或四倍大。在此,金的物质量可以是锡的物质量的最大七倍大。
根据至少一个实施方式,在第一金属层中的铟与锡的物质量的比例位于0.04比0.96和0.2比0.8之间,优选位于0.06比0.94和0.18比0.82之间,尤其优选位于0.08比0.92和0.16比0.84之间,其中包括边界值。
根据至少一个实施方式,第二金属层的铟锡合金具有式InxSn1-x,其中0.04≤x≤0.2,优选0.06≤x≤0.18,特别优选0.08≤x≤0.16。优选地,第二金属层由式为InxSn1-x的铟锡合金构成,其中0.04≤x≤0.2。铟锡合金的这种组成已经证实为是特别有利的。由于小的铟份额,熔点与纯的锡相比降低,由此可以将方法步骤F)中的温度保持得小。此外,借助x=0.2的最大铟份额可以确保,铟锡合金不在将半导体芯片施加到基板上之前已经在可选的其他方法步骤中熔化。令人意外地已经证实的是,金属化层序列的润湿特性在不超过铟含量x=0.2时是最好的。
阻挡层设立用于,将第一金属层的金属,即铟和锡,首先与第二金属层的金分离,因为具有金的铟锡合金在室温下已经产生高熔点的相。因此,第一和第二金属层首先必须彼此分离。在达到铟锡合金的熔化温度之后,也必须将液态铟和液态锡或液态铟锡合金和第二金属层的金在方法步骤F)中彼此分离。这通过阻挡层确保。阻挡层也可以称作为暂时的扩散阻挡。阻挡层优选整面地设置在第一金属层和第二金属层之间。尤其,第一金属层和第二金属层不具有共同的边界面。
根据至少一个实施方式,阻挡层包含镍、钛或铂。镍、钛或铂可以是金属或是这些金属的化合物。钛化合物例如可以是TiyWy-1或TizNz-1。优选地,阻挡层包括金属镍、钛或铂,特别优选镍或钛,或者由其构成。这些金属或化合物是特别有利的,因为这些金属或化合物在铟锡合金在方法步骤F)中熔化之后仅缓慢地并且延迟地与液态铟和锡或液态铟锡合金发生反应,进而确保金属化层序列由液态铟和锡或液态铟锡合金充分地润湿。
根据至少一个实施方式,在方法步骤F)中将通过方法步骤E)产生的装置加热直至240℃,优选200℃,特别优选190℃。在所述温度下,铟锡合金已经熔化。由于所述相对低的焊接温度,在冷却由基板和半导体芯片构成的装置时可以减小热感应的机械应力,尤其与使用纯的AuSn焊料相比。由此,预防在机械负荷下半导体芯片从基板剥离并且在机械应力下不产生或几乎不产生裂纹。
式为InxSn1-x,其中0.04≤x≤0.2的铟锡合金尤其可以具有在190℃和225℃之间的熔点。熔点描述铟锡合金完全融化的温度(液相温度)。熔化过程尤其可以在170℃和200℃的温度之间已经开始(固相温度)。
通过使用铟锡合金InxSn1-x,其中0.04≤x≤0.2,与纯锡相比熔化温度减小。在x=0.04的铟份额下,熔化温度已经位于224℃,由此所述熔化温度明显小于纯锡的为232℃的熔化温度。铟含量选择为越高,熔化温度就越低,直至达到Sn0.48In0.52和大约121℃的熔化温度的共晶体。发明人在此已确定,铟锡合金的熔化温度不应低于180℃,因为否则存在如下风险:所述铟锡合金在具有施加的焊料金属层序列的半导体芯片的其他工艺步骤,如层压或分离工艺中,已经熔化并且与邻接的层发生反应。这应当被阻止,因为否则不再能确保半导体芯片在基板上的固定的且持久的接合。通过在第二金属层中将铟少量添加给锡,其中铟与锡的比例在0.04比0.96和0.20比0.80之间,其中包括边界值,一方面可以将在方法步骤F)中的加热温度保持得比在已知的焊接方法中更小。这造成由于在半导体芯片的材料和基板的材料之间的热膨胀性能的差异引起的应力减小。另一方面可以确保,第二金属层的铟锡合金在方法步骤E)或F)之前不熔化从而提前开始与邻接的层的不期望的反应。
在方法步骤F)中加热时,铟锡合金开始熔化。在此,将金属化层序列的表面用液态铟和液态锡或液态铟锡合金润湿,并且与金属化层序列的材料发生反应。同时,铟和锡或铟锡合金与阻挡层的材料,即尤其镍、钛或铂发生反应。由于存在阻挡层,铟和锡或铟锡合金与第二金属层的金的反应首先延迟。由此确保,金属化层序列充分地由液态铟和液态锡或者铟锡合金润湿。这在铟和锡或铟锡合金立即与第二金属层的金发生反应时不能被确保,因为所述反应可能产生高熔相并且铟和锡或铟锡合金不够长时间地是液态,以便确保金属化层序列的充分润湿和与金属化层序列的材料的反应。令人意外地,在第二金属层中的铟与锡的比例在0.04比0.96和0.20比0.80之间时,润湿是非常好的,其中包括边界值。
根据至少一个实施方式,在方法步骤F)中从铟和锡或铟锡合金与阻挡层的材料,尤其镍、钛或铂的反应中形成第二金属间层,所述第二金属间层包括铟、锡和阻挡层的材料或者由其构成。同时,从铟和锡或铟锡合金与金属化层序列的材料的反应中形成第一金属间层。尤其,在第一和第二金属间层之间还设置有第一金属层。剩余的液态铟和锡或液态的铟锡合金穿过形成的第二金属间层扩散到第二金属层中并且与金发生反应以形成高熔点的固相,其在此和在下文中称作为第三金属间层。第三金属间层包括铟、锡和金或者由其构成。通过根据本发明所使用的在第二金属层中比锡的物质量更高物质量的金,形成第三金属间层,在所述第三金属间层中金的物质量大于铟的物质量。
根据至少一个实施方式,形成包括至少一种金锡合金的第三金属间层,所述金锡合金的式为Au1-ySny,其中0.10≤y≤0.185。更特别优选地,形成Zeta相的金锡合金。除了式为Au1-ySny,其中0.10≤y≤0.185的金锡合金或Zeta相的金锡合金以外,可以形成其他金锡合金和/或金锡铟合金。更特别优选的是,第三金属间层的主要组成部分是式为Au1-ySny,其中0.10≤y≤0.185的金锡合金或Zeta相的金锡合金。尤其,第三金属间层不具有或几乎不具有如下合金,所述合金具有低于280℃的熔点。这种第三金属间层在其机械特性方面证实为是特别有利的,并且与具有更高锡含量或更低金含量的金锡合金相比尤其是更能承受负荷的、更延展的且脆性明显更小的。通过所述方法制造的电子器件由此相对于机械负荷是特别鲁棒的。
根据至少一个实施方式,在方法步骤F)之后进行方法步骤G):G)在200℃和260℃之间,包含边界值的温度下将通过F)产生的装置退火。所述退火优选可以执行1小时至八小时。通过退火可以有效地禁止在第三金属间层之内形成熔点低于280℃的的化合物或合金。
根据至少一个实施方式,在方法步骤F)中形成在基板和半导体芯片之间的连接层序列。经由连接层序列,半导体芯片固定在基板上。连接层序列包括第一金属间层、第二金属间层和第三金属间层。
根据至少一个实施方式,第一金属间层在基板之上设置,第二金属间层在第一金属间层之上设置并且第三金属间层在第二金属间层之上设置。
根据至少一个实施方式,金属化层序列包括设置在基板之上的第一层,所述第一层包括镍或由镍构成。金属化层序列也可以由第一层构成。在方法步骤F)中形成的第一金属间层可以根据本实施方式包括铟、锡和镍或由这些金属构成。因此,根据本实施方式,第一和第二金属间层包含铟、锡和镍或由这些金属构成。
根据至少一个实施方式,金属化层序列包括:设置在基板之上的第一层,所述第一层包括镍;和设置在第一层之上的第二层,所述第二层包括钯。第二层也可以由钯构成。
根据至少一个实施方式,金属化层序列包括设置在第一或第二层之上的第三层,所述第三层包括金。第三层也可以由金构成。
根据至少一个实施方式,金属化层序列由第一层和第三层构成或者由第一层、第二层和第三层构成。
根据至少一个实施方式,在方法步骤E)中将半导体芯片施加在基板上,使得焊料金属层序列的第一金属层施加到金属化层序列的第三层上。在方法步骤F)中形成的第一金属间层根据本实施方式可以包括铟、锡、金、钯和镍或由这些金属构成。
根据至少一个实施方式,阻挡层具有在5nm和200nm之间,包含边界值的层厚度。借助所述层厚度,可以确保铟和锡或铟锡合金与第二金属层的金的反应的足够的延迟,以便金属化层序列充分地由液态铟锡合金润湿。
根据至少一个实施方式,第一金属层具有在750nm和3μm之间,包含边界值的层厚度。
尤其,焊料金属层序列的和金属化层序列的各个层的层厚度彼此协调,使得在方法步骤F)中铟和锡或铟锡合金尽可能完全地反应完,并且确保,液态铟锡合金与焊料金属层序列的第二金属层的金和金属化层序列的第一层的镍发生反应。由此,优选地,在方法步骤F)之后,第一金属间层、第二金属间层和第三金属间层设置在半导体芯片和基板之间。
根据至少一个实施方式,焊料金属层序列的第二金属层具有在500nm和2μm之间,包含边界值的层厚度。
根据至少一个实施方式,金属化层序列的第一层具有在2μm和4μm之间,包含边界值,例如为3μm的层厚度。
根据至少一个实施方式,金属化层序列的第二层具有在10nm和20nm之间,包含边界值的层厚度。
根据至少一个实施方式,焊料金属层序列包括包含金的防氧化保护层和第二阻挡层。第一金属层在此在第二阻挡层之上设置并且第二阻挡层在防氧化保护层之上设置。防氧化保护层用于,保护第一金属层防止氧化。铟和/或锡的氧化或部分氧化造成金属化层序列的差的润湿从而应当被避免。尤其,铟是非常氧化敏感的。所述实施方式在如下情况下是尤其有利的,包括焊料金属层序列的半导体芯片在施加到基板上之前,即在方法步骤E)之前存放一定时间。
根据至少一个实施方式,第二阻挡层包含镍、钛或铂。镍、钛或铂可以是金属或是这些金属的化合物。钛化合物例如可以是TiyWy-1或是TizNz-1。优选地,第二阻挡层包括金属镍、钛或铂,特别优选包括钛,或由其构成。第二阻挡层用于,在室温下并且尤其在半导体芯片存放期间防止铟锡合金与防氧化保护层的金之间的反应。第二阻挡层的金属或化合物与铟锡合金在方法步骤F)中仅缓慢地发生反应。为了仍然确保金属化层序列由液态铟锡合金充分地润湿,第二阻挡层与阻挡层相比优选具有明显更小的层厚度。为了在方法步骤F)中确保金属化层序列的充分润湿,第二阻挡层尤其具有在3nm和10nm之间,包含边界值,优选在5nm和10nm之间,包含边界值的层厚度。阻挡层根据本实施方式尤其可以具有在20nm和200nm之间,包含边界值的层厚度。
根据至少一个实施方式,防氧化保护层具有在50nm和100nm之间,包含边界值的层厚度。在低于50nm的情况下,所述防氧化保护层是不够严密的,以便确保充分地保护第一金属层防止氧化。高于100nm的层厚度应当被避免,以便确保金属化层序列的充分润湿。
在方法步骤F)中加热时,铟锡合金开始熔化。在此,所述铟锡合金首先与第二阻挡层的材料,即尤其镍、钛或铂发生反应,并且紧接着与防氧化保护层的金发生反应。紧接着进行金属化层序列由液态铟锡合金的润湿。为了确保充分的润湿,所述润湿必须在铟锡合金与第二金属层的金反应之前开始。这尤其可以通过选择第二阻挡层的、防氧化保护层的和阻挡层的层厚度进行。特别优选地,阻挡层具有在20nm和200nm或100nm之间,包含边界值的层厚度,第二阻挡层具有在5nm和10nm之间,包含边界值的层厚度,并且防氧化保护层具有在50nm和100nm之间,包含边界值的层厚度。
根据至少一个实施方式,在方法步骤F)中从铟和锡或铟锡合金与阻挡层的材料,尤其镍、钛或铂的反应中形成第二金属间层,所述第二金属间层包括铟、锡和阻挡层的材料或由其构成。同时,第一金属间层从铟和锡或铟锡合金与第二阻挡层的材料、金属化层序列和防氧化保护层的金的反应中形成。尤其,在第一和第二金属间层之间还设置有第一金属层。剩余的液态铟和锡或液态的铟锡合金穿过形成的第二金属间层扩散到第二金属层中并且与金发生反应以形成高熔点的固相,以形成第三金属间层。第三金属间层包括铟、锡和金或由其构成。
根据至少一个实施方式,金属化层序列的第三层具有在3nm和5nm之间,包含边界值的层厚度。第三层应当不超过5nm的层厚度,以便确保,由铟锡合金与金形成的高熔相不变得过厚从而仍然可以确保,液态铟锡合金推进至金属化层序列的第一层的镍并且与其发生反应。
根据至少一个实施方式,基板,尤其导线框架可以包括铜。经由导线框架可以电接触半导体芯片。
根据至少一个实施方式,半导体芯片是具有有源层的层序列,所述有源层设立用于发射电磁辐射。
将“层序列”在该上下文中理解为包括多于一层的层序列,例如p型掺杂的和n型掺杂的半导体层的序列,其中所述层上下相叠地设置并且其中包含至少一个有源层,所述有源层发射电磁辐射。
层序列可以构成为外延层序列或构成为具有外延层序列的发射辐射的半导体芯片,即构成为外延生长的半导体层序列。在此,层序列例如可以基于InGaAlN构成。基于InGaAlN的半导体芯片和半导体层序列尤其是如下半导体芯片和半导体层序列,其中外延制造的半导体层序列具有由不同单层构成的层序列,所述层序列包含至少一个单层,所述单层具有出自III-V族化合物半导体材料体系InxAlyGa1-x-yN的材料,其中0≤x≤1,0≤y≤1并且x+y≤1。具有基于InGaAlN的至少一个有源层的半导体层序列例如可以发射在紫外至蓝色的波长范围内的电磁辐射。
有源半导体层序列除了有源层以外可以包括其他功能性层和功能性区域,例如p型掺杂的或n型掺杂的载流子传输层,即电子或空穴传输层,未掺杂的或p型掺杂的或n型掺杂的限制层、包覆层或波导层、阻挡层、平坦化层、缓冲层、保护层和/或电极以及由其构成的组合。此外,例如可以在半导体层序列的背离生长衬底的侧上施加有一个或多个镜层。在此所描述的结构、有源层或其他功能性层和相关区域,对于本领域技术人员尤其在构造、功能和结构方面是已知的从而在该处不进行进一步阐述。
提出一种电子器件。电子器件优选借助如结合一个或多个上述实施方式所给出的方法之一制造。因此,用于方法的所有特征也对于器件公开并且反之亦然。
根据至少一个实施方式,器件是用于产生辐射或光的光电子器件。
提出一种包括基板和设置在基板之上的半导体芯片的电子器件。在半导体芯片和基板之间设置有连接层序列。尤其,半导体芯片经由连接层序列固定在基板上。
根据至少一个实施方式,连接层序列包括第一金属间层、第二金属间层和第三金属间层。尤其,第一金属间层设置在基板之上,第二金属间层设置在第一金属间层之上并且第三金属间层设置在第二金属间层之上。连接层序列也可以由第一、第二和第三金属间层构成。
根据至少一个实施方式,包括镍或由镍构成的第一层设置在基板和连接层序列之间,尤其设置在基板和第一金属间层之间。
根据至少一个实施方式,连接层序列的第一金属间层包括锡、铟和镍;锡、铟、镍和钯;锡、铟、镍、钯和金或锡、铟、镍和金或由这些金属构成。
根据至少一个实施方式,连接层序列的第一金属间层包括锡、铟、金和镍;锡、铟、镍、金和钯;锡、铟、镍、钯和金或锡、铟、镍和金或由这些金属构成。所述实施方式在如下情况下是优选的:焊料金属层序列包括包含镍的第二阻挡层和防氧化保护层。
根据至少一个实施方式,连接层序列的第一金属间层包括锡、铟、金、钛和镍;锡、铟、金、钛、镍和钯;锡、铟、金、钛、镍和钯或锡、铟、镍、金和钛或由这些金属构成。所述实施方式在如下情况下是优选的:焊料金属层序列包括包含钛的第二阻挡层和防氧化保护层。
根据至少一个实施方式,连接层序列的第一金属间层包括锡、铟、金、铂和镍;锡、铟、金、铂、镍和钯;锡、铟、金、铂、镍和钯或锡、铟、镍、金和铂或由这些金属构成。所述实施方式在如下情况下是优选的:焊料金属层序列包括包含铂的第二阻挡层和防氧化保护层。
根据至少一个实施方式,连接层序列的第一金属间层包括锡、铟、金、钛化合物和镍;锡、铟、金、钛化合物、镍和钯;锡、铟、金、钛化合物、镍和钯或锡、铟、镍、金和钛化合物或由这些金属构成。所述实施方式在如下情况下是优选的:焊料金属层序列包括包含钛化合物的第二阻挡层和防氧化保护层。
根据至少一个实施方式,第二金属间层包括锡、铟和钛化合物;锡、铟和镍;锡、铟和铂或锡、铟和钛,或者由锡、铟和钛化合物;锡、铟和镍;锡、铟和铂或锡、铟和钛构成。
根据至少一个实施方式,连接层序列的第三金属间层包括铟、锡和金或由这些金属构成。尤其,金的物质量大于锡的物质量。
根据至少一个实施方式,第三金属间层包括至少一种式为Au1-ySny的金锡合金,其中0.10≤y≤0.185。更特别优选地,形成Zeta相的金锡合金。除了式为Au1-ySny,其中0.10≤y≤0.185的金锡合金或Zeta相的金锡合金以外,其他金锡合金和/或金锡铟合金可以包含在第三金属间层中。更特别优选的是,第三金属间层的主要组成部分是式为Au1-ySny的金锡合金,其中0.10≤y≤0.185或Zeta相的金锡合金。这种第三金属间层在其机械特性方面已经证实为是特别有利的,并且与具有较高锡含量、或较低金含量的金锡合金相比尤其是更能承受负荷的、更延展的且脆性明显更小的。由此,电子器件相对于机械负荷是特别稳定的。
根据至少一个实施方式,在半导体芯片和连接层序列之间设置有附着层。附着层可以是一个或多个金属层。金属例如可以选自:铂、钛和金。
根据至少一个实施方式,半导体芯片设置在基板上。基板例如可以是蓝宝石基板。
根据至少一个实施方式,半导体芯片设置在载体上。载体例如可以是包括硅或由硅构成的载体。
附图说明
其他优点、有利的实施方式和改进方案从下面结合附图所描述的实施例中得出。在此,相同的和相同类型的或起相同作用的元件设有相同的附图标记。附图和在附图中示出的元件彼此间的大小关系不视为是合乎比例的。更确切地说,为了更好的可视性和/或为了更好的理解夸大地或简化地示出个别元件。
图1A至1D和2A至2D示意地示出用于制造电子器件的方法。
图3和4示出动态的差式扫描量热图(Differenzkalometrie-Diagramme)。
图5示出铟锡合金的相图。
图6示出金锡合金的相图。
具体实施方式
图1A示出半导体芯片1,在所述半导体芯片之上设置有焊料金属层序列2。焊料金属层序列包括第一金属层2a、在第一金属层2a之上设置的阻挡层2b和在阻挡层2b之上设置的第二金属层2c。第一金属层2a包括式为InxSn1-x的铟锡合金或由其构成,其中0.04≤x≤0.2。阻挡层2b由镍、钛或铂构成并且第二金属层2c由金构成。第二金属层2c的金的物质量大于第一金属层2a的锡的物质量。第一金属层2a具有在750nm和3μm之间,包含边界值的层厚度,阻挡层具有在5nm和200nm之间,包含边界值的层厚度,并且第二金属层2c具有在500nm至2μm之间,包含边界值的层厚度。此外,图1A示出基板3,在所述基板之上设置有金属化层序列4。金属化层序列4由在基板3之上设置的、包括镍或由镍构成的第一层4a,在第一层4a之上设置的、包括钯或由钯构成的第二层4b和在第二层4b之上设置的、包括金或由金构成的第三层4c构成。在此,第一层4a具有例如3μm的层厚度。第二层4b具有在10nm和20nm之间,包含边界值的层厚度并且第三层4c具有在3nm和5nm之间,包含边界值的层厚度。尤其,基板3是导线框架。
图1B示出如下装置,其中半导体芯片1设置在焊料金属层序列2之上并且金属化层序列4设置在基板3上。
通过将在图1B中示出的装置加热到大约200℃的温度,在第一金属层2a中的铟锡合金熔化。液态铟锡合金润湿金属化层序列4的第三层4c。液态铟锡合金与阻挡层2b的镍、铂或钛发生反应并且如在图1C中所示出的那样形成第二金属间层5b。同时,液态铟或液态铟锡合金与第三层4c的金、第二层4b的铂和第一层4a的镍发生反应并且形成第一金属间层5a。在此,如所示出那样,第一层4a的镍不能完全与液态铟锡合金发生反应,使得在层厚度方面减小的第一层4a保留。然而也可能的是,镍完全与液态铟锡合金发生反应从而不再存在层4a。
保留在第一金属层4a中的液态铟锡合金借助于晶界扩散穿过第二金属间层5b扩散至第二金属层2c并且在那里与金发生反应,以形成第三金属间层5c(参见图1D)。第三金属间层包括式为Au1-ySny的至少一种金锡合金,其中0.10≤y≤0.185,优选包括Zeta相的金锡合金。由此,通过方法制造的电子器件相对于机械负荷是特别稳定的。
在图1D中示出的电子器件100,尤其光电子器件100包括基板3、在基板3之上设置的第一层4a,所述第一层包括镍或由镍构成。在第一层之上设置有连接层序列5。连接层序列5包括第一金属间层5a、在第一金属间层5a之上设置的第二金属间层5b和在第二金属间层5b之上设置的第三金属间层5c。在连接层序列5之上,半导体芯片1固定在基板3上。
图2A示出半导体芯片1,在半导体芯片之上设置有焊料金属层序列2。焊料金属层序列2由防氧化保护层2e、在防氧化保护层2e之上设置的第二阻挡层2d、在第二阻挡层2d之上设置的第一金属层2a、在第一金属层2a之上设置的阻挡层2b和在阻挡层2b之上设置的第二金属层2c构成。防氧化保护层2e由金构成并且具有在50nm和100nm之间,包含边界值的层厚度。第二阻挡层2d由镍、钛或铂构成并且具有在3nm和10nm之间,包含边界值的层厚度。第一金属层2a包括式为InxSn1-x的铟锡合金或由其构成,其中0.04≤x≤0.2。阻挡层2b由镍、钛或铂构成并且第二金属层2c由金构成。第二金属层2c的金的物质量大于第一金属层2a的锡的物质量。第一金属层2a具有在750nm和3μm之间,包含边界值的层厚度;阻挡层具有在20nm和200nm之间,包含边界值的层厚度;并且第二金属层2c具有在500nm至2μm之间,包含边界值的层厚度。通过由金构成的防氧化保护层2e,保护第一金属层2a防止空气和湿气进入从而防止不期望的氧化。这使得焊料金属层序列所施加于的半导体芯片1是可存放的。防氧化保护层2e通过第二阻挡层2d与第一金属层2a分离,以便在室温下并且尤其在将半导体芯片1施加到基板3上之前已经防止防氧化保护层2e的金与第一金属层2a的铟锡合金的反应。此外,图2A示出基板3,尤其成形为导线框架的基板,在所述基板之上设置有金属化层序列4。金属化层序列4由设置在基板3之上的、包括镍或由镍构成的第一层4a,设置在第一层4a之上的、包括钯或由钯构成的第二层4b和设置在第二层4b之上的、包括金或由金构成的第三层4c构成。在此,第一层4a具有例如3μm的层厚度。第二层4b具有在10nm和20nm之间,包含边界值的层厚度,并且第三层4c具有在3nm和5nm之间,包含边界值的层厚度。
图2B示出如下装置,其中半导体芯片1设置在焊料金属层序列2之上并且金属化层序列4设置在基板3之上。在此,焊料金属层序列2的防氧化保护层2e设置在金属化层序列4的第三层4c之上。
通过将在图2B中示出的装置加热至大约200℃的温度,在第一金属层2a中的铟锡合金熔化。液态铟锡合金与第二阻挡层2d的镍、铂或钛,防氧化保护层2e的金发生反应,并且润湿金属化层序列4的第三层4c。液态铟锡合金与阻挡层2b的镍、铂或钛发生反应,并且如在图2C中所示出的那样,形成第二金属间层5b。同时,液态铟锡合金与第三层4c的金、第二层4b的钯和第一层4a的镍发生反应并且形成第一金属间层5a。在此,如所示出那样,第一层4a的镍能够不完全地与液态铟锡合金发生反应,使得保留层厚度减小的第一层4a。然而也可能的是,镍完全与液态铟锡合金发生反应从而不再存在层4a。
在第一金属层4a中保留的液态铟锡合金借助于晶界扩散穿过第二金属间层5b扩散至第二金属层2c并且在那里与金发生反应,以形成第三金属间层5c(参见图2D)。在此,形成式为Au1-ySny的金锡合金,其中0.10≤y≤0.185,优选形成Zeta相的金锡合金。
在图2D中示出的电子器件100,尤其光电子器件100包括基板3,在基板3之上设置的、包括镍或由镍构成的第一层4a。在第一层之上设置有连接层序列5。连接层序列5包括第一金属间层5a,在第一金属间层5a之上设置的第二金属间层5b和在第二金属间层5b之上设置的第三金属间层5c。经由连接层序列5,半导体芯片1固定在基板3上。
图3和4示出动态的差式扫描量热图。在x轴上分别说明以℃为单位的温度并且在y轴上说明mW/mg。
图3示出铟锡合金InxSn1-x与镍的反应的动态的差式扫描量热图,其中0<x≤1。SPIn/Sn表示铟锡合金的熔点并且RNi表示液态铟锡合金与镍的反应。如可见那样,与镍的反应非常慢地进行并且在达到熔点温度之后不立即发生。出于所述原因,镍尤其适合于使用在阻挡层中,因为这样可以确保,金属化层序列充分地由液态铟锡合金润湿。
图4示出铟锡合金InxSn1-x与金的反应的动态的差式扫描量热图,其中0<x≤1。SPIn/Sn表示铟锡合金的熔点并且RAu表示液态铟锡合金与金的反应。如可见那样,金的反应直接地、在铟锡合金熔化并且存在的阻碍消除之后进行。由此,在使用过薄的阻挡层或不使用阻挡层时不会润湿或不充分地润湿金属化层序列,因为在润湿和与金属化层序列的金属反应之前,铟锡合金事先在形成高熔相的情况下,与第二金属层的金凝固。
图5示出金锡合金的相图。在x轴上绘制以原子百分比(原子%)或以重量百分比(重量%)为单位的锡的份额,并且在y轴上绘制温度(T)。如可见那样,Zeta(ζ)相的金锡合金(阴影区域)从10原子百分比至18.5原子百分比的锡份额起形成从而具有式Au1-ySny,其中0.10≤y≤0.185。
图6示出铟锡合金的相图。在x轴上绘制以原子百分比(原子%)或以重量百分比(重量%)为单位的锡的份额,并且在y轴上绘制温度(T)。锡份额在4和20原子百分比之间,因此具有式InxSn1-x,其中0.04≤x≤0.2的铟锡合金具有在大约190℃和225℃之间的熔点,这证实为对于执行根据本发明的方法是特别有利的。
在此所描述的发明不受根据实施例的描述限制。更确切地说,本发明包括任意新特征以及特征的任意组合,这尤其包含实施例中的特征的任意组合,即使所述特征或所述组合本身并未详尽地在实施例中说明时也如此。
本专利申请要求德国专利申请DE 10 2017 112 866.2的优先权,其公开内容通过参引结合于此。
附图标记列表
1 半导体芯片
2 焊料金属层序列
3 基板或导线框架
4 金属化层序列
5 连接层序列
2a 第一金属层
2b 阻挡层
2c 第二金属层
2d 第二阻挡层
2e 防氧化保护层
4a 第一层
4b 第二层
4c 第三层
5a 第一金属间层
5b 第二金属间层
5c 第三金属间层
100 电子器件
T 温度
℃ 摄氏度at% 原子百分比Gew%重量百分比
Claims (17)
1.一种用于将半导体芯片(1)固定在基板(3)上的方法,所述方法包括如下方法步骤:
A)提供半导体芯片(1),
B)将焊料金属层序列(2)施加到所述半导体芯片(1)上,
C)提供基板(3),
D)将金属化层序列(4)施加到所述基板(3)上,
E)将所述半导体芯片(1)经由所述焊料金属层序列(2)和所述金属化层序列(4)施加到所述基板(3)上,
F)加热通过E)产生的用于将所述半导体芯片(1)固定在所述基板(3)上的装置,
其中所述焊料金属层序列(2)包括:
-包含铟锡合金的第一金属层(2a),
-在所述第一金属层(2a)之上设置的阻挡层(2b)和
-在所述阻挡层(2b)和所述半导体芯片(1)之间设置的第二金属层(2c),所述第二金属层包括金,其中在所述第二金属层(2c)中的金的物质量比在所述第一金属层(2a)中的锡的物质量更大。
2.根据权利要求1所述的方法,
其中在所述第二金属层(2c)中的金的物质量是在所述第一金属层(2a)中的锡的物质量的至少双倍大。
3.根据权利要求1所述的方法,
其中所述金属化层序列(4)包括在所述基板(3)之上设置的第一层(4a),所述第一层包括镍。
4.根据权利要求1所述的方法,
其中所述阻挡层(2b)包含镍、钛、铂或钛化合物。
5.根据权利要求1所述的方法,
其中在方法步骤F)中形成在所述基板和所述半导体芯片(1)之间的连接层序列(5)并且所述连接层序列(5)包括:
-第一金属间层(5a),所述第一金属间层包括铟、锡和镍;
-第二金属间层(5b),所述第二金属间层包括铟、锡和镍;铟、锡和钛;铟、锡和钛化合物或者铟、锡和铂;和
-第三金属间层(5c),所述第三金属间层包括铟、锡和金。
6.根据权利要求1所述的方法,
所述金属化层序列(4)包括在所述基板(3)之上设置的第一层(4a),所述第一层包括镍;
-在所述第一层(4a)之上设置的第二层(4b),所述第二层包括钯;和
-在所述第二层(4b)之上设置的第三层(4c),所述第三层包括金。
7.根据权利要求6所述的方法,
其中在方法步骤E)中将所述半导体芯片(1)施加到所述基板(3)上,使得将所述焊料金属层序列(2)的所述第一金属层(2a)施加到所述金属化层序列(4)的所述第三层(4c)上。
8.根据权利要求1所述的方法,
其中所述阻挡层(2b)具有在5nm和200nm之间、包含边界值的层厚度。
9.根据权利要求1所述的方法,
其中所述铟锡合金具有式InxSn1-x,其中0.04≤x≤0.2。
10.根据权利要求1所述的方法,
其中所述铟锡合金具有式InxSn1-x,其中0.06≤x≤0.18。
11.根据权利要求1所述的方法,
其中所述铟锡合金具有式InxSn1-x,其中0.08≤x≤0.16。
12.根据权利要求1所述的方法,
其中所述第一金属层(2a)具有在750nm至3μm之间、包含边界值的层厚度。
13.根据权利要求1所述的方法,
其中所述第二金属层(2c)具有在500nm至2μm之间、包含边界值的层厚度。
14.根据权利要求1所述的方法,
其中所述焊料金属层序列(2)包括包含金的防氧化保护层(2e)和第二阻挡层(2d),并且所述第一金属层(2a)在所述第二阻挡层(2d)之上设置,并且所述第二阻挡层(2d)在所述防氧化保护层(2e)之上设置。
15.根据权利要求1所述的方法,
其中所述半导体芯片(1)包括包含硅的载体。
16.一种电子器件(100),所述电子器件包括基板(3)和在所述基板(3)之上设置的半导体芯片(1),其中在所述基板(3)和所述半导体芯片(1)之间设置有连接层序列(5),并且所述连接层序列(5)包括:
-第一金属间层(5a),所述第一金属间层包括铟、锡和镍;
-第二金属间层(5b),所述第二金属间层包括铟、锡和钛化合物,铟、锡和镍;铟、锡和铂或者铟、锡和钛;和
-第三金属间层(5c),所述第三金属间层包括铟、锡和金,其中在所述第三金属间层(5c)中金的物质量大于锡的物质量,并且
所述第一金属间层(5a)设置在所述基板(3)之上,所述第二金属间层(5b)设置在所述第一金属间层(5a)之上,并且所述第三金属间层(5c)设置在所述第二金属间层(5b)之上。
17.根据权利要求16所述的电子器件(100),
其中所述第三金属间层(5c)包括Zeta相的金锡合金。
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Publication number | Publication date |
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CN110770894A (zh) | 2020-02-07 |
US20220208715A1 (en) | 2022-06-30 |
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US11315898B2 (en) | 2022-04-26 |
US20200211997A1 (en) | 2020-07-02 |
KR20200003417A (ko) | 2020-01-09 |
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