JP2020507176A - 低速周辺機器のための中断処理方法及び装置 - Google Patents

低速周辺機器のための中断処理方法及び装置 Download PDF

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Publication number
JP2020507176A
JP2020507176A JP2019562234A JP2019562234A JP2020507176A JP 2020507176 A JP2020507176 A JP 2020507176A JP 2019562234 A JP2019562234 A JP 2019562234A JP 2019562234 A JP2019562234 A JP 2019562234A JP 2020507176 A JP2020507176 A JP 2020507176A
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interrupt
circuit
signal
output
clock
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Japanese (ja)
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JP2020507176A5 (enExample
Inventor
ソニ マネーシュ
ソニ マネーシュ
スヴァルナ ラジェーヴ
スヴァルナ ラジェーヴ
カレ ニクンジ
カレ ニクンジ
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日本テキサス・インスツルメンツ合同会社
テキサス インスツルメンツ インコーポレイテッド
テキサス インスツルメンツ インコーポレイテッド
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Publication of JP2020507176A publication Critical patent/JP2020507176A/ja
Publication of JP2020507176A5 publication Critical patent/JP2020507176A5/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
JP2019562234A 2017-01-31 2018-01-31 低速周辺機器のための中断処理方法及び装置 Pending JP2020507176A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/420,267 2017-01-31
US15/420,267 US10788853B2 (en) 2017-01-31 2017-01-31 Interrupt handling method and apparatus for slow peripherals
PCT/US2018/016206 WO2018144583A1 (en) 2017-01-31 2018-01-31 Interrupt handling method and apparatus for slow peripherals

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JP2020507176A true JP2020507176A (ja) 2020-03-05
JP2020507176A5 JP2020507176A5 (enExample) 2021-03-11

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US (3) US10788853B2 (enExample)
EP (1) EP3577557A4 (enExample)
JP (1) JP2020507176A (enExample)
CN (2) CN119024924A (enExample)
WO (1) WO2018144583A1 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3109227B1 (fr) 2020-04-14 2022-05-06 St Microelectronics Alps Sas Contrôleur d’interruption et procédé de gestion d’un tel contrôleur
CN113885654A (zh) * 2020-07-03 2022-01-04 富泰华工业（深圳）有限公司 跨时钟域信号传输方法、电路及电子装置
US11200184B1 (en) * 2020-12-22 2021-12-14 Industrial Technology Research Institute Interrupt control device and interrupt control method between clock domains

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001184298A (ja) * 1999-12-27 2001-07-06 Toshiba Corp 非同期割り込み通知回路及び方法
JP2002149419A (ja) * 2000-11-03 2002-05-24 Arm Ltd 割り込みをクリアするロジック・ユニット及び集積回路
JP2009282780A (ja) * 2008-05-22 2009-12-03 Atmel Germany Gmbh 受領信号の形成装置

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KR920003152A (ko) 1990-07-31 1992-02-29 이헌조 다중 인터럽트 처리회로
US5900753A (en) * 1997-03-28 1999-05-04 Logicvision, Inc. Asynchronous interface
US6507609B1 (en) 1999-01-20 2003-01-14 Advanced Micro Devices, Inc. Mechanism for capturing and reporting interrupt events of different clock domains
JP2002041452A (ja) 2000-07-27 2002-02-08 Hitachi Ltd マイクロプロセッサ、半導体モジュール及びデータ処理システム
US6823413B2 (en) 2001-06-08 2004-11-23 Oki Electronic Industry Co., Ltd. Interrupt signal processing apparatus
US8284879B2 (en) 2003-06-25 2012-10-09 Nxp B.V. Lossless transfer of events across clock domains
US20060064529A1 (en) 2004-09-23 2006-03-23 International Business Machines Corporation Method and system for controlling peripheral adapter interrupt frequency by transferring processor load information to the peripheral adapter
DE102007023442B3 (de) * 2007-05-19 2008-10-09 Atmel Germany Gmbh Vorrichtung und Verfahren zum Erzeugen eines Quittiersignals
US7934113B2 (en) 2007-05-21 2011-04-26 Texas Instruments Incorporated Self-clearing asynchronous interrupt edge detect latching register
JP4912511B2 (ja) 2010-03-16 2012-04-11 三菱電機株式会社 速度検出装置
CN103631649B (zh) * 2012-08-24 2018-08-28 深圳市中兴微电子技术有限公司 中断处理方法、装置及中断控制器
US10014041B1 (en) * 2016-12-23 2018-07-03 Texas Instruments Incorporated Integrated circuits, methods and interface circuitry to synchronize data transfer between high and low speed clock domains
CN113885654A (zh) * 2020-07-03 2022-01-04 富泰华工业（深圳）有限公司 跨时钟域信号传输方法、电路及电子装置
US11200184B1 (en) * 2020-12-22 2021-12-14 Industrial Technology Research Institute Interrupt control device and interrupt control method between clock domains

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001184298A (ja) * 1999-12-27 2001-07-06 Toshiba Corp 非同期割り込み通知回路及び方法
JP2002149419A (ja) * 2000-11-03 2002-05-24 Arm Ltd 割り込みをクリアするロジック・ユニット及び集積回路
JP2009282780A (ja) * 2008-05-22 2009-12-03 Atmel Germany Gmbh 受領信号の形成装置

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US20200379505A1 (en) 2020-12-03
US12105550B2 (en) 2024-10-01
CN110249309A (zh) 2019-09-17
WO2018144583A1 (en) 2018-08-09
EP3577557A1 (en) 2019-12-11
US10788853B2 (en) 2020-09-29
US20180217630A1 (en) 2018-08-02
US20240411341A1 (en) 2024-12-12
CN110249309B (zh) 2024-08-30
CN119024924A (zh) 2024-11-26
EP3577557A4 (en) 2020-06-03

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