KR920003152A - 다중 인터럽트 처리회로 - Google Patents

다중 인터럽트 처리회로 Download PDF

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Publication number
KR920003152A
KR920003152A KR1019900011655A KR900011655A KR920003152A KR 920003152 A KR920003152 A KR 920003152A KR 1019900011655 A KR1019900011655 A KR 1019900011655A KR 900011655 A KR900011655 A KR 900011655A KR 920003152 A KR920003152 A KR 920003152A
Authority
KR
South Korea
Prior art keywords
flop
flip
signal
processing circuit
output
Prior art date
Application number
KR1019900011655A
Other languages
English (en)
Inventor
최재부
Original Assignee
이헌조
주식회사 금성사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 이헌조, 주식회사 금성사 filed Critical 이헌조
Priority to KR1019900011655A priority Critical patent/KR920003152A/ko
Priority to EP19910112791 priority patent/EP0469543A3/en
Publication of KR920003152A publication Critical patent/KR920003152A/ko

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Bus Control (AREA)

Abstract

내용 없음

Description

다중 인터럽트 처리회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 마이콤의 시스템 블록도.
제2도는 마이콤의 시스템 회로도.
제3도는 인터블록 회로도.

Claims (1)

  1. TNTI신호와 마스크 신호를 오아게이트(OR1)을 거쳐 플립플롭 FF1과 노아게이트 NOR1에 인가하고 그 출력과 상기 플립플롭 FF1의 Q출력을 오아게이트 OR1을 거쳐 플립플롭 FF2의 D단자 앤드게이트 AND2에 인가하고 CKT신호를 앤드게이트 AND2에 인가하여 CKO신호를 출력하고 또한 CKT시호가 플립플롭 FF2에 인가되고 플립플롭 FF2의 Q출력이 플립플롭 FF1의 CLR과 TNTO출력단에 인가되도록 구성된 것을 특징으로 하는 다중 인터럽트 처리회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900011655A 1990-07-31 1990-07-31 다중 인터럽트 처리회로 KR920003152A (ko)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019900011655A KR920003152A (ko) 1990-07-31 1990-07-31 다중 인터럽트 처리회로
EP19910112791 EP0469543A3 (en) 1990-07-31 1991-07-30 Multiple interrupt handling circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900011655A KR920003152A (ko) 1990-07-31 1990-07-31 다중 인터럽트 처리회로

Publications (1)

Publication Number Publication Date
KR920003152A true KR920003152A (ko) 1992-02-29

Family

ID=19301811

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900011655A KR920003152A (ko) 1990-07-31 1990-07-31 다중 인터럽트 처리회로

Country Status (2)

Country Link
EP (1) EP0469543A3 (ko)
KR (1) KR920003152A (ko)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2137507A1 (en) * 1993-12-09 1995-06-10 Young W. Lee Interrupt controller for an integrated circuit
GB9509626D0 (en) * 1995-05-12 1995-07-05 Sgs Thomson Microelectronics Processor interrupt control
GB2357902B (en) * 1996-06-03 2001-08-15 Nec Corp Semiconductor device and method for manufacturing same
EP0884684B1 (en) 1997-06-13 2004-10-27 Alcatel Multiple interrupt handling method and apparatus
US9189283B2 (en) 2011-03-03 2015-11-17 Hewlett-Packard Development Company, L.P. Task launching on hardware resource for client
US9645823B2 (en) 2011-03-03 2017-05-09 Hewlett-Packard Development Company, L.P. Hardware controller to choose selected hardware entity and to execute instructions in relation to selected hardware entity
US8738830B2 (en) 2011-03-03 2014-05-27 Hewlett-Packard Development Company, L.P. Hardware interrupt processing circuit
US10788853B2 (en) * 2017-01-31 2020-09-29 Texas Instruments Incorporated Interrupt handling method and apparatus for slow peripherals

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3611305A (en) * 1969-02-10 1971-10-05 Scanders Associates Inc Data processor interrupt system
CA1319441C (en) * 1988-09-09 1993-06-22 Paul R. Culley Programmable interrupt controller

Also Published As

Publication number Publication date
EP0469543A2 (en) 1992-02-05
EP0469543A3 (en) 1992-07-15

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