JP2020205003A - メモリシステム、メモリコントローラ、及び半導体記憶装置 - Google Patents

メモリシステム、メモリコントローラ、及び半導体記憶装置 Download PDF

Info

Publication number
JP2020205003A
JP2020205003A JP2019113565A JP2019113565A JP2020205003A JP 2020205003 A JP2020205003 A JP 2020205003A JP 2019113565 A JP2019113565 A JP 2019113565A JP 2019113565 A JP2019113565 A JP 2019113565A JP 2020205003 A JP2020205003 A JP 2020205003A
Authority
JP
Japan
Prior art keywords
data
memory
input
product
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2019113565A
Other languages
English (en)
Japanese (ja)
Inventor
洋 前嶋
Hiroshi Maejima
洋 前嶋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kioxia Corp
Original Assignee
Kioxia Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kioxia Corp filed Critical Kioxia Corp
Priority to JP2019113565A priority Critical patent/JP2020205003A/ja
Priority to CN202010013639.9A priority patent/CN112115078B/zh
Priority to TW111118972A priority patent/TW202234407A/zh
Priority to TW109100465A priority patent/TWI768277B/zh
Priority to US16/804,037 priority patent/US11169742B2/en
Publication of JP2020205003A publication Critical patent/JP2020205003A/ja
Priority to US17/494,015 priority patent/US11789656B2/en
Priority to US18/242,521 priority patent/US20230409241A1/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/045—Combinations of networks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/54—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5642—Multilevel memory with buffers, latches, registers at input or output
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5644—Multilevel memory comprising counting devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biomedical Technology (AREA)
  • Molecular Biology (AREA)
  • Biophysics (AREA)
  • General Health & Medical Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Data Mining & Analysis (AREA)
  • Evolutionary Computation (AREA)
  • Computational Linguistics (AREA)
  • Artificial Intelligence (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Human Computer Interaction (AREA)
  • Neurology (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Memory System (AREA)
JP2019113565A 2019-06-19 2019-06-19 メモリシステム、メモリコントローラ、及び半導体記憶装置 Pending JP2020205003A (ja)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP2019113565A JP2020205003A (ja) 2019-06-19 2019-06-19 メモリシステム、メモリコントローラ、及び半導体記憶装置
CN202010013639.9A CN112115078B (zh) 2019-06-19 2020-01-07 存储系统、存储控制器及半导体存储装置
TW111118972A TW202234407A (zh) 2019-06-19 2020-01-07 非揮發性半導體記憶體
TW109100465A TWI768277B (zh) 2019-06-19 2020-01-07 記憶體系統、記憶體控制器及非揮發性半導體記憶體
US16/804,037 US11169742B2 (en) 2019-06-19 2020-02-28 Memory system, memory controller, and semiconductor memory device
US17/494,015 US11789656B2 (en) 2019-06-19 2021-10-05 Memory system, memory controller, and semiconductor memory device
US18/242,521 US20230409241A1 (en) 2019-06-19 2023-09-06 Nonvolatile semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2019113565A JP2020205003A (ja) 2019-06-19 2019-06-19 メモリシステム、メモリコントローラ、及び半導体記憶装置

Publications (1)

Publication Number Publication Date
JP2020205003A true JP2020205003A (ja) 2020-12-24

Family

ID=73798736

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2019113565A Pending JP2020205003A (ja) 2019-06-19 2019-06-19 メモリシステム、メモリコントローラ、及び半導体記憶装置

Country Status (4)

Country Link
US (3) US11169742B2 (zh)
JP (1) JP2020205003A (zh)
CN (1) CN112115078B (zh)
TW (2) TW202234407A (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2022144449A (ja) * 2021-03-19 2022-10-03 キオクシア株式会社 メモリシステム、メモリシステムの制御方法及びホストデバイス
CN115188404A (zh) * 2021-04-07 2022-10-14 华为技术有限公司 存储装置和处理数据的方法
JP2022170342A (ja) 2021-04-28 2022-11-10 キオクシア株式会社 半導体記憶装置
JP7104843B1 (ja) * 2021-08-31 2022-07-21 ウィンボンド エレクトロニクス コーポレーション 半導体記憶装置
JP2023141561A (ja) * 2022-03-24 2023-10-05 キオクシア株式会社 半導体記憶装置
US20230317124A1 (en) * 2022-04-05 2023-10-05 Taiwan Semiconductor Manufacturing Company, Ltd. Memory system and operating method of memory system

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6781895B1 (en) * 1991-12-19 2004-08-24 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device and memory system using the same
JP5142692B2 (ja) 2007-12-11 2013-02-13 株式会社東芝 不揮発性半導体記憶装置
JP4635066B2 (ja) 2008-03-19 2011-02-16 株式会社東芝 半導体記憶装置
JP2009238874A (ja) 2008-03-26 2009-10-15 Toshiba Corp 半導体メモリ及びその製造方法
JP5283960B2 (ja) 2008-04-23 2013-09-04 株式会社東芝 三次元積層不揮発性半導体メモリ
JP2009266944A (ja) 2008-04-23 2009-11-12 Toshiba Corp 三次元積層不揮発性半導体メモリ
US9430735B1 (en) * 2012-02-23 2016-08-30 Micron Technology, Inc. Neural network in a memory device
US20150269480A1 (en) * 2014-03-21 2015-09-24 Qualcomm Incorporated Implementing a neural-network processor
US9600183B2 (en) 2014-09-22 2017-03-21 Intel Corporation Apparatus, system and method for determining comparison information based on memory data
IL281321B (en) * 2016-10-04 2022-07-01 Magic Leap Inc Efficient data layouts for convolutional neural networks
US10896367B2 (en) * 2017-03-07 2021-01-19 Google Llc Depth concatenation using a matrix computation unit
JP7173709B2 (ja) * 2017-04-14 2022-11-16 株式会社半導体エネルギー研究所 ニューラルネットワーク回路
US11475274B2 (en) * 2017-04-21 2022-10-18 International Business Machines Corporation Parameter criticality-aware resilience
US11783160B2 (en) * 2018-01-30 2023-10-10 Intel Corporation Memoryless weight storage hardware for neural networks

Also Published As

Publication number Publication date
US11169742B2 (en) 2021-11-09
US20200401347A1 (en) 2020-12-24
TW202234407A (zh) 2022-09-01
TW202101203A (zh) 2021-01-01
US20220027094A1 (en) 2022-01-27
US11789656B2 (en) 2023-10-17
TWI768277B (zh) 2022-06-21
US20230409241A1 (en) 2023-12-21
CN112115078B (zh) 2024-04-05
CN112115078A (zh) 2020-12-22

Similar Documents

Publication Publication Date Title
TWI768277B (zh) 記憶體系統、記憶體控制器及非揮發性半導體記憶體
US10629259B2 (en) Non-volatile memory device and on-chip valley search (OCVS) read method thereof
KR102599123B1 (ko) 인공 신경망 모델에 기초하여 읽기 레벨들을 추론하는 스토리지 장치 및 인공 신경망 모델의 학습 방법
US10910080B2 (en) Nonvolatile memory device configured to adjust a read parameter based on degradation level
US10916314B2 (en) Non-volatile memory device and a read method thereof
US9548127B1 (en) Memory system
JP2019169207A (ja) 半導体記憶装置
JP2019057350A (ja) 半導体メモリ
US11232835B2 (en) Methods and apparatus for reading NAND flash memory
CN115938445A (zh) 半导体存储器设备和操作该半导体存储器设备的方法
JP2022050898A (ja) メモリシステムおよびメモリシステムの制御方法
JP2000251485A (ja) 不揮発性半導体記憶装置およびそのデータ書き込み方法
JP4364207B2 (ja) 不揮発性半導体記憶装置
JP3905936B2 (ja) 不揮発性半導体記憶装置
JP4302118B2 (ja) 不揮発性半導体記憶装置
JP4302117B2 (ja) 不揮発性半導体記憶装置
US20240177786A1 (en) Page buffer, memory device including page buffer and memory system including memory device
US20240161832A1 (en) Semiconductor device related to performance of a program operation and method of operating the semiconductor device
US20230057711A1 (en) System and method for dynamic inter-cell interference compensation in non-volatile memory storage devices
JP2024046271A (ja) 半導体記憶装置
KR20220104514A (ko) 페이지 버퍼, 이를 포함하는 반도체 메모리 장치 및 이의 동작 방법
CN117476078A (zh) 用于有效地检查编程状态的存储器装置及其操作方法
JP2006228426A (ja) 不揮発性半導体記憶装置