JP2020077753A5 - - Google Patents

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Publication number
JP2020077753A5
JP2020077753A5 JP2018210072A JP2018210072A JP2020077753A5 JP 2020077753 A5 JP2020077753 A5 JP 2020077753A5 JP 2018210072 A JP2018210072 A JP 2018210072A JP 2018210072 A JP2018210072 A JP 2018210072A JP 2020077753 A5 JP2020077753 A5 JP 2020077753A5
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JP
Japan
Prior art keywords
taper angle
pattern
control unit
controls
line
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JP2018210072A
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English (en)
Japanese (ja)
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JP2020077753A (ja
JP7195113B2 (ja
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Priority claimed from JP2018210072A external-priority patent/JP7195113B2/ja
Priority to JP2018210072A priority Critical patent/JP7195113B2/ja
Priority to TW108139225A priority patent/TWI826563B/zh
Priority to US16/671,407 priority patent/US11380545B2/en
Priority to KR1020190140601A priority patent/KR102944094B1/ko
Priority to CN201911082523.4A priority patent/CN111162006B/zh
Publication of JP2020077753A publication Critical patent/JP2020077753A/ja
Publication of JP2020077753A5 publication Critical patent/JP2020077753A5/ja
Publication of JP7195113B2 publication Critical patent/JP7195113B2/ja
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JP2018210072A 2018-11-07 2018-11-07 処理方法及び基板処理装置 Active JP7195113B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2018210072A JP7195113B2 (ja) 2018-11-07 2018-11-07 処理方法及び基板処理装置
TW108139225A TWI826563B (zh) 2018-11-07 2019-10-30 處理方法及基板處理裝置
US16/671,407 US11380545B2 (en) 2018-11-07 2019-11-01 Processing method and substrate processing apparatus
KR1020190140601A KR102944094B1 (ko) 2018-11-07 2019-11-06 처리 방법 및 기판 처리 장치
CN201911082523.4A CN111162006B (zh) 2018-11-07 2019-11-07 处理方法和基板处理装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2018210072A JP7195113B2 (ja) 2018-11-07 2018-11-07 処理方法及び基板処理装置

Publications (3)

Publication Number Publication Date
JP2020077753A JP2020077753A (ja) 2020-05-21
JP2020077753A5 true JP2020077753A5 (https=) 2021-09-24
JP7195113B2 JP7195113B2 (ja) 2022-12-23

Family

ID=70458783

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018210072A Active JP7195113B2 (ja) 2018-11-07 2018-11-07 処理方法及び基板処理装置

Country Status (5)

Country Link
US (1) US11380545B2 (https=)
JP (1) JP7195113B2 (https=)
KR (1) KR102944094B1 (https=)
CN (1) CN111162006B (https=)
TW (1) TWI826563B (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10727045B2 (en) * 2017-09-29 2020-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method for manufacturing a semiconductor device
JP7627645B2 (ja) * 2021-11-01 2025-02-06 東京エレクトロン株式会社 プラズマ処理方法及びプラズマ処理装置
JPWO2024203220A1 (https=) * 2023-03-24 2024-10-03

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6624016B2 (en) * 2001-02-22 2003-09-23 Silicon-Based Technology Corporation Method of fabricating trench isolation structures with extended buffer spacers
JP4176365B2 (ja) * 2002-03-25 2008-11-05 東京エレクトロン株式会社 プラズマエッチング方法
JP4727171B2 (ja) * 2003-09-29 2011-07-20 東京エレクトロン株式会社 エッチング方法
KR100553839B1 (ko) * 2003-11-27 2006-02-24 삼성전자주식회사 캐패시터와 그 제조 방법, 이를 포함하는 반도체 장치 및그 제조 방법
KR100573827B1 (ko) * 2003-12-30 2006-04-26 주식회사 하이닉스반도체 반도체 소자의 콘택 형성 방법
JP2006203035A (ja) * 2005-01-21 2006-08-03 Tokyo Electron Ltd プラズマエッチング方法
US7271108B2 (en) * 2005-06-28 2007-09-18 Lam Research Corporation Multiple mask process with etch mask stack
US20070181530A1 (en) * 2006-02-08 2007-08-09 Lam Research Corporation Reducing line edge roughness
JP2007294905A (ja) * 2006-03-30 2007-11-08 Hitachi High-Technologies Corp 半導体製造方法およびエッチングシステム
US7491343B2 (en) 2006-09-14 2009-02-17 Lam Research Corporation Line end shortening reduction during etch
US7894927B2 (en) * 2008-08-06 2011-02-22 Tokyo Electron Limited Using Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models for metal-gate structures
US7772122B2 (en) * 2008-09-18 2010-08-10 Lam Research Corporation Sidewall forming processes
US8592327B2 (en) * 2012-03-07 2013-11-26 Tokyo Electron Limited Formation of SiOCl-containing layer on exposed low-k surfaces to reduce low-k damage
US20130267097A1 (en) * 2012-04-05 2013-10-10 Lam Research Corporation Method and apparatus for forming features with plasma pre-etch treatment on photoresist
JP2014225501A (ja) * 2013-05-15 2014-12-04 東京エレクトロン株式会社 プラズマエッチング方法及びプラズマエッチング装置
JP6185305B2 (ja) * 2013-06-28 2017-08-23 東京エレクトロン株式会社 プラズマエッチング方法およびプラズマエッチング装置
KR20150015978A (ko) * 2013-08-02 2015-02-11 삼성디스플레이 주식회사 표시 장치의 방법
CN104916577B (zh) * 2014-03-14 2018-08-24 北京北方华创微电子装备有限公司 斜孔刻蚀方法
US9922839B2 (en) 2015-06-23 2018-03-20 Lam Research Corporation Low roughness EUV lithography
JP2017084938A (ja) * 2015-10-27 2017-05-18 東京エレクトロン株式会社 被処理体を処理する方法

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