JP2019525480A - 隣接する非対称アクティブゲート／ダミーゲート幅レイアウトを採用する電界効果トランジスタ（ｆｅｔ）デバイス - Google Patents

隣接する非対称アクティブゲート／ダミーゲート幅レイアウトを採用する電界効果トランジスタ（ｆｅｔ）デバイス Download PDF

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JP2019525480A
JP2019525480A JP2019506475A JP2019506475A JP2019525480A JP 2019525480 A JP2019525480 A JP 2019525480A JP 2019506475 A JP2019506475 A JP 2019506475A JP 2019506475 A JP2019506475 A JP 2019506475A JP 2019525480 A JP2019525480 A JP 2019525480A
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gate
dummy gate
drain
gate width
active
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JP2019525480A5 (enExample
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ヨン・ソン・チェ
ウクジン・ロー
シャシャンク・エクボテ
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クアルコム，インコーポレイテッド
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/608—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having non-planar bodies, e.g. having recessed gate electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0273—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming final gates or dummy gates after forming source and drain electrodes, e.g. contact first technology
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H10D30/6211—Fin field-effect transistors [FinFET] having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/205—Nanosized electrodes, e.g. nanowire electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/258—Source or drain electrodes for field-effect devices characterised by the relative positions of the source or drain electrodes with respect to the gate electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/518—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their lengths or sectional shapes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Nanotechnology (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2019506475A 2016-08-24 2017-08-21 隣接する非対称アクティブゲート／ダミーゲート幅レイアウトを採用する電界効果トランジスタ（ｆｅｔ）デバイス Pending JP2019525480A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/245,777 2016-08-24
US15/245,777 US9634138B1 (en) 2016-08-24 2016-08-24 Field-effect transistor (FET) devices employing adjacent asymmetric active gate / dummy gate width layout
PCT/US2017/047747 WO2018039108A1 (en) 2016-08-24 2017-08-21 Field-effect transistor (fet) devices employing adjacent asymmetric active gate / dummy gate width layout

Publications (2)

Publication Number Publication Date
JP2019525480A true JP2019525480A (ja) 2019-09-05
JP2019525480A5 JP2019525480A5 (enExample) 2020-09-17

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JP2019506475A Pending JP2019525480A (ja) 2016-08-24 2017-08-21 隣接する非対称アクティブゲート／ダミーゲート幅レイアウトを採用する電界効果トランジスタ（ｆｅｔ）デバイス

Country Status (7)

Country Link
US (2) US9634138B1 (enExample)
EP (1) EP3504732B1 (enExample)
JP (1) JP2019525480A (enExample)
KR (1) KR20190040488A (enExample)
CN (1) CN109643658B (enExample)
BR (1) BR112019002959A2 (enExample)
WO (1) WO2018039108A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019534550A (ja) * 2016-09-21 2019-11-28 クアルコム，インコーポレイテッド ＦｉｎＦＥＴにおけるレイアウトの影響の緩和

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9634138B1 (en) 2016-08-24 2017-04-25 Qualcomm Incorporated Field-effect transistor (FET) devices employing adjacent asymmetric active gate / dummy gate width layout
CN108281479A (zh) * 2017-01-06 2018-07-13 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US10134859B1 (en) 2017-11-09 2018-11-20 International Business Machines Corporation Transistor with asymmetric spacers
US10916478B2 (en) * 2018-02-20 2021-02-09 Globalfoundries U.S. Inc. Methods of performing fin cut etch processes for FinFET semiconductor devices
KR102535087B1 (ko) * 2018-04-20 2023-05-19 삼성전자주식회사 반도체 장치
US10475693B1 (en) * 2018-06-07 2019-11-12 Globalfoundries Inc. Method for forming single diffusion breaks between finFET devices and the resulting devices
US10236364B1 (en) 2018-06-22 2019-03-19 International Busines Machines Corporation Tunnel transistor
US10249755B1 (en) 2018-06-22 2019-04-02 International Business Machines Corporation Transistor with asymmetric source/drain overlap
KR102577262B1 (ko) 2018-08-14 2023-09-11 삼성전자주식회사 확산 방지 영역을 갖는 반도체 소자
US10483200B1 (en) * 2018-09-27 2019-11-19 Qualcomm Incorporated Integrated circuits (ICs) employing additional output vertical interconnect access(es) (VIA(s)) coupled to a circuit output VIA to decrease circuit output resistance
TWI788487B (zh) * 2018-12-21 2023-01-01 聯華電子股份有限公司 半導體元件
US11710768B2 (en) 2021-05-26 2023-07-25 International Business Machines Corporation Hybrid diffusion break with EUV gate patterning
US12230684B2 (en) * 2021-07-26 2025-02-18 Samsung Electronics Co., Ltd. Integrated circuit with continuous active region and raised source/drain region

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130015524A1 (en) * 2011-07-12 2013-01-17 Chun-Wei Hsu Semiconductor device having metal gate and manufacturing method thereof
JP2016042568A (ja) * 2014-08-18 2016-03-31 ルネサスエレクトロニクス株式会社 半導体装置
US20160111320A1 (en) * 2014-10-16 2016-04-21 Globalfoundries Inc. T-shaped fin isolation region and methods of fabrication
US20160155739A1 (en) * 2014-12-01 2016-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Finfets and methods of forming finfets

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100425462B1 (ko) * 2001-09-10 2004-03-30 삼성전자주식회사 Ｓｏｉ 상의 반도체 장치 및 그의 제조방법
KR100714285B1 (ko) * 2004-12-28 2007-05-02 주식회사 하이닉스반도체 반도체 장치 및 그 제조방법
US7732845B2 (en) * 2008-04-08 2010-06-08 International Business Machines Corporation Pixel sensor with reduced image lag
US7777282B2 (en) * 2008-08-13 2010-08-17 Intel Corporation Self-aligned tunneling pocket in field-effect transistors and processes to form same
US8143131B2 (en) * 2009-03-31 2012-03-27 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating spacers in a strained semiconductor device
US8969958B1 (en) * 2009-11-13 2015-03-03 Maxim Integrated Products, Inc. Integrated MOS power transistor with body extension region for poly field plate depletion assist
US8247869B2 (en) * 2010-04-26 2012-08-21 Freescale Semiconductor, Inc. LDMOS transistors with a split gate
CN101834141B (zh) * 2010-04-28 2015-03-04 复旦大学 一种不对称型源漏场效应晶体管的制备方法
US9324866B2 (en) 2012-01-23 2016-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for transistor with line end extension
US9673328B2 (en) 2010-05-28 2017-06-06 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for providing line end extensions for fin-type active regions
US8193094B2 (en) 2010-06-21 2012-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Post CMP planarization by cluster ION beam etch
US8383485B2 (en) 2011-07-13 2013-02-26 Taiwan Semiconductor Manufacturing Co., Ltd. Epitaxial process for forming semiconductor devices
US9337318B2 (en) * 2012-10-26 2016-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with dummy gate on non-recessed shallow trench isolation (STI)
US9209182B2 (en) 2012-12-28 2015-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy metal gate structures to reduce dishing during chemical-mechanical polishing
US20140252491A1 (en) * 2013-03-05 2014-09-11 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method of the same
KR102021768B1 (ko) 2013-03-15 2019-09-17 삼성전자 주식회사 반도체 장치의 제조 방법 및 그 방법에 의해 제조된 반도체 장치
US8846491B1 (en) 2013-06-19 2014-09-30 Globalfoundries Inc. Forming a diffusion break during a RMG process
US9293586B2 (en) 2013-07-17 2016-03-22 Globalfoundries Inc. Epitaxial block layer for a fin field effect transistor device
US9515172B2 (en) 2014-01-28 2016-12-06 Samsung Electronics Co., Ltd. Semiconductor devices having isolation insulating layers and methods of manufacturing the same
US9871037B2 (en) 2014-02-26 2018-01-16 Taiwan Semiconductor Manufacturing Company Limited Structures and methods for fabricating semiconductor devices using fin structures
US9171752B1 (en) 2014-08-12 2015-10-27 Globalfoundries Inc. Product comprised of FinFET devices with single diffusion break isolation structures, and methods of making such a product
KR102312262B1 (ko) * 2014-09-02 2021-10-15 삼성전자주식회사 반도체 장치 및 이의 제조 방법
KR102264656B1 (ko) 2014-10-17 2021-06-14 삼성전자주식회사 게이트 코어들 및 핀 액티브 코어를 포함하는 반도체 소자 및 그 제조 방법
US9502243B2 (en) * 2014-12-22 2016-11-22 International Business Machines Corporation Multi-orientation SOI substrates for co-integration of different conductivity type semiconductor devices
US9368496B1 (en) 2015-01-30 2016-06-14 Globalfoundries Inc. Method for uniform recess depth and fill in single diffusion break for fin-type process and resulting devices
US9634138B1 (en) 2016-08-24 2017-04-25 Qualcomm Incorporated Field-effect transistor (FET) devices employing adjacent asymmetric active gate / dummy gate width layout

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130015524A1 (en) * 2011-07-12 2013-01-17 Chun-Wei Hsu Semiconductor device having metal gate and manufacturing method thereof
JP2016042568A (ja) * 2014-08-18 2016-03-31 ルネサスエレクトロニクス株式会社 半導体装置
US20160111320A1 (en) * 2014-10-16 2016-04-21 Globalfoundries Inc. T-shaped fin isolation region and methods of fabrication
US20160155739A1 (en) * 2014-12-01 2016-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Finfets and methods of forming finfets

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019534550A (ja) * 2016-09-21 2019-11-28 クアルコム，インコーポレイテッド ＦｉｎＦＥＴにおけるレイアウトの影響の緩和

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Publication number Publication date
CN109643658A (zh) 2019-04-16
BR112019002959A2 (pt) 2019-05-21
WO2018039108A1 (en) 2018-03-01
EP3504732A1 (en) 2019-07-03
CN109643658B (zh) 2022-03-22
US20180061943A1 (en) 2018-03-01
KR20190040488A (ko) 2019-04-18
US10062768B2 (en) 2018-08-28
US9634138B1 (en) 2017-04-25
EP3504732B1 (en) 2024-02-28

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