JP2019099438A - SiCエピタキシャルウェハの評価方法及び製造方法 - Google Patents
SiCエピタキシャルウェハの評価方法及び製造方法 Download PDFInfo
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- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 2
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- 244000000626 Daucus carota Species 0.000 description 1
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- 229910052782 aluminium Inorganic materials 0.000 description 1
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- 229910052698 phosphorus Inorganic materials 0.000 description 1
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- 229910052720 vanadium Inorganic materials 0.000 description 1
- LEONUFNNVUYDNQ-UHFFFAOYSA-N vanadium atom Chemical compound [V] LEONUFNNVUYDNQ-UHFFFAOYSA-N 0.000 description 1
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Abstract
Description
本発明は、上記課題を解決するため、以下の手段を提供する。
本実施形態にかかるSiCエピタキシャルウェハの製造方法は、不純物濃度が1×1018cm−3以上の高濃度エピタキシャル層をSiC基板上に積層する工程と、所定のSiCエピタキシャルウェハの評価方法を用いて高濃度エピタキシャル層を評価する工程と、高濃度エピタキシャル層上にドリフト層を積層する工程と、を有する。
まずSiC基板を準備する。SiC基板の作製方法は特に問わない。例えば、昇華法等で得られたSiCインゴットをスライスすることで得られる。本明細書において、SiCエピタキシャルウェハはエピタキシャル膜を形成後のウェハを意味し、SiC基板はエピタキシャル膜を形成前のウェハを意味する。
次いで、高濃度エピタキシャル層の評価工程(第1工程)として、高濃度エピタキシャル層内にBPDが存在するかを評価する。第1工程では、不純物濃度が1×1018cm−3以上の高濃度エピタキシャル層に対して励起光を照射し、430nm以下の波長帯のバンドパスフィルターを介して励起光の照射面を観測する。
また、この評価方法により測定したBPDは画像解析ソフトを使用しての自動検出が可能であり、定量的に計数できる。
最後に、高濃度エピタキシャル層上にドリフト層を積層する。ドリフト層は、公知の方法で積層される。ドリフト層の不純物濃度は、高濃度エピタキシャル層より低く、1×1016cm−3程度である。ドリフト層は、SiCデバイスが形成される層である。ドリフト層にBPDが含まれると、SiCデバイスの順方向特性の劣化要因となる。これについては、基板とエピタキシャル層の界面においてTEDへの転換することで、ドリフト層に含まれるBPDを低減することができる。また、ドリフト層は、高濃度エピタキシャル層上に積層されるため、基板中のBPDによる特性劣化もまた抑制されている。
Claims (6)
- 不純物濃度が1×1018cm−3以上の高濃度エピタキシャル層に対して励起光を照射し、430nm以下の波長帯のバンドパスフィルターを介して前記励起光の照射面を観測する第1工程を有する、SiCエピタキシャルウェハの評価方法。
- 前記第1工程において、オフセット方向に延在しアスペクト比が1より大きい欠陥を観測する、請求項1に記載のSiCエピタキシャルウェハの評価方法。
- 前記励起光の照射面を430nmより大きい波長帯のバンドパスフィルターを介して観測する第2工程と、
前記第1工程の観測結果と前記第2工程の評価結果を比較する第1判定工程をさらに有する、請求項1又は2に記載のSiCエピタキシャルウェハの評価方法。 - 前記励起光の照射面と同一面を表面観察する第3工程と、
前記第1工程の観測結果と前記第3工程の評価結果を比較する第2判定工程をさらに有する、請求項1〜3のいずれか一項に記載のSiCエピタキシャルウェハの評価方法。 - 不純物濃度が1×1018cm−3以上の高濃度エピタキシャル層をSiC基板の一面に積層する工程と、
請求項1〜4のいずれか一項に記載のSiCエピタキシャルウェハの評価方法を用いて、前記高濃度エピタキシャル層を評価する工程と、
前記高濃度エピタキシャル層上にドリフト層を積層する工程と、を有する、SiCエピタキシャルウェハの製造方法。 - 前記SiC基板と前記高濃度エピタキシャル層との間に、前記高濃度エピタキシャル層より不純物濃度が低いバッファ層を積層する工程をさらに有する、請求項5に記載のSiCエピタキシャルウェハの製造方法。
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JP2017234586A JP6986944B2 (ja) | 2017-12-06 | 2017-12-06 | SiCエピタキシャルウェハの評価方法及び製造方法 |
DE102018130046.8A DE102018130046A1 (de) | 2017-12-06 | 2018-11-28 | BEWERTUNGSVERFAHREN UND HERSTELLUNGSVERFAHREN VON SiC-EPITAXIALWAFERN |
CN201811449365.7A CN109887853B (zh) | 2017-12-06 | 2018-11-30 | SiC外延晶片的评价方法及制造方法 |
US16/207,396 US11315839B2 (en) | 2017-12-06 | 2018-12-03 | Evaluation method and manufacturing method of SiC epitaxial wafer |
US17/707,743 US20220223482A1 (en) | 2017-12-06 | 2022-03-29 | EVALUATION METHOD AND MANUFACTURING METHOD OF SiC EPITAXIAL WAFER |
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Cited By (2)
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JP7187620B1 (ja) | 2021-07-13 | 2022-12-12 | 昭和電工株式会社 | SiCエピタキシャルウェハ及びSiCエピタキシャルウェハの製造方法 |
JP7216248B1 (ja) | 2021-07-13 | 2023-01-31 | 昭和電工株式会社 | SiCデバイス及びSiCデバイスの製造方法 |
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JP6986944B2 (ja) * | 2017-12-06 | 2021-12-22 | 昭和電工株式会社 | SiCエピタキシャルウェハの評価方法及び製造方法 |
JP6585799B1 (ja) * | 2018-10-15 | 2019-10-02 | 昭和電工株式会社 | SiC基板の評価方法及びSiCエピタキシャルウェハの製造方法 |
JP7318424B2 (ja) * | 2019-09-02 | 2023-08-01 | 株式会社レゾナック | SiC基板の評価方法、SiCエピタキシャルウェハの製造方法及びSiCデバイスの製造方法 |
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JP7187620B1 (ja) | 2021-07-13 | 2022-12-12 | 昭和電工株式会社 | SiCエピタキシャルウェハ及びSiCエピタキシャルウェハの製造方法 |
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