JP2019075498A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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JP2019075498A
JP2019075498A JP2017201883A JP2017201883A JP2019075498A JP 2019075498 A JP2019075498 A JP 2019075498A JP 2017201883 A JP2017201883 A JP 2017201883A JP 2017201883 A JP2017201883 A JP 2017201883A JP 2019075498 A JP2019075498 A JP 2019075498A
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multilayer substrate
resin
groove
semiconductor device
thin film
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JP6981168B2 (en
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仁寛 丸亀
Yoshihiro Marugame
仁寛 丸亀
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to KR1020180035574A priority patent/KR102037655B1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67126—Apparatus for sealing, encapsulating, glassing, decapsulating or the like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

To obtain a method of manufacturing a semiconductor device capable of preventing a resin from overflowing while reducing cost.SOLUTION: A thin film 2 is formed on a mounting surface of a multilayer substrate 1. A semiconductor chip 3 is mounted on the mounting surface of the multilayer substrate 1. The multilayer substrate 1 is sandwiched between a lower mold 4 and an upper mold 5, and the semiconductor chip 3 is encapsulated with a resin 7. The thin film 2 has a groove 9 extending from an encapsulation region encapsulated with the resin 7 to the outside of the multilayer substrate 1. At the encapsulation with the resin 7, an upper surface of the thin film 2 and the upper mold 5 are contacted with each other at an outer peripheral part of the multilayer substrate 1, and the groove 9 is used as an air vent. The groove 9 has turning parts 15a and 15b.SELECTED DRAWING: Figure 2

Description

本発明は、半導体装置の製造方法に関する。   The present invention relates to a method of manufacturing a semiconductor device.

多層基板の実装面を樹脂で封止する際に、金型に形成されたエアベントからキャビティ内の空気が外部に排出される。エアベントの形状が最適でない場合、空気が樹脂内に留まってボイド又は未充填が発生し、逆に樹脂がエアベントから溢れ出すオーバーフローが発生するなどの問題がある。このため、多層基板に実装する半導体チップに合わせて金型にエアベントを設ける必要がある。従って、半導体チップが増減した場合に新規の金型が必要になり、コストがかかるという問題があった。これに対して、多層基板の実装面のソルダレジスト等に溝を形成し、エアベントとして用いる半導体装置の製造方法が提案されている（例えば、特許文献１（第１図）参照）。   When the mounting surface of the multilayer substrate is sealed with resin, air in the cavity is discharged to the outside from an air vent formed in the mold. If the shape of the air vent is not optimum, there is a problem that air remains in the resin and voids or unfilling occurs, and conversely, the resin overflows from the air vent, and the like. For this reason, it is necessary to provide an air vent in the mold according to the semiconductor chip mounted on the multilayer substrate. Therefore, when the number of semiconductor chips increases and decreases, a new mold is required, which causes a problem of cost increase. On the other hand, a method of manufacturing a semiconductor device has been proposed in which a groove is formed in a solder resist or the like on the mounting surface of a multilayer substrate and used as an air vent (see, for example, Patent Document 1 (FIG. 1)).

特開２００３−７７９４６号公報JP 2003-77946 A

従来は多層基板の実装面に直線状の溝を形成していたため、樹脂が溝から溢れ出すオーバーフローが発生し易いという問題があった。   Conventionally, since linear grooves were formed on the mounting surface of the multilayer substrate, there was a problem that the resin overflowed easily from the grooves.

本発明は、上述のような課題を解決するためになされたもので、その目的はコストを削減しつつ、樹脂のオーバーフローを防ぐことができる半導体装置の製造方法を得るものである。   The present invention has been made to solve the problems as described above, and an object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing resin overflow while reducing the cost.

本発明に係る半導体装置の製造方法は、多層基板の実装面に薄膜を形成する工程と、前記多層基板の前記実装面に半導体チップを実装する工程と、前記多層基板を下金型と上金型で挟んで前記半導体チップを樹脂で封止する工程とを備え、前記薄膜は、前記樹脂で封止される封止領域から前記多層基板の外側まで延びる溝を有し、前記樹脂で封止する際に、前記多層基板の外周部において前記薄膜の上面と前記上金型が接し、前記溝をエアベントとして用い、前記溝は切り返しを有することを特徴とする。   A method of manufacturing a semiconductor device according to the present invention comprises the steps of: forming a thin film on a mounting surface of a multilayer substrate; mounting a semiconductor chip on the mounting surface of the multilayer substrate; And sealing the semiconductor chip with a resin, wherein the thin film has a groove extending from the sealing region sealed with the resin to the outside of the multilayer substrate, and is sealed with the resin In this case, the upper surface of the thin film is in contact with the upper mold at the outer peripheral portion of the multilayer substrate, the groove is used as an air vent, and the groove has a turn.

本発明では、多層基板に設けた薄膜の溝をエアベントとして用いる。このように多層基板にエアベントの機能を持たせることで、半導体チップが増減しても新規の金型は不要であるため、コストを削減することができる。また、多層基板の実装面に形成する溝が切り返しを有する。これにより、樹脂のオーバーフローを防ぐことができる。   In the present invention, a thin film groove provided in a multilayer substrate is used as an air vent. By providing the multilayer substrate with the air vent function as described above, the cost can be reduced because a new mold is not necessary even if the number of semiconductor chips increases or decreases. Further, the groove formed on the mounting surface of the multilayer substrate has a turn. This can prevent resin overflow.

実施の形態１に係る半導体装置の製造方法を示す断面図である。FIG. 7 is a cross-sectional view showing the method of manufacturing the semiconductor device of the first embodiment. 実施の形態１に係る半導体装置の製造方法を示す平面図である。FIG. 7 is a plan view showing the method of manufacturing a semiconductor device in accordance with the first embodiment. 図２のＩ−ＩＩに沿った断面図である。It is sectional drawing along I-II of FIG. 比較例に係る半導体装置の製造方法を示す断面図である。FIG. 16 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the comparative example. 実施の形態２に係る半導体装置の製造方法を示す平面図である。FIG. 16 is a plan view showing a method of manufacturing a semiconductor device in accordance with a second embodiment. 実施の形態３に係る半導体装置の製造方法を示す平面図である。FIG. 16 is a plan view showing a method of manufacturing a semiconductor device in accordance with a third embodiment. 図６のＩ−ＩＩに沿った断面図である。It is sectional drawing along I-II of FIG.

本発明の実施の形態に係る半導体装置の製造方法について図面を参照して説明する。同じ又は対応する構成要素には同じ符号を付し、説明の繰り返しを省略する場合がある。   A method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. The same or corresponding components may be assigned the same reference numerals and repetition of the description may be omitted.

実施の形態１．
図１は、実施の形態１に係る半導体装置の製造方法を示す断面図である。まず、多層基板１の実装面に薄膜２を形成する。多層基板１の実装面に半導体チップ３を実装する。 Embodiment 1
FIG. 1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to the first embodiment. First, the thin film 2 is formed on the mounting surface of the multilayer substrate 1. The semiconductor chip 3 is mounted on the mounting surface of the multilayer substrate 1.

続いて、多層基板１の実装面にトランスファーモールド装置で樹脂封止を実施する。まず、多層基板１を下金型４と上金型５で挟んで型締めする。次に、上金型５と多層基板１の実装面の間に形成されるキャビティ６内に溶けた樹脂７を流し込み、半導体チップ３を樹脂７で封止する。   Subsequently, resin sealing is performed on the mounting surface of the multilayer substrate 1 by a transfer molding apparatus. First, the multilayer substrate 1 is clamped between the lower mold 4 and the upper mold 5 and clamped. Next, the melted resin 7 is poured into the cavity 6 formed between the upper mold 5 and the mounting surface of the multilayer substrate 1, and the semiconductor chip 3 is sealed with the resin 7.

薄膜２は、樹脂７で封止される封止領域から多層基板１の外側まで延びる溝９を有する。樹脂７で封止する際に、多層基板１の外周部において溝９以外の部分で薄膜２の上面と上金型５が接する。溝９をエアベントとして用いてキャビティ６内の空気を外に排出することでボイド及び未充填を防ぐことができる。   The thin film 2 has a groove 9 extending from the sealing region sealed with the resin 7 to the outside of the multilayer substrate 1. When sealing with the resin 7, the upper die 5 is in contact with the upper surface of the thin film 2 at the portion other than the groove 9 in the outer peripheral portion of the multilayer substrate 1. By using the groove 9 as an air vent and discharging the air in the cavity 6 to the outside, it is possible to prevent voids and unfilling.

図２は、実施の形態１に係る半導体装置の製造方法を示す平面図である。図３は図２のＩ−ＩＩに沿った断面図である。多層基板１の基材の実装面に、薄膜２として、導電パターン１０と、導電パターン１０を覆うソルダレジスト１１とが形成されている。多層基板１の裏面にも同様に導電パターン１２とソルダレジスト１３が形成されている。なお、多層基板１の配線構造は何層でもかまわない。また、ソルダレジスト１３の開口部において半導体チップ３と多層基板１の導電パターン１０は銀ペースト又は金線などの導電性接合材で接続されているが、ここでは図示を省略している。   FIG. 2 is a plan view showing the method of manufacturing the semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view taken along line I-II of FIG. A conductive pattern 10 and a solder resist 11 covering the conductive pattern 10 are formed as the thin film 2 on the mounting surface of the base material of the multilayer substrate 1. The conductive pattern 12 and the solder resist 13 are similarly formed on the back surface of the multilayer substrate 1 as well. The wiring structure of the multilayer substrate 1 may be any number of layers. In the opening of the solder resist 13, the semiconductor chip 3 and the conductive pattern 10 of the multilayer substrate 1 are connected by a conductive bonding material such as a silver paste or a gold wire, but are not shown here.

本実施の形態の効果を比較例と比較して説明する。図４は、比較例に係る半導体装置の製造方法を示す断面図である。比較例では樹脂成型の際にキャビティ内の空気が上金型５に作られたエアベント１４から外に排出される。エアベント１４の形状が最適でない場合、空気が樹脂７内に留まってボイド又は未充填が発生し、逆に樹脂７がエアベント１４から溢れ出すオーバーフローが発生するなどの問題がある。このため、多層基板１に実装する半導体チップ３に合わせて上金型５にエアベント１４を設ける必要がある。従って、半導体チップ３が増減した場合に新規の金型が必要になり、コストがかかる。   The effect of the present embodiment will be described in comparison with a comparative example. FIG. 4 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the comparative example. In the comparative example, the air in the cavity is discharged from the air vent 14 formed on the upper mold 5 during resin molding. If the shape of the air vent 14 is not optimum, air remains in the resin 7 to cause voids or unfilling, and conversely, the resin 7 overflows from the air vent 14 and overflow occurs. Therefore, it is necessary to provide the upper mold 5 with the air vent 14 in accordance with the semiconductor chip 3 to be mounted on the multilayer substrate 1. Therefore, when the number of semiconductor chips 3 increases and decreases, a new mold is required, which is costly.

一方、本実施の形態では、多層基板１に設けた薄膜２の溝９をエアベントとして用いる。このように多層基板１にエアベントの機能を持たせることで、半導体チップ３が増減しても新規の金型は不要であるため、コストを削減することができる。   On the other hand, in the present embodiment, the groove 9 of the thin film 2 provided in the multilayer substrate 1 is used as an air vent. As described above, by providing the multi-layered substrate 1 with an air vent function, the cost can be reduced because a new mold is not necessary even if the semiconductor chip 3 increases or decreases.

また、本実施の形態では、薄膜２に形成された溝９は直線ではなく、２箇所の切り返し１５ａ，１５ｂを有する。即ち、溝９は、まず基板内側から外側に向かって進み、切り返し１５ａで基板内側に戻り、切り返し１５ｂで再び外側に向かって進む。このように樹脂７の流れの向きを変えることで、溝９の途中で樹脂７を留め、樹脂７のオーバーフローを防ぐことができる。   Further, in the present embodiment, the groove 9 formed in the thin film 2 is not a straight line, and has two cutbacks 15a and 15b. That is, the groove 9 first advances from the inside to the outside of the substrate, returns to the inside of the substrate by the turnback 15a, and advances to the outside again by the turnback 15b. By changing the flow direction of the resin 7 in this manner, it is possible to fasten the resin 7 in the middle of the groove 9 and prevent the resin 7 from overflowing.

実施の形態２．
図５は、実施の形態２に係る半導体装置の製造方法を示す平面図である。溝９の断面構造は実施の形態１と同様であるが、溝９の幅を最初の切り返し１５ａより外側で広げている。即ち、封止領域から外側に向かう途中で溝９の幅が広くなる。このように樹脂７の通り道の断面積を広げるとベルヌーイの法則から樹脂７の流れる速度を落とせる。従って、実施の形態１よりも短い距離で樹脂７を留めることができる。このため、溝９に必要な基板長を短くでき、基板コストを削減することができる。また、樹脂７の選定と条件設定の自由度が増える。 Second Embodiment
FIG. 5 is a plan view showing a method of manufacturing a semiconductor device according to the second embodiment. The cross-sectional structure of the groove 9 is the same as that of the first embodiment, but the width of the groove 9 is expanded outside the first cutback 15a. That is, the width of the groove 9 becomes wide on the way from the sealing region to the outside. As described above, when the cross-sectional area of the passage of the resin 7 is expanded, the flow velocity of the resin 7 can be reduced from Bernoulli's law. Therefore, the resin 7 can be held at a distance shorter than that of the first embodiment. Therefore, the substrate length required for the groove 9 can be shortened, and the substrate cost can be reduced. In addition, the degree of freedom in selecting the resin 7 and setting the conditions is increased.

また、封止領域側で溝９の幅は樹脂７のフィラー径より狭いことが好ましい。これにより、樹脂７のオーバーフローを更に防ぐことができる。ただし、封止領域側で溝９の幅を狭めることで空気を排出しづらくなるため、１つの半導体チップ３に対して溝９を複数形成することが好ましい。その他の構成及び効果は実施の形態１と同様である。   Further, the width of the groove 9 is preferably narrower than the filler diameter of the resin 7 on the sealing region side. Thereby, the overflow of the resin 7 can be further prevented. However, since it becomes difficult to discharge air by narrowing the width of the groove 9 on the sealing region side, it is preferable to form a plurality of grooves 9 in one semiconductor chip 3. Other configurations and effects are the same as in the first embodiment.

実施の形態３．
図６は、実施の形態３に係る半導体装置の製造方法を示す平面図である。図７は図６のＩ−ＩＩに沿った断面図である。導電パターン１０のソルダレジスト１１から露出した部分に溝９が形成されている。これにより、多層基板１を下金型４と上金型５で挟んだ際にソルダレジスト１１が潰れても溝９の幅が狭くなるのを防ぐことができる。従って、実施の形態２のように溝９の幅を狭くした場合でも設計値の溝幅を維持することができる。また、ソルダレジスト１１の潰れ量を考慮する必要がないため、型締め圧力の自由度が増える。その他の構成及び効果は実施の形態１と同様である。 Third Embodiment
FIG. 6 is a plan view showing a method of manufacturing a semiconductor device according to the third embodiment. 7 is a cross-sectional view taken along line I-II of FIG. A groove 9 is formed in a portion of the conductive pattern 10 exposed from the solder resist 11. Thus, when the multilayer substrate 1 is sandwiched between the lower mold 4 and the upper mold 5, the width of the groove 9 can be prevented from being narrowed even if the solder resist 11 is crushed. Therefore, even when the width of the groove 9 is narrowed as in the second embodiment, the designed groove width can be maintained. Further, since it is not necessary to consider the amount of collapse of the solder resist 11, the degree of freedom of the clamping pressure is increased. Other configurations and effects are the same as in the first embodiment.

１ 多層基板、３ 半導体チップ、４ 下金型、５ 上金型、７ 樹脂、９ 溝、１０ 導電パターン（薄膜）、１１ ソルダレジスト（薄膜）、１５ａ，１５ｂ 切り返し REFERENCE SIGNS LIST 1 multi-layer substrate 3 semiconductor chip 4 lower mold 5 upper mold 7 resin 9 groove 10 conductive pattern (thin film) 11 solder resist (thin film) 15 a, 15 b cut back

Claims (4)

多層基板の実装面に薄膜を形成する工程と、
前記多層基板の前記実装面に半導体チップを実装する工程と、
前記多層基板を下金型と上金型で挟んで前記半導体チップを樹脂で封止する工程とを備え、
前記薄膜は、前記樹脂で封止される封止領域から前記多層基板の外側まで延びる溝を有し、
前記樹脂で封止する際に、前記多層基板の外周部において前記薄膜の上面と前記上金型が接し、前記溝をエアベントとして用い、
前記溝は切り返しを有することを特徴とする半導体装置の製造方法。 Forming a thin film on the mounting surface of the multilayer substrate;
Mounting a semiconductor chip on the mounting surface of the multilayer substrate;
Sandwiching the multilayer substrate between a lower mold and an upper mold and sealing the semiconductor chip with a resin;
The thin film has a groove extending from a sealing region sealed with the resin to the outside of the multilayer substrate,
When sealing with the resin, the upper surface of the thin film is in contact with the upper mold at the outer peripheral portion of the multilayer substrate, and the groove is used as an air vent,
The method for manufacturing a semiconductor device, wherein the groove has a turn. 前記封止領域から外側に向かう途中で前記溝の幅が広くなることを特徴とする請求項１に記載の半導体装置の製造方法。   The method for manufacturing a semiconductor device according to claim 1, wherein the width of the groove becomes wide on the way from the sealing region to the outside. １つの前記半導体チップに対して前記溝を複数形成することを特徴とする請求項１又は２に記載の半導体装置の製造方法。   3. The method of manufacturing a semiconductor device according to claim 1, wherein a plurality of the grooves are formed in one of the semiconductor chips. 前記薄膜は、導電パターンと、前記導電パターンを覆うソルダレジストとを有し、
前記導電パターンの前記ソルダレジストから露出した部分に前記溝が形成されていることを特徴とする請求項１〜３の何れか１項に記載の半導体装置の製造方法。 The thin film has a conductive pattern and a solder resist covering the conductive pattern,
The method for manufacturing a semiconductor device according to claim 1, wherein the groove is formed in a portion of the conductive pattern exposed from the solder resist.
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