CN100463132C - Chip packaging structure and manufacturing method therefor - Google Patents
Chip packaging structure and manufacturing method therefor Download PDFInfo
- Publication number
- CN100463132C CN100463132C CNB2006101040618A CN200610104061A CN100463132C CN 100463132 C CN100463132 C CN 100463132C CN B2006101040618 A CNB2006101040618 A CN B2006101040618A CN 200610104061 A CN200610104061 A CN 200610104061A CN 100463132 C CN100463132 C CN 100463132C
- Authority
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- China
- Prior art keywords
- base plate
- circuit base
- wafer
- perforation
- rete
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 38
- 238000004806 packaging method and process Methods 0.000 title description 2
- 239000000084 colloidal system Substances 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims description 33
- 239000000463 material Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 abstract description 4
- 238000005538 encapsulation Methods 0.000 abstract description 2
- 238000003466 welding Methods 0.000 abstract 7
- 235000012431 wafers Nutrition 0.000 description 49
- 239000000853 adhesive Substances 0.000 description 12
- 230000001070 adhesive effect Effects 0.000 description 12
- 239000003292 glue Substances 0.000 description 6
- 238000012545 processing Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005484 gravity Effects 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Dicing (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The present invention relates to a manufacturing method for the wafer encapsulation structure, and includes the following steps: firstly, a circuitry substrate with a first surface, a second surface and a through-hole connected with the two surfaces are provided. Secondly, a wafer with an active surface and a plurality of welding washers arranged on the active surface are provided. Thirdly, the wafer is fixed on the circuitry substrate, the second surface is face to face with the active surface, and the through-hole exposes the welding washers. Fourthly, a plurality of welding lines passed the through-hole and connected electrically with the welding washers and the first surface are formed. Fifthly, a film layer with one opening hole is formed on the first surface. The opening hole exposes the welding lines, the welding washers and the through-hole and a part of the first surface. Sixthly, a colloid is formed inside the opening hole and the through-hole to pack a part of the active surface, the welding lines and a part of the first surface. Lastly, the film layer is removed. Thereby the colloid overflow phenomenon can be mended, and the manufacturing cost can be reduced.
Description
Technical field
The present invention relates to a kind of semiconductor element and manufacture method thereof, particularly relate to a kind of chip package structure and manufacture method thereof.
Background technology
In semiconductor industry, (integrated circuits, production IC) mainly can be divided into three phases to integrated circuit: the encapsulation (IC package) of the making (ICprocess) of the design of integrated circuit (IC design), integrated circuit and integrated circuit.
In the making of integrated circuit, wafer (chip) is to finish via wafer (wafer) making, formation integrated circuit and cutting crystal wafer steps such as (wafer sawing).Wafer has an active surface (active surface), the surface with active member (active devicc) of its general reference wafer.After the integrated circuit of wafer inside was finished, the active surface of wafer more disposed a plurality of weld pads (bonding pad), can outwards be electrically connected at a carrier (carrier) via these weld pads so that finally cut formed wafer by wafer.Carrier for example is a lead frame (leadframe) or a base plate for packaging (package substrate).The mode that wafer can routing engages (wire bonding) or chip bonding (flip chip bonding) is connected on the carrier, makes these weld pads of wafer can be electrically connected at the contact of carrier, to constitute a chip package structure.
See also shown in Figure 1ly, it is the generalized section of existing a kind of chip package structure.Existing chip package structure 100 comprises a circuit base plate (wiring substrate) 110, one wafer 120, many bonding wires (bonding wire) 130, colloid (encapsulant) 140 and a plurality of soldered balls (solderball) 150.Wherein, circuit base plate 110 has a first surface 112, a second surface 114 and a perforation (through hole) 116, and perforation 116 connects first surface 112 and second surface 114.In addition, wafer 120 has an active surface 122 and a plurality of weld pads 124, and wherein these weld pads 124 are disposed on the active surface 122, and the active surface 122 of the second surface 114 of circuit base plate 110 and wafer 120 toward each other, and perforation 116 exposes these weld pads 124.
These bonding wires 130 connect the first surface 112 of these weld pads 124 and circuit base plate 110 respectively, and these bonding wires 130 are by perforation 116.Colloid 140 coats (encapsulate) part active surface 122, these bonding wires 130 and part first surface 112, and wherein colloid 140 has an end face 142, a bottom surface 144 and a sidewall 146 that is positioned on the first surface 112.The end face 142 of colloid 140 is away from first surface 112, and bottom surface 144 contacts with part first surface 112, and the area of bottom surface 144 is greater than the area of end face 142, makes to form a draft angle θ between the vertical line of sidewall 146 and first surface 112.
The external form of colloid 140 is identical with the external form of the die cavity of sealing (molding) mould that processing procedure uses (not illustrating), can break away from the employed mould of manufacture procedure of adhesive smoothly and the function of draft angle θ is the chip package structure 100 that makes sealing finish.Therefore when carrying out manufacture procedure of adhesive, the external form of wafers having different sizes encapsulating structure 100 its top and the bottom of employed mould is inconsistent, so will increase the cost of Mold Making.In addition, when carrying out manufacture procedure of adhesive, produce excessive glue (flash) phenomenon sometimes and the first surface 112 of contamination line base board 110.
Summary of the invention
The manufacture method that the purpose of this invention is to provide a kind of chip package structure is produced the glue phenomenon of overflowing to improve in manufacture procedure of adhesive.
Another object of the present invention provides a kind of chip package structure, and the cost of manufacture of the employed mould of its manufacture procedure of adhesive is lower.
For reaching above-mentioned or other purposes, the present invention proposes a kind of manufacture method of chip package structure, and it comprises the following steps.At first, provide a circuit base plate.Circuit base plate has a first surface, a second surface and a perforation, and perforation connects first surface and second surface.Then, provide a wafer.Wafer has an active surface and a plurality of weld pad, and these weld pads are disposed on the active surface.Then, wafer is bonded on the circuit base plate, wherein the active surface of the second surface of circuit base plate and wafer toward each other and perforation expose these weld pads.Afterwards, form many bonding wires by perforation, wherein these weld pads are electrically connected to the first surface of circuit base plate respectively by these bonding wires.Afterwards, form a rete (film) on the first surface of circuit base plate, wherein rete has a perforate (opening), and perforate exposes these bonding wires, these weld pads, perforation and part first surface.Then, in perforate and perforation, form colloid, with covered section active surface, these bonding wires and part first surface.Then, remove rete.
In one embodiment of this invention, the material of above-mentioned rete for example is to comprise pi flexible films such as (polyimide).
In one embodiment of this invention, the above-mentioned mode that removes rete comprises and removing.
In one embodiment of this invention, the manufacture method of above-mentioned chip package structure is before the step that forms colloid, more comprise one first mould and one second mould are provided, wherein first mould and second mould form a die cavity jointly, make wafer, circuit base plate, these bonding wires and rete be positioned at die cavity, and first mould is pressed on the rete and cover perforate, and the second surface of the second mould cover wafers and circuit base plate.
In one embodiment of this invention, the manufacture method of above-mentioned chip package structure more comprises forming a plurality of soldered balls on the first surface of circuit base plate after removing the step of rete.
For reaching above-mentioned or other purposes, the present invention proposes a kind of chip package structure, and it comprises a circuit base plate, a wafer, many bonding wires and colloid.Circuit base plate has a first surface, a second surface and a perforation, and perforation connects first surface and second surface.Wafer configuration is on circuit base plate and have an active surface and a plurality of weld pad, and wherein these weld pads are disposed on the active surface, and the active surface of the second surface of circuit base plate and wafer toward each other, and perforation exposes these weld pads.These bonding wires connect the first surface of these weld pads and circuit base plate respectively, and these bonding wires pass through perforation.Colloid covered section active surface, these bonding wires and part first surface, wherein colloid has an end face and a bottom surface that is positioned on the first surface, end face is away from first surface, and the bottom surface contacts with the part first surface, and the difference of the width of the width of end face and bottom surface 1/2nd divided by the absolute value of distance ratio between end face and the bottom surface smaller or equal to 0.2.
In one embodiment of this invention, above-mentioned chip package structure more comprises a plurality of soldered balls, is disposed on the first surface of circuit base plate.
Based on above-mentioned, because the present invention before carrying out manufacture procedure of adhesive, forms rete earlier on the first surface of circuit base plate, therefore in manufacture procedure of adhesive, this rete can improve the glue phenomenon of overflowing.In addition, owing to adopt rete,, therefore can reduce the manufacturing cost of mould, and then reduce the manufacturing cost of wafer assembling structure of the present invention so can adopt the first identical mould for the wafers having different sizes encapsulating structure.In addition, owing to after carrying out manufacture procedure of adhesive, just remove rete, so the sidewall of the colloid of chip package structure of the present invention and the first surface approximate vertical of circuit base plate.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 is the generalized section of existing a kind of chip package structure.
Fig. 2 is the generalized section of the chip package structure of one embodiment of the invention.
Fig. 3 A to Fig. 3 H is the schematic diagram of manufacture method of the chip package structure of one embodiment of the invention.
100,200: chip package structure 110,210: circuit base plate
112,212: first surface 114,214: second surface
116,216: perforation 120,220: wafer
122,222: active surface 124,224: weld pad
130,230: bonding wire 140,240: colloid
142,242: end face 144,244: bottom surface
146,246: sidewall 150,250: soldered ball
226: the back side C of wafer: die cavity
D: end face and bottom surface apart from F: rete
G: adhesion glue M1: first mould
M2: second mould 0: perforate
W1: the width w2 of end face: the width of bottom surface
θ: draft angle
Embodiment
See also shown in Figure 2ly, it is the generalized section of the chip package structure of one embodiment of the invention.The chip package structure 200 of present embodiment comprises a circuit base plate 210, a wafer 220, many bonding wires 230 and colloid 240.Circuit base plate 210 has a first surface 212, a second surface 214 and a perforation 216, and wherein perforation 216 connects first surface 212 and second surface 214.Wafer 220 is disposed on the circuit base plate 210, and wafer 220 has an active surface 222 and a plurality of weld pads 224, wherein these weld pads 224 are disposed on the active surface 222, and the active surface 222 of the second surface 214 of circuit base plate 210 and wafer 220 toward each other, and perforation 216 exposes these weld pads 224.
These bonding wires 230 connect the first surface 212 of these weld pads 224 and circuit base plate 210 respectively, and these bonding wires 230 are by perforation 216.In addition, these bonding wires 230 are in order to the media as electric connection between wafer 220 and the circuit base plate 210.In addition, colloid 240 covered section active surfaces 222, these bonding wires 230 and part first surface 212.As shown in Figure 2, in the present embodiment, colloid 240 is the back side 226 of second surface 214 and the wafer 220 of covering thread base board 210 more.In this mandatory declaration is that the function of colloid 240 is for protecting these bonding wires 230 to avoid being subjected to extraneous moisture, heat and The noise.
Below describe for the manufacture method of the chip package structure 200 of present embodiment.Fig. 3 A to Fig. 3 H is the schematic diagram of manufacture method of the chip package structure of one embodiment of the invention.The manufacture method of the chip package structure 200 of present embodiment comprises the following steps.At first, see also shown in Fig. 3 A, a circuit base plate 210 is provided.Circuit base plate 210 has a first surface 212, a second surface 214 and at least one perforation 216 (Fig. 3 A only illustrates two), and wherein each perforation 216 connects first surface 212 and second surface 214.
Then, provide at least one wafer 220 (Fig. 3 A only illustrates two).Each wafer 220 has an active surface 222 and a plurality of weld pads 224, and wherein these weld pads 224 are disposed on the active surface 222.In addition, the active surface 222 of each wafer 220 is towards the second surface 214 of circuit base plate 210.
See also shown in Fig. 3 B, these wafers 220 be bonded on the circuit base plate 210, wherein the active surface 222 of the second surface 214 of circuit base plate 210 and each wafer 220 toward each other, and these perforations 216 expose these weld pads 224.In the present embodiment, these wafers 220 are to be bonded on the circuit base plate 210 by adhesion glue G.
See also shown in Fig. 3 C, form many bonding wires 230, and these weld pads 224 of each wafer 220 are electrically connected to the first surface 212 of circuit base plate 210 respectively by these bonding wires 230 by these perforations 216.In other words, these bonding wires 230 are in order to the media as electric connection between these wafers 220 and the circuit base plate 210.
See also shown in Fig. 3 D, form a rete F on the first surface 212 of circuit base plate 210, wherein rete F has at least one perforate 0 (Fig. 3 D only illustrates two), and these perforates 0 expose these bonding wires 230, these weld pads 224, these perforations 216 and part first surface 212.In the present embodiment, the material of rete F for example comprises pi.In addition, the mode of formation rete F can be to attach.
See also shown in Fig. 3 E, one first mould M1 and one second mould M2 are provided, wherein the first mould M1 and the second mould M2 are common forms a die cavity C, and these wafers 220, circuit base plate 210, these bonding wires 230 and rete F are positioned at die cavity C.In addition, the first mould M1 is pressed on the rete F, and covers these perforates 0.The second surface 214 of the second mould M2 cover wafers 220 and circuit base plate 210.
See also shown in Fig. 3 F, carry out manufacture procedure of adhesive, that is in these perforates 0 and these perforations 216, form colloid 240, with covered section active surface 222, these bonding wires 230 and part first surfaces 212.In addition, the material of colloid 240 for example is a resin.In the present embodiment, colloid 240 back side 226 of second surface 214 and the wafer 220 of covering thread base board 210 more.In addition, after injecting the material that forms colloid 240, carry out a curing process, to form colloid 240.
See also shown in Fig. 3 G, remove the first mould M1, the second mould M2 and rete F.In the present embodiment, the mode that removes rete F comprises and removing, and can reach by the mode of artificial or mechanical automation and remove rete F.
See also shown in Fig. 3 H, in the present embodiment, can form a plurality of soldered balls 250 on the first surface 212 of circuit base plate 210, with media as the electronic installation (not illustrating) that electrically connects next level.In addition, the mode that forms these soldered balls 250 can be disposed at the former material of soldered ball 250 on the preposition by vacsorb (vacuum transfer) or the gravity modes such as (gravity transfer) of waving, and carries out reflow (reflow) processing procedure again and forms.In addition, after forming these soldered balls 250, can carry out singulation (singulation) processing procedure, to form a plurality of chip package structures 200.
In sum, chip package structure of the present invention and manufacture method thereof have the following advantages at least:
One, because the present invention before carrying out manufacture procedure of adhesive, forms rete earlier on the first surface of circuit base plate, therefore in manufacture procedure of adhesive, this rete can improve the glue phenomenon of overflowing.
Two, for the wafers having different sizes encapsulating structure, as long as just arranging in pairs or groups with the width of opening, the thickness of change rete uses the first identical mould, therefore can reduce the manufacturing cost of mould, and then reduce the manufacturing cost of wafer assembling structure of the present invention.In addition, with regard to configuration aspects, owing to after carrying out manufacture procedure of adhesive, just remove rete, so the sidewall of the colloid of chip package structure of the present invention and the first surface approximate vertical of circuit base plate.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (7)
1. the manufacture method of a chip package structure is characterized in that it comprises:
One circuit base plate is provided, and this circuit base plate has a first surface, a second surface and a perforation, and this perforation connects this first surface and this second surface;
One wafer is provided, and this wafer has an active surface and a plurality of weld pad, and these a plurality of weld pads are disposed on this active surface;
This wafer is bonded on this circuit base plate, wherein this active surface of this second surface of this circuit base plate and this wafer toward each other and this perforation expose this a plurality of weld pads;
Form many bonding wires by this perforation, wherein these a plurality of weld pads are electrically connected to this first surface of this circuit base plate respectively by these many bonding wires;
Form a rete on this first surface of this circuit base plate, wherein this rete has a perforate, and this perforate exposes these many bonding wires, these a plurality of weld pads, this perforation and this first surface of part;
In this perforate and this perforation, form colloid, with this active surface of covered section, these many bonding wires and this first surface of part; And
Remove this rete.
2. the manufacture method of chip package structure according to claim 1 is characterized in that the material of wherein said rete comprises pi.
3. the manufacture method of chip package structure according to claim 1 is characterized in that the wherein said mode that removes this rete comprises to remove.
4. the manufacture method of chip package structure according to claim 1, it is characterized in that wherein said before the step that forms this colloid, more comprise one first mould and one second mould are provided, wherein this first mould and this second mould form a die cavity jointly, make this wafer, this circuit base plate, these many bonding wires and this rete be positioned at this die cavity, and this first mould is pressed on this rete and cover this perforate, and this second mould covers this second surface of this wafer and this circuit base plate.
5. the manufacture method of chip package structure according to claim 1 is characterized in that wherein saidly after removing the step of this rete, more comprises forming a plurality of soldered balls on this first surface of this circuit base plate.
6. chip package structure is characterized in that it comprises:
One circuit base plate has a first surface, a second surface and a perforation, and this perforation connects this first surface and this second surface;
One wafer is disposed on this circuit base plate and has an active surface and a plurality of weld pad, and wherein these a plurality of weld pads are disposed on this active surface, and this active surface of this second surface of this circuit base plate and this wafer toward each other, and this perforation exposes this a plurality of weld pads; And
Many bonding wires connect this first surface of these a plurality of weld pads and this circuit base plate respectively, and these many bonding wires are by this perforation; And
Colloid, this active surface of covered section, these many bonding wires and this first surface of part, wherein this colloid has an end face and a bottom surface that is positioned on this first surface, this end face is away from this first surface, and this bottom surface contacts with this first surface of part, and the difference of the width of the width of this end face and this bottom surface 1/2nd divided by the absolute value of distance ratio between this end face and this bottom surface smaller or equal to 0.2.
7. chip package structure according to claim 6 is characterized in that it more comprises a plurality of soldered balls, is disposed on this first surface of this circuit base plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101040618A CN100463132C (en) | 2006-07-31 | 2006-07-31 | Chip packaging structure and manufacturing method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101040618A CN100463132C (en) | 2006-07-31 | 2006-07-31 | Chip packaging structure and manufacturing method therefor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101118861A CN101118861A (en) | 2008-02-06 |
| CN100463132C true CN100463132C (en) | 2009-02-18 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006101040618A Expired - Fee Related CN100463132C (en) | 2006-07-31 | 2006-07-31 | Chip packaging structure and manufacturing method therefor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100463132C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8772087B2 (en) | 2009-10-22 | 2014-07-08 | Infineon Technologies Ag | Method and apparatus for semiconductor device fabrication using a reconstituted wafer |
| CN112830448B (en) * | 2021-01-19 | 2023-12-26 | 潍坊歌尔微电子有限公司 | Microphone packaging technology and microphone packaging structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6190943B1 (en) * | 2000-06-08 | 2001-02-20 | United Test Center Inc. | Chip scale packaging method |
| CN2502404Y (en) * | 2001-08-30 | 2002-07-24 | 南茂科技股份有限公司 | Mould pressing tool for preventing glue-spilling semicondcutor encapsulating die press |
| CN1405869A (en) * | 2001-09-18 | 2003-03-26 | 南茂科技股份有限公司 | Method for packaging substrate on wafer |
-
2006
- 2006-07-31 CN CNB2006101040618A patent/CN100463132C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6190943B1 (en) * | 2000-06-08 | 2001-02-20 | United Test Center Inc. | Chip scale packaging method |
| CN2502404Y (en) * | 2001-08-30 | 2002-07-24 | 南茂科技股份有限公司 | Mould pressing tool for preventing glue-spilling semicondcutor encapsulating die press |
| CN1405869A (en) * | 2001-09-18 | 2003-03-26 | 南茂科技股份有限公司 | Method for packaging substrate on wafer |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101118861A (en) | 2008-02-06 |
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