CN2502404Y - Mould pressing tool for preventing glue-spilling semicondcutor encapsulating die press - Google Patents
Mould pressing tool for preventing glue-spilling semicondcutor encapsulating die press Download PDFInfo
- Publication number
- CN2502404Y CN2502404Y CN 01233087 CN01233087U CN2502404Y CN 2502404 Y CN2502404 Y CN 2502404Y CN 01233087 CN01233087 CN 01233087 CN 01233087 U CN01233087 U CN 01233087U CN 2502404 Y CN2502404 Y CN 2502404Y
- Authority
- CN
- China
- Prior art keywords
- die
- glue
- mold
- semicondcutor
- circuit substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000003825 pressing Methods 0.000 title abstract description 13
- 239000003292 glue Substances 0.000 claims abstract description 44
- 208000002925 dental caries Diseases 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 12
- 239000007788 liquid Substances 0.000 abstract description 8
- 239000004065 semiconductor Substances 0.000 abstract description 6
- 239000000377 silicon dioxide Substances 0.000 abstract description 6
- 229920005989 resin Polymers 0.000 abstract description 4
- 239000011347 resin Substances 0.000 abstract description 4
- 239000003795 chemical substances by application Substances 0.000 abstract description 3
- 239000012778 molding material Substances 0.000 abstract 2
- 230000004888 barrier function Effects 0.000 abstract 1
- 238000004806 packaging method and process Methods 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 30
- 235000012431 wafers Nutrition 0.000 description 17
- 238000005538 encapsulation Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 239000000945 filler Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 239000002390 adhesive tape Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000004040 coloring Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000010412 perfusion Effects 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
A pressing tool preventing glue overflow of the semiconductor packaging stamp is provided, a lower module forms a glue overflow conduit at the two sides of the edge of the lower module. As the reserve space for the liquid resin in the molding material, a barrier forms between the glue overflow conduit and the edge of the lower module to resist the silica loading agent in the molding material, which can limit the overflowing liquid resin in the glue overflow conduit and prevents the further enlargement of the glue overflow area to cause the difficult balling situation.
Description
Technical field
The utility model relates to a kind of stamper tool that prevents excessive glue of semicondcutor encapsulating die press, particularly be formed with the glue conduit that overflows in the dip mold both sides of edges relevant for a kind of bed die, with prevent substrate on wafer kenel (Substrate-On-Chip SOC) produces the stamper tool of the glue phenomenon of overflowing during semiconductor packages.
Background technology
The semiconductor package that in traditional semiconductor package, includes a kind of SOC kenel, so-called " SOC encapsulation " is the Substrate-On-Chip encapsulation, be the abbreviation of substrate on wafer, it is to be pasted on a wafer with a circuit substrate with window, and pass this window connecting circuit substrate and wafer with most metal bonding wires, this circuit substrate also is formed with the soldered ball of most arranged, as shown in Figure 1, traditional SOC encapsulating structure 10 is to include a circuit substrate 12, one wafer 11 and most soldered balls 13, this circuit substrate 12 is to utilize adhesive tape 14 and wafer 11 mutual cementations, make wafer 11 be fixed in upper surface 1 2c of circuit substrate 12, because circuit substrate 12 has an opening 12a, can expose the weld pad in the middle of wafer 11, make metal bonding wire 15 can pass opening 12a, to electrically connect wafer 11 and circuit substrate 12, utilize pressing mold (molding) method to form seal glue 16 again, most soldered balls 13 of welding afterwards are in the solder ball pad 12d of the lower surface 12b of this circuit substrate 12, because the seal glue 16 salable coating entire wafer 11 that pressing mold forms need not be exposed the brilliant back of the body.
Can announce No. 404563 with reference to the Taiwan patent gazette about the SOC encapsulating structure that forms with pressing mold, be to have more preferable wafer sealing protection performance than a notes (potting) and printing technology such as (printing) so form seal glue 16 in the pressing mold mode in this SOC encapsulating structure 10.
In above-mentioned SOC encapsulating structure 10, as shown in Figure 2, be to be stained with the circuit substrate 12 of wafer 11 with mold 20 and bed die 30 clampings when the pressing mold process, because mold 20 must have the die cavity space greater than wafer 11, make the top die edge 21 of mold 20 contact circuit substrates 12 be distal to the dip mold edge 31 of bed die 30, that is to say that the upper surface 12c of circuit substrate 12 at 31 places, dip mold edge lacks the downward pressure force of mold 20, cause seal glue 16 to invade crack between circuit substrate 12 and the bed die 30 easily, be 31 places, dip mold edge, produce the glue phenomenon of overflowing, even the solder ball pad 12d of pollution circuit board substrate 12, cause the difficulty that grafts soldered ball 13, this also is the problem that present SOC encapsulation often suffers from.
Summary of the invention
Main purpose of the present utility model is to provide a kind of stamper tool that prevents excessive glue of semicondcutor encapsulating die press, utilize bed die to be formed with excessive glue conduit in the dip mold both sides of edges, as liquid resinous spare space in the seal glue, and between excessive glue conduit and dip mold edge, form a retaining dike, stop the silica filler in the seal glue, the liquid resin that can limit to overflow is in excessive glue conduit, reach the situation generation that prevents that further excessive glue face from enlarging, and cause the purpose of the difficulty of planting ball.
The purpose of this utility model is achieved in that a kind of stamper tool that prevents excessive glue of semicondcutor encapsulating die press, it includes and has upper mould cave and at the mold at the top die edge of upper mould cave periphery, and have most die cavitys and at the bed die at the dip mold edge of die cavity periphery down down, it is characterized in that: the dip mold both sides of edges of this bed die is formed with the excessive glue conduit of the spare space of filling for seal glue.
One side of this mold is formed with at least one gum-injecting port.The following die cavity of this bed die is strip.
Further specify below in conjunction with preferred embodiment and accompanying drawing
Description of drawings
Fig. 1 is the schematic cross-section of traditional SOC encapsulating structure.
Fig. 2 is the schematic cross-section of traditional SOC encapsulating structure at the pressing mold state.
Fig. 3 is the schematic cross-section figure of SOC encapsulating structure of the present utility model at the pressing mold state.
Fig. 4 is the end face schematic diagram of bed die of the present utility model.
Fig. 5 is the end face schematic diagram of SOC encapsulating structure of the present utility model at the circuit substrate of pressing mold state.
Embodiment
Consult Fig. 3-shown in Figure 5, the utility model is the innovative technology that prevents the excessive improper pollution of glue in the pressing mold process of SOC encapsulation, as shown in Figure 3, a kind of bed die 130 of the SOC of being applicable to kenel semiconductor packages is to have die cavity 133 under most the strips, it is in the scope that dip mold edge 131 is centered on, and corresponding to the slotted opening 112a of circuit substrate 112, be formed with the glue conduit 132 that overflows in the both sides at dip mold edge 131, as the liquid resinous spare space of overflow in the limitation seal glue, to prevent the further generation of excessive glue, reduce the chance of polluting circuit substrate 112 solder ball pad 11d.
As shown in Figure 3, before the pressing mold of a large amount of production SOC kenel semiconductor packages, in advance at most wafers 111 of the upper surface 112c of a circuit substrate 112 cementation, and pass the window 112a of circuit substrate 112 with most metal bonding wires 115, electrically connect the lower surface 112b of wafer 111 to circuit substrate 112, in the pressing mold process, the circuit substrate 112 that is combined with wafer 111 is with a mold 120 and aforesaid bed die 130 clampings, with the perfusion seal glue, so-called seal glue is to be a kind of insulating properties thermosetting compound, traditional composition includes silica and fills material (silica filler), the curing agent of epoxy resin and a spot of phenol resin and so on, curing accelerator and colouring agent etc., wherein silica is filled material and is accounted for more than 50% of percentage, be a kind of solid particles, and epoxy resin is to be in a liquid state, and has flowability before curing.
In the present embodiment, seal glue is gum-injecting port 122 importings by mold 120, as shown in Figure 5, gum-injecting port 122 is sides that are positioned at mold 120, and have most individual corresponding to the sticking brilliant number of permutations of circuit substrate 112, flow in order to the balance mould, avoid the excessive flow surface of radian, at first seal glue is the upper mould cave 123 (between the top die edge 121 of mold 120) that is filled in the upper surface 112c of mold 120 and circuit substrate 112, and form one toward lower compression power, make the lower surface 112b of circuit substrate 112 and the dip mold edge 131 of bed die 130 have the urgent power of enhancing, to prevent the glue that overflows.Embodiment preferably, as shown in Figure 5, circuit substrate 112 is formed with material hole 112e between gum-injecting port 122 and adjacent wafer 111, flow into die cavity 133 down for seal glue by upper mould cave 123, when seal glue is flowed under the strip that the lower surface 112b by bed die 130 and circuit substrate 112 constituted die cavity 133 by upper mould cave 123, as shown in Figure 3, bed die 130 is originally at the retaining dike 134 that overflows and form between glue conduit 132 and the dip mold edge 131, the silica filler that can stop solid particles in the seal glue, and the excessive glue conduit 132 of 131 both sides, dip mold edge is as liquid resinous spare space in the seal glue, the limitation liquid resin is at the overflow area of circuit substrate 112 lower surface 112b, can reach the effect of the solder ball pad 112d that prevents to pollute circuit substrate 112, promote follow-up acceptance rate of planting the ball step in the SOC encapsulation flow process.
More than be preferred embodiment of the present utility model, anyly know this skill person, variation and the modification done in not breaking away from spirit and scope of the present utility model all belong to protection range of the present utility model.
Claims (3)
1, a kind of stamper tool that prevents excessive glue of semicondcutor encapsulating die press, it includes and has upper mould cave and at the mold at the top die edge of upper mould cave periphery, and have most die cavitys and at the bed die at the dip mold edge of die cavity periphery down down, it is characterized in that: the dip mold both sides of edges of this bed die is formed with the excessive glue conduit of the spare space of filling for seal glue.
2, the stamper tool that prevents excessive glue of semicondcutor encapsulating die press according to claim 1, it is characterized in that: a side of this mold is formed with at least one gum-injecting port.
3, the stamper tool that prevents excessive glue of semicondcutor encapsulating die press according to claim 1, it is characterized in that: the following die cavity of this bed die is strip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01233087 CN2502404Y (en) | 2001-08-30 | 2001-08-30 | Mould pressing tool for preventing glue-spilling semicondcutor encapsulating die press |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01233087 CN2502404Y (en) | 2001-08-30 | 2001-08-30 | Mould pressing tool for preventing glue-spilling semicondcutor encapsulating die press |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2502404Y true CN2502404Y (en) | 2002-07-24 |
Family
ID=33647009
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 01233087 Expired - Lifetime CN2502404Y (en) | 2001-08-30 | 2001-08-30 | Mould pressing tool for preventing glue-spilling semicondcutor encapsulating die press |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2502404Y (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100394569C (en) * | 2005-07-06 | 2008-06-11 | 乾坤科技股份有限公司 | Method for preventing overflow of glue of package element |
| CN100463132C (en) * | 2006-07-31 | 2009-02-18 | 南茂科技股份有限公司 | Chip packaging structure and manufacturing method therefor |
| CN101546735B (en) * | 2005-08-17 | 2011-08-17 | 南茂科技股份有限公司 | Packaging structure of bug-hole downwards wafer and manufacturing method thereof |
| CN102729409A (en) * | 2012-06-27 | 2012-10-17 | 昆山市飞荣达电子材料有限公司 | Mold glue overflow-preventing keep-space structure |
| CN102130019B (en) * | 2010-01-14 | 2013-09-11 | 日月光半导体制造股份有限公司 | Semiconductor packaging process and die utilized in same |
| CN103779239A (en) * | 2012-10-25 | 2014-05-07 | 广东美的制冷设备有限公司 | Method for manufacturing intelligent power module and intelligent power module |
| CN104374123A (en) * | 2013-08-12 | 2015-02-25 | 浙江盾安热工科技有限公司 | Microchannel heat exchanger |
-
2001
- 2001-08-30 CN CN 01233087 patent/CN2502404Y/en not_active Expired - Lifetime
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100394569C (en) * | 2005-07-06 | 2008-06-11 | 乾坤科技股份有限公司 | Method for preventing overflow of glue of package element |
| CN101546735B (en) * | 2005-08-17 | 2011-08-17 | 南茂科技股份有限公司 | Packaging structure of bug-hole downwards wafer and manufacturing method thereof |
| CN100463132C (en) * | 2006-07-31 | 2009-02-18 | 南茂科技股份有限公司 | Chip packaging structure and manufacturing method therefor |
| CN102130019B (en) * | 2010-01-14 | 2013-09-11 | 日月光半导体制造股份有限公司 | Semiconductor packaging process and die utilized in same |
| CN102729409A (en) * | 2012-06-27 | 2012-10-17 | 昆山市飞荣达电子材料有限公司 | Mold glue overflow-preventing keep-space structure |
| CN103779239A (en) * | 2012-10-25 | 2014-05-07 | 广东美的制冷设备有限公司 | Method for manufacturing intelligent power module and intelligent power module |
| CN103779239B (en) * | 2012-10-25 | 2016-08-03 | 广东美的制冷设备有限公司 | The manufacture method of a kind of SPM and SPM |
| CN104374123A (en) * | 2013-08-12 | 2015-02-25 | 浙江盾安热工科技有限公司 | Microchannel heat exchanger |
| CN104374123B (en) * | 2013-08-12 | 2018-07-06 | 浙江盾安热工科技有限公司 | A kind of micro-channel heat exchanger |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: BAIMUDA NANMAO SCIENCE & TECHNOLOGY CO., LTD. Free format text: FORMER OWNER: NANMAO SCIENCE + TECHNOLOGY CO., LTD. Effective date: 20040806 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20040806 Address after: Bermuda, England Patentee after: Bermuda ChipMos Technologies Co., Ltd. Address before: Hsinchu Science Industrial Park, Taiwan Patentee before: ChipMOS Technologies Co., Ltd. |
|
| C17 | Cessation of patent right | ||
| CX01 | Expiry of patent term |
Expiration termination date: 20110830 Granted publication date: 20020724 |