JP2003100957A - Semiconductor package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid making a semiconductor device detective, if the quantity of a coating resin increases to overflow to a solder bowl in a seal step, depending on the condition of the device, and reduce the height variation of a finished sealed surface between samples with simplifying the control of the resin coating quantity, if the quantity of the coating resin varies in the coating step. SOLUTION: For a BGA package of a type for sealing with an epoxy resin, without using dies, a second dam is formed outside a dam provided for preventing the resin from flowing into a solder bowl.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly to a package which is sealed by applying an epoxy resin and curing it by baking without using a mold in the sealing step.

[0002]

2. Description of the Related Art A conventional semiconductor package will be described with reference to the drawings. FIG. 9A is a plan view of a conductor package based on JP-A-10-351443 of the prior art seen from the solder ball side, and FIG. 9B is taken along the line AA ′ of FIG. 9A. FIG. The package 1 is made of metal, organic plastic, or the like, and has a cavity 7 that is a recess for mounting the LSI chip 2 in the center. This cavity 7 is formed by die processing or organic plastic substrate lamination. Stitches 8 serving as electrodes for electrically connecting the LSI chip 2 and the package 1 are formed around the cavity 7. The stitch 8 is formed by forming a conductive layer on the insulating layer by a plating method and patterning the conductive layer using a photolithography technique. On the outer periphery of the package 1, solder balls 3 made of a material such as eutectic solder are arranged in a grid pattern. The solder balls 3 and the stitches 8 are electrically connected by the internal wiring of the package 1. A ring-shaped dam 4 made of epoxy resin or the like is formed between the stitch 8 and the solder ball 3. The dam 4 plays a role of damming the sealing resin 6 so that the sealing resin 6 does not flow out to the solder ball 3 side after the resin sealing process.

For assembly, first, the LSI chip 2 is mounted on the package 1 using an adhesive such as silver paste. Next, a bonding wire 5 is applied to the LSI chip 2 and the stitch 8 by a bonding work. As the bonding wire, gold or aluminum wire having a diameter of 30 μm is generally used. Finally, resin sealing is performed so that the LSI chip 2, the bonding wire 5, and the stitch 8 are not exposed. For resin encapsulation, the encapsulating resin 6 is applied to the inside of the dam 4 and baked at 100 ° C. to 200 ° C. for 2 to 3 hours, so that the encapsulating resin 6 is liquefied and then cured. Therefore, the sealing surface after curing the sealing resin 6 becomes flat.

[0004]

In the conventional semiconductor package described above, the first problem is that the resin is applied when the amount of the resin applied increases due to the accuracy of the equipment and the change in the viscosity of the resin in the sealing process. Overflows from the sealing area surrounded by the dam, and the solder balls are covered with resin, resulting in a defective semiconductor device. The reason is that the area from the outside of the dam to the solder ball mounting portion is flat.

The second problem is that more precise control of the resin coating amount is required, especially when the sealing area is reduced as the size of the LSI chip is reduced. The reason for this is that the amount of change in the height of the sealing surface with respect to the amount of change in the amount of resin used for sealing becomes large, and even a slight change in the amount of resin applied changes the height of the sealing surface. Because they cross the dam.

[0006] Further, in the mold type encapsulation in which the die is used for encapsulation, it is necessary to prepare the die in accordance with the chip size and the pattern of the package.

Therefore, the object of the present invention is to simplify the control of the amount of resin applied in the sealing step, to shorten the time required for obtaining working conditions, and to increase the number of products produced per unit time. In addition, by expanding the margin of the amount of resin applied in the encapsulation process, the manufacturing conditions and the manufacturing jig can be simplified even if the semiconductor device is miniaturized and densified. The objective is to improve yield and reduce production costs.

For the resin sealing, the resin 6 is dropped inside the first dam 4a, and the resin is baked at a temperature of 150 ° C. for 2 hours to once liquefy and then cured. The resin 6 is usually dammed by the first dam 4a. However, when the sealing resin 6 is applied and the coating amount increases and exceeds the limit value, the sealing resin 6 exceeds the first dam. However, since the sealing resin 6 that has passed over the first dam is dammed by the second dam 4b, the resin 6 does not flow out to the solder ball 3 side.

[0009]

SUMMARY OF THE INVENTION The semiconductor package of the present invention is a package which is sealed with an epoxy resin, and is made of an excessive amount of resin on the outer periphery of the ring-shaped first dam used to dam the resin. It is characterized in that it has a ring-shaped second dam used for preventing the resin from flowing out to the solder ball side when the resin crosses the first dam. In addition, in a package sealed with an epoxy resin, a solder ball is provided on the outer periphery of a ring-shaped first dam used for damming the resin when the resin exceeds the first dam due to excessive resin. Has a ring-shaped second dam used to prevent resin from flowing out to the side,
Further, a semiconductor package having at least one row of ring-shaped dams on the outer side thereof. In addition, the second dam and one or more rows of dams arranged on the outside thereof are formed between the first dam and the solder ball row arranged in a grid pattern.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1A is a front view of a semiconductor package according to the technique of the present invention as seen from a surface having solder balls, and FIG. 1B is a front view of FIG.
3 is a cross-sectional view taken along the line AA ′ of FIG. The embodiment of the present invention uses the insulating material such as metal, organic or ceramic as the substrate, and has the recessed cavity 7 for mounting the LSI chip 2 in the central portion thereof. There is a stitch 8 around the cavity 7 which serves as an electrode on the package 1 side when electrically connected to. The solder balls 3 are arranged in a grid pattern on the outer ends of the package 1. The solder balls 3 are used as terminals for connecting the package 1 and the outside of a printed circuit board or the like. The stitch 8 is electrically connected to the solder ball 3 by a wiring (not shown) inside the package 1. Between the stitch 8 and the solder ball 3, there is a first dam 4a for blocking the sealing resin 6 in the sealing process, and a second dam 4b is provided on the outer periphery of the first dam 4a.

Next, the manufacturing process of the semiconductor package in the technique of the present invention will be described with reference to FIGS. 2 (a1) to 2 (b1). In the package, first, a recessed cavity 7 for mounting an LSI chip is formed in a central portion of a package substrate 11 made of a material such as metal or organic plastic by die processing or etching. The package substrate thickness is 1 mm to 3 mm, and the cavity depth is 0.5 mm to 1 mm. Alternatively, FIG. 2 (a2)-
As shown in (b2), a laminated substrate 21b made of an organic plastic or the like whose central portion is hollowed out is attached to a package substrate 21a made of a material such as metal or organic plastic with an adhesive or the like. Thus, the cavity 7 is formed. Package substrate 21a in this case
And the thickness of the laminated substrate 21b are 0.5 mm to 1 mm, respectively.
Is. Next, as shown in FIG. 2C, the cavity 7
A stitch 8 used when electrically connecting the LSI chip and the package 1 is formed around the. The formation method is
Generally, a conductive layer formed of copper plating or the like is patterned on the insulating layer by using a photolithography technique. Next, solder balls 3 made of a material such as eutectic solder are arranged on the outer periphery of the package in a grid pattern. The solder ball 3 usually has a diameter of 0.6 mm to 0.8 mm and a height of 0.5 mm to 0.
Use a 7 mm one. The solder balls 3 are attached by applying flux to the mounting surface of the solder balls 3, arranging it on the flux, and then performing reflow in the temperature range of 220 ° C. to 270 ° C. Finally, as shown in FIG. 2D, a first dam 4a is formed around the stitch 8 with an epoxy resin, and a second dam 4b is formed around the first dam 4a at a position of about 1 mm. Each dam is shown in Figure 2 (e)
As shown in, a linear epoxy resin is applied using the nozzle 9 and baked at a temperature of 120 ° C. to 170 ° C. to be cured. The width of each dam 4a, 4b is 0.5
The height is 0.2 mm to 0.3 mm at ˜1 mm. In addition, even if the first dam 4a and the second dam 4b are formed at the same time,
They may be formed separately.

Next, assembly of the semiconductor package according to the technique of the present invention will be described with reference to FIG. Figure 3 (a)
The assembly can be performed by a general method as shown in FIG. First, the LSI chip 2 is mounted in the cavity 7 with an adhesive such as silver paste. Next, as shown in FIG. 3B, the LSI chip 2 and the stitch 8 are electrically connected via a bonding wire 5 by a bonding operation. Finally, as shown in FIG. 3C, a resin sealing work is performed so as to completely cover the LSI chip 2, the bonding wire 5, and the stitch 8. Epoxy resin 6 is used as the resin, and is applied to the area surrounded by the first dam 4a, and then baked for 2 hours to 3 hours in the range of 100 ° C to 170 ° C. Since the sealing resin 6 is once liquefied and cured by the baking operation, the sealing surface after curing can be made flat.

Next, FIG. 4 is an enlarged view from the cavity 7 of the semiconductor package 1 to the second dam 4b in the technique of the present invention. First, as shown in FIG.
The chip 2 is mounted and bonded. Next, the sealing is performed by applying the sealing resin 6 on the inner side (closer to the cavity) of the first dam 4a and then performing a baking operation. By baking, the sealing resin 6 is once liquefied, and after the surface becomes flat, it is cured. At this time, if the application amount of the sealing resin 6 is proper, the sealing resin 6 is stopped inside the first dam 4a as shown in FIG. 4B. However, the viscosity of the sealing resin may change due to an increase in the ambient temperature of the equipment and the coating amount may increase even under the same working conditions. When the amount of increase exceeds the limit, the sealing resin 6 partially overflows beyond the first dam 4a (sealing resin excess portion 6a), however, FIG.
As shown in (c), the overflowing resin 6a is dammed by the second dam 4b.

For example, the sealing area is 26 mm square (676 square mm), the height of the dam is 0.3 mm, the first dam 4a and the second dam 4a.
When the distance from the dam 4b is 1 mm, the amount of resin that can be applied to the inside of the first dam 4a is about 250 cubic mm, and the amount of resin applied is about 50 cubic mm (about 20 cubic mm of the original applied amount).
%) Even if the amount is increased, the sealing resin 6 will not exceed the second dam 4b. That is, if the sealing resin excess 6a (application increase amount) is up to 50 cubic mm, the semiconductor device will not be defective.

Next, regarding the second embodiment of the present invention,
This will be described with reference to FIG. First, as shown in FIG. 5A, the material and the manufacturing method are the same as those in the first embodiment.
Is formed lower than the second dam 4b. For example, second
The height of the dam 4b is 0.3 mm, and the height of the first dam 4a is 0.2 mm, that is, 0.1 mm lower than that of the second dam 4b. Next, resin sealing is performed in the same manner as in the first embodiment. For resin sealing, the resin 6 is applied to the inside of the first dam and then baked. Incidentally, the sealing resin which is usually used has a low viscosity and a surface tension of about 0.1 mm. When this resin is used, the height of the sealing surface after sealing is about 0.3 mm when the sealing resin 6 is applied to the limit not exceeding the first dam 4a as shown in FIG. 5 (b). . Further, as shown in FIG. 5C, when the coating amount increases at the stage of coating the sealing resin 6, the sealing resin 6 exceeds the first dam 4a but is dammed by the second dam 4b.
The height of the sealing surface at this time is about 0.3 mm, which is the same as in the case of FIG. 5B. That is, the height of the sealing surface becomes constant by adjusting the coating amount of the sealing resin 6 from the amount exceeding the first dam 4a to the amount reaching the same height as the second dam 4b. FIG. 5D shows the correlation between the amount of the sealing resin applied when the semiconductor package is sealed with the resin according to the second embodiment of the present invention and the height of the sealing surface after the sealing with the resin. It is a schematic diagram. The dotted line in the graph represents the correlation when the conventional semiconductor package is used. The height of the sealing surface becomes constant at the portion of ΔU in the schematic view of FIG. 5 (d). The height of the first dam 4a is
If the height of the second dam 4b is designed to be the target height of the sealing surface with a value obtained by subtracting the surface tension of the resin 6 from the target height of the sealing surface, the ΔU portion in the schematic diagram will be described. Is constant at the target height of the sealing surface. For example, the surface tension of the sealing resin 6 is 0.1 mm, the height of the first dam 4a is 0.2 mm, and the height of the second dam 4b (target height of the sealing surface) is 0.3 mm. When the area (inside the first dam 4a) is 26 mm □, ΔU is about 50 cubic mm.

Next, a third embodiment of the present invention will be described with reference to FIG. The first dam 31a and the second dam 31b are configured by attaching an insulating tape instead of the epoxy resin. The tape is formed by laminating several insulating tapes each having a width of 0.5 mm and a thickness of 0.1 mm. The parts other than the dam are the same as those in the first and second embodiments.

Next, a fourth embodiment of the present invention will be described with reference to FIG. For example, the first dam 31a is an insulating tape and the second dam 4b is an epoxy resin. The parts other than the dam are the same as those in the first and second embodiments.

Next, a fifth embodiment of the present invention will be described with reference to FIG.
Will be described with reference to. By bonding a plurality of insulating tapes having different widths to each other, the dam is formed into an L-shape facing the cavity, and the corners of the dam are the first dam part 32a and the second dam part 32b from the bottom. . At the time of resin sealing, the corners of the first dam portion 32a are used to form the sealing surface by surface tension. Even if the sealing resin 6 exceeds the first dam portion,
Since the side wall having the second dam portion is dammed up, the sealing resin 6 does not flow out to the solder ball side. The parts other than the dam are the same as those in the first and second embodiments.
In addition, in the first to fifth embodiments, the effect is increased by providing a plurality of second dams.

[0019]

As described above, according to the first aspect of the present invention,
Even if the resin coating amount is increased during the resin sealing work, the semiconductor product is not defective. The reason is that the second dam is formed on the outside of the dam used for damming the usual sealing resin.

Second, at the time of sealing, the height of the sealing surface can be kept constant even if the resin coating amount fluctuates within a certain range, simplifying the management of the resin coating amount in the sealing process. However, there is an effect that it is possible to reduce the height variation of the sealing surface between the semiconductor products. The reason is that since the second dam is located outside the first dam that is normally used to dam the sealing resin, it is possible to control the height of the sealing surface using the surface tension of the resin at the first dam. This is because the resin that has crossed over the first dam is stopped by the second dam, so that the resin is prevented from flowing out to the solder ball side while keeping the height of the sealing surface constant.

[Brief description of drawings]

FIG. 1A is a surface view of a semiconductor package according to an embodiment of the present invention when viewed from a solder ball surface. (B) Figure 1
It is sectional drawing in the AA 'line of (a).

2 (a1) to (e) are views showing a manufacturing process of a semiconductor package in the technique of the present invention.

3 (a) to (c) are diagrams showing a process of assembling a semiconductor package according to the technique of the present invention.

4 (a) to (c) are diagrams showing a first embodiment of the present invention.

5A to 5C are diagrams showing a second embodiment of the present invention.

FIG. 6 is a diagram showing a third exemplary embodiment of the present invention.

FIG. 7 is a diagram showing a fourth exemplary embodiment of the present invention.

FIG. 8 is a diagram showing a fifth embodiment of the present invention.

FIG. 9A is a surface view of a semiconductor package according to a conventional technique as viewed from a solder ball surface. (B) It is sectional drawing in the AA 'line of FIG.6 (a).

[Explanation of symbols]

1 package 2 LSI chips 3 solder balls 4 dams (prior art) 4a 1st dam (composed of epoxy resin) 4b 2nd dam (composed of epoxy resin) 5 Bonding wire 6 Sealing resin 6a Encapsulation resin excess 7 cavities 8 stitches 9 nozzles 11 Package board (thick board) 21a Package substrate (thin substrate) 21b Organic laminated substrate 31a 1st dam (composed of insulating tape) 31b 2nd dam (composed of insulating tape) 32a First dam section 32b Second dam section

Claims (14)

[Claims] 1. In a package sealed with an epoxy resin, when the resin exceeds the first dam due to an excessive amount of resin on the outer periphery of a ring-shaped first dam used for damming the resin. A semiconductor package having a ring-shaped second dam used for preventing resin from flowing out to the solder ball side. 2. In a package sealed with an epoxy resin, when the resin exceeds the first dam due to excessive resin on the outer periphery of a ring-shaped first dam used for damming the resin. Has a ring-shaped second dam used to prevent the resin from flowing out to the solder ball side, and further has at least one row of ring-shaped dams on the outside thereof. Semiconductor package. 3. The semiconductor package according to claim 1, wherein the second dam is formed between the first dam and the solder ball row arranged in a grid pattern. 4. The semiconductor package according to claim 1, wherein the ring-shaped first dam and the ring-shaped second dam are made of an epoxy resin. 5. The semiconductor package according to claim 1, wherein the first dam and the second dam are formed by attaching an insulating tape. 6. The first dam and the second dam are formed of, for example, a first epoxy resin, and a second material made of a different material such as an insulating tape attached, and a construction method. The semiconductor package according to claim 1. 7. The first dam and the second dam are formed at the same height, respectively.
The semiconductor package described in 4, 5, and 6. 8. The first dam and the second dam are formed at different heights, respectively.
The semiconductor package described in 4, 5, and 6. 9. The second dam and one or more rows of dams arranged outside the second dam are formed between the first dam and the solder ball row arranged in a grid pattern. Item 2. The semiconductor package according to item 2. 10. The ring-shaped first dam, the ring-shaped second dam, and one or more rows of dams arranged on the outer side of the first dam are made of an epoxy resin. Semiconductor package. 11. The semiconductor package according to claim 2, wherein the first dam, the second dam, and one or more rows of dams arranged outside the first dam are formed by attaching an insulating tape. . 12. The first dam, the second dam, and one or more rows of dams arranged on the outside thereof are, for example, the first dam.
3. The semiconductor package according to claim 2, wherein is an epoxy resin, and the second or more are formed by different materials such as sticking an insulating tape and a construction method. 13. The first dam, the second dam, and one or more rows of dams arranged outside the first dam and the second dam are formed at the same height, respectively.
11. The semiconductor package according to 11, 12. 14. The first dam, the second dam, and one or more rows of dams arranged outside the first dam and the second dam are formed at different heights, respectively.
The semiconductor package described in 1 or 12.