JP2019050285A - 記憶装置 - Google Patents
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- 229910052814 silicon oxide Inorganic materials 0.000 description 16
- 238000003491 array Methods 0.000 description 14
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- 102100024853 Carnitine O-palmitoyltransferase 2, mitochondrial Human genes 0.000 description 9
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- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 101100512517 Trypanosoma brucei brucei MCA4 gene Proteins 0.000 description 6
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- 101100497208 Solanum lycopersicum CPT3 gene Proteins 0.000 description 5
- 101000859570 Homo sapiens Carnitine O-palmitoyltransferase 1, liver isoform Proteins 0.000 description 4
- 101000989606 Homo sapiens Cholinephosphotransferase 1 Proteins 0.000 description 4
- 101150009920 MCA2 gene Proteins 0.000 description 4
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 238000000605 extraction Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
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- 239000002344 surface layer Substances 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 101000578349 Homo sapiens Nucleolar MIF4G domain-containing protein 1 Proteins 0.000 description 3
- 101150073928 MCA3 gene Proteins 0.000 description 3
- 102100027969 Nucleolar MIF4G domain-containing protein 1 Human genes 0.000 description 3
- 101150043410 SHE2 gene Proteins 0.000 description 3
- 101100347614 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) MYO4 gene Proteins 0.000 description 3
- 101150099986 she-1 gene Proteins 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
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- 239000010703 silicon Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
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- 239000002994 raw material Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5642—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
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Abstract
Description
図1(a)および(b)は、第1実施形態に係る記憶装置1を示す模式断面図である。図1(a)に示すように、記憶装置1は、複数のメモリセルアレイMCA1〜MCA4をZ方向に積層した構造を有する。さらに、記憶装置1は、メモリセル領域MCRと、引き出し領域HURと、を含む。メモリセル領域MCRは、3次元配置されたメモリセルを含み、引き出し領域HURは、各メモリセルアレイの端部と、それらをZ方向に貫く複数のコンタクトプラグCPと、を含む。
図19(b)に示すように、レジストマスク37を用いて、絶縁膜33Tおよび35Tを選択的に除去し、段差STP4を形成する。
図30は、第2実施形態に係る記憶装置2を示す模式平面図である。本実施形態においても、記憶装置2は、複数のメモリセルアレイMCAをZ方向に積層した構造を有し、そのワード線WLは、メモリホールMHが設けられる第1領域WLP1と、端部WLEと、第1領域WLP1と端部WLEとを電気的に接続する第2領域WLP2と、を含む。第2領域WLP2は、第1領域WLP1と端部WLEとの間において、それらの外縁よりもY方向に後退した外縁を有する。これにより、第1領域WLP1と端部WLEとの間に凹部RPが設けられる。
図31(b)に示すように、絶縁膜13および15は交互にZ方向に積層される。絶縁膜13は、例えば、シリコン酸化膜であり、絶縁膜15は、例えば、シリコン窒化膜である。なお、図31(b)および後続する断面図では、便宜上、絶縁膜13および15の積層数を減らして記載している。
図33(b)に示すように、溝G1およびG2は、絶縁膜13Tと絶縁膜15Tを順に選択的に除去することにより形成される。溝G1およびG2の底面には、絶縁膜13Mが露出される。
図41(a)中に示す矢印は、絶縁膜15のエッチングの進行方向を示している。絶縁膜15のエッチングは、スリットST1の内壁および段差STP1、STP2およびSTP3に露出した部分から進行する。この例でも、段差STP1およびSTPからX方向に進むエッチングが絶縁膜21に到達した後、メモリセル領域MCRにおいて絶縁膜15が全て除去されるまでの時間を制御する。この例では、最上層の絶縁膜15Tのエッチングは、その他の絶縁膜15とは異なる進行を示す。
記憶装置2は、図31〜図49に示す工程を繰り返し、任意の数の積層体を積み重ねることにより形成される。ここで、各積層体は、図1(a)に示すメモリセルアレイMCAに該当する。
Claims (5)
- 第1方向に積層された複数の第1電極層と、
前記第1電極層を前記第1方向に貫いて延びる第1半導体ピラーと、
前記第1電極層から見て前記第1方向に位置し、前記第1方向に積層された複数の第2電極層と、
前記第2電極層を前記第1方向に貫いて延びる第2半導体ピラーと、
前記第1電極層と前記第2電極層との間に設けられ、前記第1半導体ピラーおよび前記第2半導体ピラーに電気的に接続された配線と、
前記第1電極層のうちの1つと、前記第2電極層のうちの1つと、に電気的に接続され、前記第2電極層のうちの1つを貫いて前記第1方向に延びる第1接続導体と、
を備えた記憶装置。 - 前記接続導体は、前記第1電極層の1つの端部に接続され、前記第2電極層の1つの端部を前記第1方向に貫く請求項1記載の記憶装置。
- 前記第1電極層のうちの別の1つと、前記第2電極層のうちの別の1つと、に電気的に接続された第2接続導体をさらに備え、
前記第2電極層のうちの1つは、前記第1半導体ピラーと交差する第1領域と、前記第1領域と前記端部とをつなぐ第2領域と、を含み、
前記第2電極層のうちの1つは、前記第1領域と前記端部との間において、前記第2領域を前記第1方向と交差する方向に後退させた凹部を有し、
前記第2接続導体は、前記第2電極層のうちの1つに接触することなく前記凹部を通り前記第1方向に延在する請求項1または2に記載の記憶装置。 - 前記第1接続導体は、前記第1電極層のうちの1つを貫く第1部分と、前記第2電極層を貫く第2部分とを含む請求項1〜3のいずれか1つに記載の記憶装置。
- 第1方向に積層された複数の第1電極層と、
前記第1電極層を前記第1方向に貫いて延びる第1半導体ピラーと、
前記第1方向に延在し、前記第1電極層のそれぞれに電気的に接続された接続導体と、
を備え、
前記第1電極層のそれぞれは、前記第1半導体ピラーと交差する第1領域と、前記接続導体と交差する端部と、前記第1領域と前記端部とをつなぐ第2領域と、を含み、
前記第1電極層のそれぞれは、前記第1領域と前記端部との間において、前記第2領域を前記第1方向と交差する方向に後退させた凹部を有する記憶装置。
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US15/919,250 US10381081B2 (en) | 2017-09-08 | 2018-03-13 | Three dimensional memory device with multiple stacked electrode layers |
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KR20210141561A (ko) * | 2020-03-13 | 2021-11-23 | 양쯔 메모리 테크놀로지스 씨오., 엘티디. | 3차원 메모리를 위한 접촉 구조들 |
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KR102344984B1 (ko) * | 2017-11-10 | 2021-12-29 | 삼성전자주식회사 | 수직형 반도체 소자 |
KR20210034749A (ko) | 2019-09-20 | 2021-03-31 | 삼성전자주식회사 | 반도체 메모리 소자 및 이의 제조 방법 |
CN113571467A (zh) * | 2020-03-13 | 2021-10-29 | 长江存储科技有限责任公司 | 用于三维存储器的接触结构 |
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JP2008258458A (ja) * | 2007-04-06 | 2008-10-23 | Toshiba Corp | 半導体記憶装置及びその製造方法 |
JP2011054758A (ja) * | 2009-09-02 | 2011-03-17 | Toshiba Corp | 半導体集積回路装置 |
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