JP2019024138A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device comprising an IGBT capable of reducing generation of a switching loss and a switching noise and of achieving excellent ON-voltage and short circuit resistance.SOLUTION: Provided is a semiconductor device 1 that includes: an FET structure 8 that is formed at a lateral side of an annular trench 10 formed on a semiconductor substrate 15, and that has an ntype emitter region 31 and an ntype drain region 17 opposed to each other in a depth direction of the annular trench 10 while interposing a p-type base region 28 therebetween; a p-type floating region 9 formed at an opposite side to the FET structure 8 across the annular trench 10; and a gate junction 19 and an emitter junction 20 electrically connected with the ntype emitter region 31, that are insulated and separated from each other in the annular trench 10. The gate junction 19 and the emitter junction 20 are opposed to the FET structure 8 and the p-type floating region 9 via an insulating film 18.SELECTED DRAWING: Figure 2A

Description

  The present invention relates to a semiconductor device including an IGBT (Insulated Gate Bipolar Transistor).

Conventionally, a trench type IGBT having a collector-emitter saturation voltage V _CE (sat) and a high short-circuit tolerance has a p-type floating region. The p-type floating region is generally formed by diffusing in the drift layer so as to be in contact with the trench gate. This drift layer is an epitaxial wafer or a pulling wafer having a resistance value comparable to that of the epitaxial wafer.

Satoru Machida, Takahide Sugiyama, Masayasu Ishiko, Satoshi Yasuda, Jun Saito, Kimimori Hirota, “Analysis of IGBT Switching Loss and Device Capacitance”, IEEJ Electronic Materials Study Group (EFM-09, 16-26, 28-) 29), p. 55-59 Watanabe, Hiroshi Mori, Atsuka Arai, Keisuke Ishibashi, Satoshi Toyoda, Tetsuo Oda, Taku Harada, Katsuaki Saito, “Low loss, low noise, high reliability 1.7kV trench IGBT with floating p-layer separated from gate” , Electrotechnical Society Electronic Device Research Material (EDD-11, 66-83), p. 67-71 Japanese Patent No. 4785334

However, the IGBT having a structure in which the p-type floating region and the trench gate are electrically connected has a problem that the switching loss increases because the junction region between the trench gate and the p-type floating region has a high stray capacitance. There is also a problem that switching noise occurs during the switching-on operation.
Further, it cannot be said that there is still a promising technique for improving such switching loss and switching noise problems without sacrificing various characteristics such as on-voltage and short-circuit tolerance of the semiconductor device.

  One embodiment of the present invention provides a semiconductor device including an IGBT that can reduce the generation of switching loss and switching noise and achieve an excellent on-voltage and short-circuit tolerance.

  One embodiment of the present invention includes a first conductivity type semiconductor layer having a front surface and a back surface, a second conductivity type collector region formed on a surface layer portion of the back surface of the semiconductor layer, an outer peripheral surface, and an inner peripheral surface And a plurality of annular trenches formed on the surface of the semiconductor layer, each including a bottom surface connecting the outer peripheral surface and the inner peripheral surface and spaced apart from each other in a manner in which the outer peripheral surfaces face each other. An insulating film formed on the inner surface of each trench; a gate junction embedded with the insulating film on the outer peripheral surface side of each trench; and the gate junction on the inner peripheral surface side of each trench An emitter junction embedded with the insulating film being spaced apart from a portion; a central insulating film interposed between the gate junction and the emitter junction in each trench; and the surface of the semiconductor layer The surface of the semiconductor layer is formed in a region between the outer peripheral surfaces of the plurality of trenches adjacent to each other in the surface layer portion, and the central portion of the trench or the central portion of the trench with respect to the thickness direction of the semiconductor layer A second conductivity type base region having a bottom portion located on the side; a first conductivity type emitter region formed in a surface layer portion of the base region; and a surface layer portion of the surface of the semiconductor layer in each of the trenches. A second portion formed in an electrically floating state in a region surrounded by an inner peripheral surface and having a bottom portion located on the back surface side of the semiconductor layer with respect to the bottom surface of the trench in the thickness direction of the semiconductor layer; A conductive floating region, an interlayer insulating film that selectively covers the surface of the semiconductor layer, and an interlayer insulating film formed on the interlayer insulating film and electrically connected to the gate junction. And a surface gate electrode, wherein formed on the interlayer insulating film, the emitter junction and including, and electrically connected to the surface emitter electrode on the emitter region, to provide a semiconductor device.

According to this configuration, an FET structure including the semiconductor layer, the base region, and the emitter region is formed in a region between the first side surfaces of the plurality of adjacent trenches in the surface layer portion on the surface of the semiconductor layer. In addition, a floating region is formed in a region between the second side surfaces of the plurality of adjacent trenches in the surface layer portion on the surface of the semiconductor layer.
According to this configuration, the capacitance component due to the contact between the trench and the floating region can be changed to the capacitance component (capacitance between the collector-emitter junction) in the junction region between the emitter junction and the floating region. As a result, the gate junction is not affected by the junction with the floating region. Therefore, switching loss can be reduced as compared with the conventional semiconductor device in which the floating region and the trench gate are joined. On the other hand, if the semiconductor layer facing the gate junction is grounded together with the collector region, the capacitance change between the gate junction and the semiconductor layer can be kept stable during the switching operation. As a result, generation of switching noise can be suppressed.

  On the other hand, the inventors of the present application have formed a semiconductor device including an IGBT having a structure in which a plurality of trench emitters are formed between adjacent trench gates and the trench emitters and the floating region are electrically joined to each other (hereinafter referred to as “reference example”). "Semiconductor device according to the present invention"). In this structure, since there is no junction region between the trench gate and the floating region, the above-described problems of switching loss and switching noise can be improved. However, in the case of the semiconductor device according to the reference example, an FET structure is formed in each region between the trench gate and the trench emitter. Therefore, the trench gate and the trench emitter face each other through the FET structure. Therefore, the carrier accumulation effect by sandwiching the FET structure between the trench gates is reduced, and accordingly, the carrier density in the semiconductor layer is also reduced. As a result, the drift resistance in the semiconductor layer increases, and the on-voltage tends to increase.

  On the other hand, according to the configuration of the present invention, the gate junction can be opposed to each other via the insulating film and the FET structure, so that the carrier accumulation effect by the gate junction can be enhanced. Thereby, since the carrier density in the semiconductor layer increases, the drift resistance in the semiconductor layer can be reduced. Thereby, the on-voltage of the semiconductor device can be reduced.

  Furthermore, according to the configuration of the present invention, unlike the semiconductor device according to the reference example, since the gate junction and the emitter junction are formed in the same trench, it is necessary to form the trench gate and the trench emitter. Absent. Therefore, the number of FET structures to be formed is small. That is, the number of contact openings for connecting the FET structure is small. Thereby, since a contact opening ratio can be made small, the fall of the short circuit tolerance of a semiconductor device can be suppressed effectively.

FIG. 1 is a schematic plan view of a semiconductor device according to the first embodiment of the present invention. 2A is a schematic cross-sectional view of the semiconductor device shown in FIG. 2B is a schematic cross-sectional view showing one end portion of the trench of the semiconductor device shown in FIG. FIG. 3 is a schematic cross-sectional view of a semiconductor device according to a reference example. FIG. 4 is a graph for comparing the steady losses of the semiconductor device shown in FIG. 1 and the semiconductor device according to the reference example. FIG. 5 is a graph for comparing the carrier densities of the semiconductor device shown in FIG. 1 and the semiconductor device according to the reference example. 6A is a cross-sectional view for explaining an example of a manufacturing process of the semiconductor device of FIG. FIG. 6B is a diagram showing the next manufacturing step after FIG. 6A. FIG. 6C is a view showing the next manufacturing step after FIG. 6B. FIG. 6D is a diagram showing the next manufacturing step after FIG. 6C. FIG. 6E is a diagram showing the next manufacturing step after FIG. 6D. FIG. 6F is a view showing the next manufacturing step after FIG. 6E. FIG. 6G is a diagram showing the next manufacturing step after FIG. 6F. FIG. 6H is a view showing the next manufacturing step after FIG. 6G. FIG. 6I is a view showing the next manufacturing step after FIG. 6H. FIG. 6J is a view showing the next manufacturing step after FIG. 6I. FIG. 6K is a view showing the next manufacturing step after FIG. 6J. FIG. 7 is a schematic cross-sectional view of a semiconductor device according to the second embodiment of the present invention. FIG. 8 is a schematic cross-sectional view of a semiconductor device according to the third embodiment of the present invention. FIG. 9 is a schematic cross-sectional view of a semiconductor device according to the fourth embodiment of the present invention. FIG. 10 is a schematic plan view of the semiconductor device according to the first reference example. FIG. 11 is a schematic plan view for explaining the routing wiring of the semiconductor device according to the first reference example. FIG. 12 is an enlarged plan view of the routing wiring of the semiconductor device shown in FIG. FIG. 13A is a cross-sectional view taken along section line XIIIA-XIIIA shown in FIG. FIG. 13B is an electric circuit diagram for explaining the electrical structure of the semiconductor device shown in FIG. 10. FIG. 14A is a graph showing switching characteristics of the semiconductor device shown in FIG. 14B is a graph showing switching characteristics of the semiconductor device shown in FIG. 14C is a graph showing switching characteristics of the semiconductor device shown in FIG. FIG. 15 is a schematic plan view of a semiconductor device according to a second reference example. FIG. 16 is a schematic plan view for explaining the routing wiring of the semiconductor device according to the second reference example. FIG. 17 is a schematic cross-sectional view showing a modification of the semiconductor device according to the first embodiment. FIG. 18 is a circuit diagram for explaining an inverter circuit to which the semiconductor device according to the first to fourth embodiments is applied. FIG. 19 is a schematic cross-sectional view showing a modification of the semiconductor device according to the first and second reference examples. FIG. 20 is a circuit diagram for explaining an inverter circuit to which the semiconductor device according to the first and second reference examples is applied.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic plan view of a semiconductor device 1 according to the first embodiment of the present invention.
The semiconductor device 1 is formed in a square shape (hereinafter, simply referred to as “plan view”) as viewed from the normal direction of the surface thereof, and has a gate finger 2 and a gate pad at the periphery of the surface. 3 are formed. The gate finger 2 is formed in a substantially square ring shape along the peripheral edge of the semiconductor device 1 in plan view. An active region 4 is formed in a region surrounded by the gate fingers 2.

  A gate pad 3 having a substantially quadrangular shape in plan view is provided at the center in the longitudinal direction of the region along one side of the gate finger 2. The gate pad 3 is formed so as to be continuous with the gate finger 2. A bonding wire (not shown) is connected to the gate pad 3, whereby electric power is supplied to the semiconductor device 1. The gate finger 2 and the gate pad 3 are made of, for example, a metal material containing Al as a main component. In this embodiment, an example in which the gate pad 3 is provided in the central portion in the longitudinal direction of the region along one side of the semiconductor device 1 will be described. However, the gate pad 3 is formed at one corner of the gate finger 2. May be.

  In a region surrounded by the gate finger 2 and the gate pad 3, a removal region 5 for preventing the gate finger 2 and the gate pad 3 from contacting the emitter electrode 6 is formed. The removal region 5 is formed in a concave ring shape in plan view so as to follow the gate finger 2 and the gate pad 3. The emitter electrode 6 is formed in a concave shape in which a part thereof is selectively recessed in plan view so as to cover the region surrounded by the removal region 5. The gate pad 3 is disposed in a recessed area of the emitter electrode 6. The emitter electrode 6 is made of, for example, the same metal material as the gate finger 2 and the gate pad 3.

  In the active region 4, a plurality of FET structures 8 that form unit cells 7 of IGBTs (Insulated Gate Bipolar Transistors) are formed in stripes. A region having a constant width is provided between the plurality of FET structures 8, and one annular trench 10 is formed in each region. As a result, the FET structure 8 and the annular trench 10 are alternately formed in the active region 4.

The annular trench 10 is formed in a closed curve structure formed in a rectangular annular shape that is long along the stripe direction. A p-type floating region 9 (a region indicated by a broken line in FIG. 1) is formed in the inner region of the annular trench 10.
The shape of the annular trench 10 is not limited to a rectangular shape in plan view, and may be any shape as long as it is formed in an annular shape. For example, an annular trench 10 having an elliptical shape in plan view may be formed.

A gate contact trench 11 and an emitter contact trench 12 are respectively formed at both ends in the longitudinal direction of the annular trench 10. The gate contact trench 11 and the emitter contact trench 12 are drawn outward and inward from each end of the annular trench 10 in opposite directions.
Each of the gate contact trench 11 and the emitter contact trench 12 is formed in an arch shape that is continuous with the annular trench 10 in a plan view. More specifically, the gate contact trench 11 and the emitter contact trench 12 are both arched over the short side of the annular trench 10 (in this embodiment, the pair of pillars facing each other and the pair of pillars It is formed in the shape of a square arch including a beam portion connecting the column portions. The gate finger 2 is disposed so as to cross the gate contact trench 11 formed in each annular trench 10 (specifically, covering the beam portion of the gate contact trench 11).

  Next, a cross-sectional view of the semiconductor device 1 will be described with reference to FIGS. 2A and 2B. 2A is a schematic cross-sectional view of the semiconductor device 1 shown in FIG. 2B is a schematic cross-sectional view showing one end of the annular trench 10 of the semiconductor device 1 shown in FIG. FIG. 2A is a cross-sectional view when the semiconductor device 1 is cut in a direction perpendicular to the stripe direction of the annular trench 10. FIG. 2B is a cross-sectional view of the semiconductor device 1 cut in a direction crossing the short side of the annular trench 10, the gate contact trench 11 and the emitter contact trench 12.

As shown in FIGS. 2A and 2B, the semiconductor device 1 includes a semiconductor substrate 15 as an example of the semiconductor layer of the present invention. The semiconductor substrate 15 is, for example, an n ⁻ type silicon substrate, and has a structure in which a p ⁺ type collector region 16 and an n ⁻ type drain region 17 are formed in this order from the back side. The p ⁺ type collector region 16 is exposed on the entire back surface of the semiconductor substrate 15, and the n ⁻ type drain region 17 is exposed on the surface of the semiconductor substrate 15.

The dopant concentration of the p ⁺ -type collector region 16 is, for example, 1 × 10 ¹⁵ cm ⁻³ to 2 × 10 ¹⁹ cm ⁻³ . As the p-type dopant, for example, B (boron), Al (aluminum), or the like can be used (hereinafter the same). On the other hand, the dopant concentration of the n ⁻ -type drain region 17 is, for example, 1 × 10 ¹⁵ cm ^{−3 to} 5 × 10 ¹⁷ cm ⁻³ . In addition, as the n-type dopant, for example, N (nitrogen), P (phosphorus), As (arsenic), or the like can be used (hereinafter the same).

  An annular trench 10 is formed in the semiconductor substrate 15 by digging the surface of the semiconductor substrate 15 in the thickness direction. The annular trench 10 is formed with a constant width. The side surface of the annular trench 10 is formed substantially perpendicular to the surface of the semiconductor substrate 15. The bottom of the annular trench 10 is formed to be rounded from the side surface of the annular trench 10. A p-type floating region 9 is formed in an inner region partitioned by the annular trench 10.

The p-type floating region 9 is a semiconductor region in which an electrically floating state is maintained. In this embodiment, the p-type floating region 9 is formed so as to wrap around outwardly below the annular trench 10, and its bottom is located deeper than the bottom of the annular trench 10. Specifically, the outer peripheral edge at the bottom of the p-type floating region 9 is located below the central insulating film 21 described later. As a result, the p-type floating region 9 is formed below the emitter junction 20 described later, but is not formed below the gate junction 19. The dopant concentration of the p-type floating region 9 is, for example, 5 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ .

In the region between the adjacent annular trenches 10 (outer region of the annular trench 10), the n ⁺ -type emitter region 31 and the n ⁻ -type that are opposed to each other with the p-type base region 28 in the depth direction of the annular trench 10. An FET structure 8 (unit cell 7) including the drain region 17 is formed.
The p-type base region 28 is shared by one annular trench 10 and the other annular trench 10 that are adjacent to each other. In this embodiment, the interface between the p-type base region 28 and the n ⁻ -type drain region 17 is set at the center in the depth direction of the annular trench 10 or above the center. Are diffused and formed relatively shallow in the semiconductor substrate 15. The dopant concentration of the p-type base region 28 is, for example, 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ .

In the p-type base region 28, a contact trench 29 dug from the surface of the semiconductor substrate 15 is formed. The contact trench 29 is formed with a constant width along the longitudinal direction of the annular trench 10. A p ⁺ -type base contact region 30 is formed at the bottom of the contact trench 29. The dopant concentration of the p ⁺ type base contact region 30 is, for example, 5 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ .

On the surface of the p-type base region 28, an n ⁺ -type emitter region 31 is formed between the contact trench 29 and each annular trench 10. One n ⁺ -type emitter region 31 is provided on each side of the contact trench 29, and each n ⁺ -type emitter region 31 is exposed on the side surface of the contact trench 29. The dopant concentration of the n ⁺ -type emitter region 31 is 1 × 10 ¹⁹ cm ^{−3 to} 5 × 10 ²⁰ cm ⁻³ .

  As shown in FIGS. 2A and 2B, an insulating film 18 made of, for example, a silicon oxide film is formed on the surface of the semiconductor substrate 15 and the inner surface (side surface and bottom) of each annular trench 10. In the annular trench 10, a gate junction 19 and an emitter junction 20 are formed inside the insulating film 18. The gate junction 19 and the emitter junction 20 are formed in the annular trench 10 with a space therebetween and are insulated from each other. More specifically, the gate junction 19 and the emitter junction 20 are formed in a film shape along the inner side surface and the outer side surface of the annular trench 10 in the cross sections shown in FIGS. 2A and 2B, respectively. As a result, a space defined by the rear surfaces of the gate junction 19 and the emitter junction 20 (opposite surfaces in contact with the annular trench 10) is formed in the center of the annular trench 10 in the width direction. Then, the space is completely backfilled with the central insulating film 21 up to the opening end of the annular trench 10, whereby the gate junction 19 and the emitter junction 20 are insulated and separated from each other.

The gate junction 19 is formed in a substantially square ring shape in plan view so as to surround the emitter junction 20. That is, the gate junction 19 is formed on the outer region side of the annular trench 10 and is joined to the FET structure 8 via the insulating film 18. The gate junction 19 is made of an electrode material such as polysilicon, for example.
The emitter junction 20 is formed in a substantially square ring shape in plan view on the inner region side of the annular trench 10. That is, the emitter junction 20 is joined to the p-type floating region 9 via the insulating film 18. The emitter junction 20 is made of the same material as the gate junction 19.

As shown in FIG. 2B, a gate contact trench 11 and an emitter contact trench 12 are formed at one end in the longitudinal direction of the annular trench 10 with a width W ₂ narrower than the width W ₁ of the annular trench 10. . The width W ₁ of the annular trench 10 is, for example, 1.5 μm to 3.0 μm, whereas the width W ₂ of the gate contact trench 11 and the emitter contact trench 12 is, for example, 0.7 μm to 1.2 μm. is there. Note that the gate contact trench 11 and the emitter contact trench 12 may be formed with different widths within this numerical range.

  An insulating film 18 is formed on the inner surfaces of the contact trenches 11 and 12 in the same manner as the annular trench 10 described above. A buried gate electrode 24 is formed in the gate contact trench 11 via an insulating film 18. The buried gate electrode 24 is formed so as to be integrated with the gate junction portion 19 formed in the annular trench 10. On the other hand, a buried emitter electrode 25 is formed in the emitter contact trench 12 via an insulating film 18. The buried emitter electrode 25 is formed so as to be integrated with the emitter junction 20 formed in the annular trench 10.

  Since the contact trenches 11 and 12 are completely backfilled by the buried electrodes 24 and 25, respectively, the area of the polysilicon (electrode material) when the contact trenches 11 and 12 are viewed from above in the depth direction. Is at least equal to the diameter (width) of each contact trench 11, 12. As a result, it is possible to easily make contact with the embedded electrodes 24 and 25.

An interlayer film 34 is laminated on the surface of the semiconductor substrate 15 as shown in FIGS. 2A and 2B. In the interlayer film 34, a contact hole 35 that is integrally connected to the contact trench 29 is formed. 2B, an emitter contact hole 36 for selectively exposing the buried emitter electrode 25 and a gate contact hole 37 for selectively exposing the buried gate electrode 24 are formed in the interlayer film 34. Has been. The interlayer film 34 is made of an insulating material such as tetraethyl orthosilicate (TEOS), boron phosphorus silicate glass (BPSG), silicon oxide (SiO ₂ ), or the like.

On the interlayer film 34, an emitter electrode 6, a gate finger 2, and a gate pad 3 (see FIG. 1) are formed.
The emitter electrode 6 enters the contact trench 29 through the contact hole 35, and is connected to the n ⁺ -type emitter region 31 on the side surface of the contact trench 29. The emitter electrode 6 is connected to the p-type base region 28 via the p ⁺ -type base contact region 30 at the bottom of the contact trench 29.

Further, the emitter electrode 6 enters the emitter contact hole 36 and is connected to the buried emitter electrode 25. As a result, the power from the emitter electrode 6 is supplied to the emitter junction 20 via the buried emitter electrode 25.
On the other hand, the gate finger 2 enters the gate contact hole 37 and is connected to the buried gate electrode 24. As a result, power from the gate finger 2 (gate pad 3) is supplied to the gate junction 19 through the buried gate electrode 24.

  As described above, according to the semiconductor device 1, the p-type floating region 9 is disposed in the inner region of the annular trench 10 as shown in FIG. 2A. Emitter junctions 20 formed on the inner region side of the trench 10 face each other. In other words, the gate junction 19 formed on the outer region side of the annular trench 10 is separated from the p-type floating region 9 via the emitter junction 20 and the central insulating film 21. Therefore, the capacitance component due to the contact between the annular trench 10 and the p-type floating region 9 can be the capacitance between the collector-emitter junction. On the other hand, since the gate junction 19 is not in contact with the p-type floating region 9, it is possible to prevent the gate junction 19 from being affected by capacitance due to contact with the p-type floating region 9. As a result, switching loss can be effectively reduced.

In addition, the n ⁻ type drain region 17 with the gate junction 19 facing through the insulating film 18 is grounded together with the p ⁺ type collector region 16. For this reason, the capacitance change between the gate junction 19 and the n ⁻ -type drain region 17 is stabilized during the switching operation, so that noise hardly occurs. As a result, the generation of noise during the switching operation can be reduced.
Further, when the characteristics of the semiconductor device 1 and the characteristics of the semiconductor device 41 according to the reference example shown in FIG. 3 were examined by simulation, the graph shown in FIG. 4 and the graph shown in FIG. 5 were obtained. Hereinafter, after describing the configuration of the semiconductor device 41 according to the reference example of FIG. 3, the characteristics of the semiconductor device 1 will be described with reference to FIGS. 3 to 5.

FIG. 3 is a schematic cross-sectional view of a semiconductor device 41 according to a reference example. 3, parts corresponding to those shown in FIG. 2A described above are denoted by the same reference numerals, and description thereof is omitted.
A semiconductor device 41 according to the reference example is a semiconductor device including an IGBT having a structure in which a plurality of trench emitters 43 are formed between adjacent trench gates 42 and the trench emitters 43 and the p-type floating region 9 are joined. is there. FIG. 3 shows an example in which two trench emitters 43 are formed between adjacent trench gates 42.

  The trench gate 42 includes a gate electrode 45 embedded in the trench 44 through the insulating film 18, and the trench emitter 43 includes an emitter electrode 46 embedded in the trench 44 through the insulating film 18. An FET structure 8 is formed in each region between the trench gate 42 and the trench emitter 43. That is, in the semiconductor device 41 according to the reference example, there is no junction region between the trench gate 42 and the p-type floating region 9, and the contact trench 29 and the contact hole 35 correspond to the region where each FET structure 8 is formed. And are formed.

FIG. 4 is a graph for comparing the steady loss of the semiconductor device 1 shown in FIG. 1 and the semiconductor device 41 according to the reference example. FIG. 5 is a graph for comparing the carrier densities of the semiconductor device 1 shown in FIG. 1 and the semiconductor device 41 according to the reference example.
The graph of FIG. 4 shows the relationship between the collector current I _C (A) and the collector-emitter voltage V _CE (V), and the graph of FIG. 5 shows the carrier density (1 / cm ⁻³ ) and the semiconductor substrate 15. It shows the relationship with the position (μm) from the surface. 4 and FIG. 5, the characteristic of the semiconductor device 1 is indicated by a solid line, and the characteristic of the semiconductor device 41 according to the reference example is indicated by a broken line.

Referring to FIG. 4, the collector current I _C of the semiconductor device 41 according to the reference example has a gentle region from the rising edge to the saturation region, and is in a relatively high collector-emitter voltage V _CE state. It can be confirmed that the saturation region has been reached.
On the other hand, the collector current I _C of the semiconductor device 1 has a steep region from the rising edge to the saturation region, and reaches the saturation region with a relatively low collector-emitter voltage V _CE. Can be confirmed.

Further, it can be confirmed that the ON voltage of the semiconductor device 1 is lower than the ON voltage of the semiconductor device 41 according to the reference example. Therefore, it can be said that the steady loss of the semiconductor device 1 is lower than the steady loss of the semiconductor device 41 according to the reference example. The on-state voltage is defined by a collector-emitter voltage V _CE necessary for flowing a rated current in a state where a voltage necessary for the on-state is applied between the gate and the emitter (a state where V _GE is applied). Is done.

Next, referring to FIG. 5, when the carrier density of the semiconductor device 1 is compared with the carrier density of the semiconductor device 41 according to the reference example, the semiconductor device 1 covers the entire area from the front surface to the back surface of the semiconductor substrate 15. It can be seen that the carrier density of the semiconductor device 41 according to the reference example is higher than the carrier density.
According to the configuration of the semiconductor device 41 according to the reference example, as shown in FIG. 3, since there is no junction region between the trench gate 42 and the p-type floating region 9, the gate junction 19 has a capacitance between the collector and the gate junction. The problem of switching loss and switching noise can be improved. However, in such a structure, the FET structure 8 is sandwiched between the trench gate 42 and the trench emitter 43 and is not sandwiched between the adjacent trench gates 42. Therefore, the carrier accumulation effect by the trench gate 42 is reduced, and accordingly, as shown in FIG. 5, the carrier density in the semiconductor substrate 15 is reduced, so that the drift resistance in the n ⁻ -type drain region 17 is increased. As a result, as shown in FIG. 4, the on-voltage of the IGBT becomes relatively high.

On the other hand, according to the configuration of the semiconductor device 1, as shown in FIG. 2A, the FET structure 8 is sandwiched between the adjacent gate junctions 19, so that the carrier accumulation effect by the gate junctions 19 can be enhanced. it can. As a result, as shown in FIG. 5, the carrier density in the semiconductor substrate 15 increases, so that the drift resistance in the n ⁻ -type drain region 17 can be reduced. As a result, the on-voltage of the IGBT can be reduced as shown in FIG.

Further, although not shown in the drawings, the simulation of how much switching noise is generated for each of the structures of the semiconductor device 1 and the semiconductor device 41 according to the reference example reveals that the noise of the structure of the semiconductor device 1 is related to the semiconductor device according to the reference example. It was confirmed that it was significantly smaller than the 41 structure.
Furthermore, according to the configuration of the semiconductor device 1, unlike the semiconductor device 41 according to the reference example, the gate junction 19 and the emitter junction 20 are provided in the same annular trench 10. There is no need to form the emitter 43. Therefore, the number of FET structures 8 to be formed is small. That is, the number of contact trenches 29 (contact holes 35) for connecting the FET structure 8 can be reduced. Thereby, since a contact opening ratio can be made small, it can suppress effectively that the short circuit tolerance of IGBT falls.

Next, a manufacturing process of the semiconductor device 1 will be described with reference to FIGS. 6A to 6K. 6A to 6K are cross-sectional views for explaining an example of a manufacturing process of the semiconductor device 1 of FIG. 6A to 6K correspond to FIG. 2A, respectively.
In order to manufacture the semiconductor device 1, first, as shown in FIG. 6A, a semiconductor substrate 15 is prepared in a state where the p ⁺ -type collector region 16 is not formed on the back surface side. Next, an ion implantation mask 50 having an opening selectively in a region where the p-type floating region 9 is to be formed is formed on the semiconductor substrate 15. Then, a p-type dopant is implanted into the semiconductor substrate 15 through the ion implantation mask 50. Thereby, an ion implantation region 56 is formed. After the ion implantation region 56 is formed, the ion implantation mask 50 is removed.

  Next, as shown in FIG. 6B, a hard mask 51 having an opening selectively in a region where an annular trench 10, a gate contact trench 11 and an emitter contact trench 12 (see FIG. 2B) are to be formed is a semiconductor. It is formed on the substrate 15. Then, the semiconductor substrate 15 is etched through the hard mask 51, and the trenches 10, 11, and 12 are formed simultaneously. After forming the trenches 10, 11, and 12, the hard mask 51 is removed.

Next, as shown in FIG. 6C, the surface of the semiconductor substrate 15 is subjected to thermal oxidation treatment. As a result, a sacrificial oxide film 57 made of a silicon oxide film is formed on the surface of the semiconductor substrate 15 including the inner surfaces (bottom surface and side surfaces) of the trenches 10, 11, 12.
Next, as shown in FIG. 6D, the semiconductor substrate 15 covered with the sacrificial oxide film 57 is annealed to diffuse the p-type dopant in the ion implantation region 56 (drive-in). This annealing process is performed under the condition that the p-type dopant goes under the annular trench 10. At this time, since the sacrificial oxide film 57 is formed on the inner surface of the annular trench 10 prior to the drive-in process, the escape of ions from the inner surface can be prevented. As a result, the p-type dopant can be efficiently diffused, and as a result, the p-type floating region 9 that wraps around below the annular trench 10 is formed.

Next, as shown in FIG. 6E, after the sacrificial oxide film 57 is peeled off, the surface of the semiconductor substrate 15 is subjected to a thermal oxidation process, whereby the insulating film 18 is formed. Next, polysilicon is deposited on the surface of the semiconductor substrate 15 by, for example, a CVD (Chemical Vapor Deposition) method to form a polysilicon deposition layer 52. At this time, the width W _{2 of} the gate contact trench 11 and the emitter contact trench 12 is narrower than the width W ₁ of the annular trench 10 (W ₂ <W ₁ see FIG. 2). Therefore, the annular trench 10 having a width W _1, as shown in FIG. 6E, while the polysilicon deposition layer 52 is formed along the shape of its inner surface, each contact trench 11 having a width W ₂ is The polysilicon deposited layers 52 deposited on one and the other side surfaces are integrated inside the contact trenches 11 and 12. 2B, the contact trenches 11 and 12 can be completely backfilled with the polysilicon deposition layer 52, and the buried gate electrode 24 and the buried emitter electrode 25 buried in the contact trenches 11 and 12 can be obtained. Can be obtained. Next, the surface of the polysilicon deposition layer 52 is oxidized to form a thin polysilicon oxide film 53.

  Next, as shown in FIG. 6F, the surface of the semiconductor substrate 15 is left so as to leave the polysilicon deposition layer 52 formed on the side surface of the annular trench 10 by anisotropic etching such as RIE (Reactive Ion Etching). And the polysilicon deposited layer 52 formed on the bottom of the annular trench 10 are selectively removed. Thereby, the gate junction 19 and the emitter junction 20 are formed simultaneously.

Next, as shown in FIG. 6G, SiO ₂ is formed into the annular trench 10 (more specifically, the gate junction 19 and the emitter junction by, for example, HDP-CVD (High Density Plasma CVD) method). It is deposited on the surface of the semiconductor substrate 15 so as to backfill the region between 20). Thereby, the SiO ₂ film 54 is formed.
Next, as shown in FIG. 6H, the surface of the SiO ₂ film 54 is etched back by, for example, dry etching or the like so as to be substantially flush with the surface of the semiconductor substrate 15. Thereby, the central insulating film 21 interposed between the gate junction 19 and the emitter junction 20 is formed.

Next, as shown in FIG. 6I, an ion implantation mask 55 having an opening selectively in a region where the p-type base region 28 and the n ⁺ -type emitter region 31 are to be formed is formed. Then, a p-type dopant and an n-type dopant are selectively implanted into the semiconductor substrate 15 through the ion implantation mask 55. Thereby, the FET structure 8 including the p-type base region 28 and the n ⁺ -type emitter region 31 is formed. After the p-type base region 28 and the n ⁺ -type emitter region 31 are formed, the ion implantation mask 55 is removed.

Next, as shown in FIG. 6J, TEOS is deposited on the semiconductor substrate 15 by an LP-CVD (Low Pressure CVD) method or the like, for example, and an interlayer film 34 is formed. Next, a hard mask (not shown) having an opening selectively in a region where the contact hole 35 and the emitter contact hole 36 and the gate contact hole 37 (see FIG. 2B) are to be formed is formed on the interlayer film 34. It is formed. Then, the contact holes 35, 36, and 37 are formed by etching the interlayer film 34 through the hard mask. Simultaneously with the formation of the contact holes 35, 36, and 37, a contact trench 29 that is dug from the surface of the semiconductor substrate 15 is formed in the p-type base region 28. After the contact trench 29 is formed, the hard mask is removed. Next, p-type dopant is implanted into the p-type base region 28 through the contact trench 29 to form the p ⁺ -type base contact region 30.

Next, as shown in FIG. 6K, materials for the emitter electrode 6 and the gate finger 2 (gate pad 3) are deposited on the interlayer film 34. Next, the emitter electrode 6 and the gate finger 2 (gate pad 3) are simultaneously formed by patterning the material. Next, ap type dopant is selectively implanted into the back surface of the semiconductor substrate 15 to form ap ⁺ type collector region 16. Thereby, the semiconductor substrate 15 has a structure in which the p ⁺ -type collector region 16 and the n ⁻ -type drain region 17 are formed in this order from the back surface side. The semiconductor device 1 is manufactured through the above steps.

  FIG. 7 is a schematic cross-sectional view of a semiconductor device 61 according to the second embodiment of the present invention. The semiconductor device 61 according to the second embodiment is different from the semiconductor device 1 according to the first embodiment described above in that a p-type floating region 62 formed relatively shallowly is formed instead of the p-type floating region 9. And a plurality of emitter trenches 63 are formed in a region surrounded by the annular trench 10. Other configurations are the same as those of the semiconductor device 1 according to the first embodiment described above. 7, parts corresponding to those shown in FIG. 2A described above are denoted by the same reference numerals, and description thereof is omitted.

  In this embodiment, the p-type floating region 62 is formed with the same depth as the p-type base region 28. A plurality of emitter trenches 63 as second trenches of the present invention are formed in a region surrounded by the annular trench 10 so as to penetrate the p-type floating region 62. In this embodiment, an example in which two emitter trenches 63 are formed in a region surrounded by the annular trench 10 is shown, but two or more emitter trenches 63 are formed. Also good. Further, a configuration in which one emitter trench 63 is formed in a region surrounded by the annular trench 10 may be adopted.

The emitter trench 63 is formed so as to be continuous with the annular trench 10. More specifically, the emitter trench 63 is formed in a stripe shape in plan view in the longitudinal direction of the annular trench 10 in a region surrounded by the annular trench 10, and continues to the annular trench 10 at each short side of the annular trench 10. Yes. The emitter trench 63 is formed in the same cross-sectional shape as the annular trench 10. That is, the width W ₃ of the emitter trench 63 is the same as the width W ₁ of the annular trench 10. The emitter trench 63 is formed with the same depth as the annular trench 10.

  In the emitter trench 63, a pair of second emitter junctions 64 are formed in a stripe shape in plan view via the insulating film 18. The pair of second emitter junctions 64 is formed in the same configuration as the gate junction 19 and the second emitter junction 20 in the first embodiment described above. That is, the pair of second emitter junctions 64 are formed in the emitter trench 63 with a space therebetween and are insulated and separated from each other. More specifically, the pair of second emitter junctions 64 are formed separately from each other in a film shape along one side and the other side of the emitter trench 63 in the cross section shown in FIG. As a result, a space defined by the back surfaces of the pair of second emitter junctions 64 (opposite surfaces that are in contact with the emitter trench 63) is formed at the center in the width direction of the emitter trench 63. The space is completely backfilled with the central insulating film 21 up to the opening end of the emitter trench 63, so that the pair of second emitter junctions are insulated from each other.

  The pair of second emitter junctions 64 are each connected to the p-type floating region 62 via the insulating film 18. Further, the pair of second emitter junctions 64 are formed so as to be integrated with the emitter junction 20 at each short side of the annular trench 10. As a result, power is supplied from the emitter electrode 6 to the second emitter junction 64 via the emitter junction 20. The pair of second emitter junctions 64 is formed of the same material as the gate junction 19 and the emitter junction 20.

  In order to form such a semiconductor device 61, for example, in the step of forming the annular trench 10 in FIG. 6B described above, the layout of the hard mask 51 may be changed so that the emitter trench 63 is formed. Thereafter, the second emitter junction 64 can be formed through the same process (see FIGS. 6E to 6H) as the process of forming the gate junction 19 and the emitter junction 20.

As described above, even with the configuration of the semiconductor device 61 according to the second embodiment, the same effects as those of the semiconductor device 1 according to the first embodiment described above can be obtained.
FIG. 8 is a schematic cross-sectional view of a semiconductor device 81 according to the third embodiment of the present invention. The semiconductor device 81 according to the third embodiment is different from the semiconductor device 61 according to the second embodiment described above in that an emitter trench 83 that is relatively narrow with respect to the annular trench 10 is formed. . Other configurations are the same as those of the semiconductor device 61 according to the second embodiment described above. 8, parts corresponding to those shown in FIG. 7 are given the same reference numerals, and descriptions thereof are omitted.

A plurality of emitter trenches 83 are formed in a region surrounded by the annular trench 10 so as to be narrower than the width W ₁ of the annular trench 10. The width W ₄ of the emitter trench 83 is, for example, the same width as the width W ₂ (see FIG. 2B) of the gate contact trench 11 and the emitter contact trench 12 described above, and is 0.7 μm to 1.2 μm. is there. In this embodiment, an example in which three emitter trenches 83 are formed is shown, but a configuration in which one or two emitter trenches 83 are formed may be employed. Further, a configuration in which three or more emitter trenches 83 are formed may be employed.

In the emitter trench 83, unlike the second embodiment described above, the pair of second emitter junctions 64 is not formed, but a second emitter junction 84 embedded as an integral part is formed.
As described above, the semiconductor device 81 can achieve the same effects as those described in the second embodiment. The width W ₄ of the emitter trench 83 is formed to be narrower than the width W ₁ of the annular trench 10. Therefore, in the process of FIG. 6E described above, the width W ₄ narrower than that of the annular trench 10 according to the same principle as that in which each of the relatively narrow contact trenches 11 and 12 is completely backfilled with the polysilicon deposition layer 52. The emitter trench 83 can be completely backfilled with the polysilicon deposition layer 52, and the second emitter junction 84 buried in the emitter trench 83 can be obtained.

FIG. 9 is a schematic cross-sectional view of a semiconductor device 91 according to the fourth embodiment of the present invention. The semiconductor device 91 according to the fourth embodiment is different from the semiconductor device 1 according to the first embodiment described above in that the semiconductor substrate 15 includes an n ⁻ type buffer region 92 and a contact trench 29 is formed. In addition, the p ⁺ -type base contact region 30 and the n ⁺ -type emitter region 31 are partly exposed from the surface of the semiconductor substrate 15. Other configurations are the same as those of the semiconductor device 1 according to the first embodiment described above. In FIG. 9, parts corresponding to those shown in FIG. 2A are given the same reference numerals, and description thereof is omitted.

The semiconductor substrate 15 according to the semiconductor device 91 includes an n ⁻ type buffer region 92 interposed between the p ⁺ type collector region 16 and the n ⁻ type drain region 17. The dopant concentration of the n ⁻ type buffer region 92 is, for example, 1 × 10 ¹⁵ cm ^{−3 to} 5 × 10 ¹⁷ cm ⁻³ .
In such an n ⁻ type buffer region 92, an n type dopant is selectively implanted into the back side of the semiconductor substrate 15 prior to the step of forming the p ⁺ type collector region 16 in the step shown in FIG. Can be formed.

A tungsten contact 93 containing tungsten is formed in each contact hole 35 related to the semiconductor device 91. The tungsten contact 93 is connected to the p ⁺ type base contact region 30 and a part of the n ⁺ type emitter region 31 on the surface of the semiconductor substrate 15. The emitter electrode 6 is connected to the p ⁺ type base contact region 30 and the buried emitter electrode 25 through a tungsten contact 93. On the other hand, the gate finger 2 is connected to the buried gate electrode 24 through a tungsten contact 93.

  As described above, according to the semiconductor device 91, since the tungsten contact 93 is formed in each contact hole 35, a good contact can be obtained. Therefore, it is not necessary to separately form the contact trench 29 in the step shown in FIG. 6J. Further, in the process shown in FIG. 6K, when forming the emitter electrode 6 and the gate finger 2, it is only necessary to bury tungsten in each contact hole 35, so that the manufacturing process is not complicated. Thus, even with the configuration of the semiconductor device 91, the same effects as those described in the first embodiment can be obtained.

FIG. 10 is a schematic plan view of the semiconductor device 101 according to the first reference example.
As shown in FIG. 10, for example, the semiconductor device 101 is formed in a rectangular chip shape in a plan view (hereinafter simply referred to as “plan view”) when the surface of the semiconductor device 101 is viewed from the normal direction. Yes. In the semiconductor device 101, an active region 102 and a termination region 113 surrounding the active region 102 are set. The active region 102 is formed in a substantially rectangular shape in plan view in the inner region of the semiconductor device 101. In the active region 102, a plurality of gate trenches 137 are formed in a stripe shape.

  On the surface of the semiconductor device 101, a gate metal 103 as an example of a surface gate metal that selectively surrounds the active region 102 and an emitter electrode 104 that selectively covers the active region 102 are formed. In FIG. 10, the gate metal 103 and the emitter electrode 104 are cross-hatched for clarity. Gate metal 103 further includes a gate pad 105 as an example of a pad portion, and a wiring portion 167 including a gate finger 106 and a pad peripheral portion 107.

The gate pad 105 is formed in a substantially quadrangular shape in plan view at the center in the longitudinal direction of the region along the one side 101 a of the semiconductor device 101. Electric power is supplied to the gate pad 105 from outside by connecting the bonding wire 108. The gate pad 105 is made of, for example, a metal material containing Al (aluminum) as a main component.
The gate finger 106 is formed in a line shape so as to surround the active region 102 of the semiconductor device 101. More specifically, the gate finger 106 extends from the side of the gate pad 105 in the stripe direction of the gate trench 137 (that is, the direction along one side 101a of the semiconductor device 101) from the side of the gate pad 105 in plan view, and further to the one side 101a. It is formed to extend in a direction perpendicular to the stripe direction intersecting at right angles (that is, a direction along the other side 101b and the side 101c facing the other side 101b). A pad peripheral portion 107 is formed around the gate pad 105 with the first removal region 110 interposed therebetween.

  In the first reference example, an example in which the gate pad 105 is provided in the central portion in the longitudinal direction of the region along the one side 101 a of the semiconductor device 101 will be described. However, the gate pad 105 is formed at one corner of the semiconductor device 101. May be. In the first reference example, an example is shown in which the gate finger 106 is not formed on the side 101d facing the one side 101a of the semiconductor device 101. However, the gate finger 106 extends around the entire circumference of the semiconductor device 101. It may be formed.

  The first removal region 110 is formed in a substantially square annular shape in plan view so as to surround the periphery of the gate pad 105. The first removal region 110 is a region where the metal material is removed, and is formed so that the gate pad 105 and the pad peripheral portion 107 do not contact each other. In the first reference example, an example in which the first removal region 110 is formed in an annular shape that surrounds the entire periphery of the gate pad 105 will be described. However, the first removal region 110 is formed on the gate pad 105. A configuration in which a part of the periphery is selectively enclosed may be used.

  The pad peripheral portion 107 is formed in a substantially square ring shape so as to surround the entire periphery of the gate pad 105 in a plan view. The pad peripheral portion 107 is formed so as to be integrated with the gate finger 106 in a region on the side of the gate pad 105. A second removal region 111 that selectively surrounds the periphery of the first removal region 110 is formed in the pad peripheral portion 107, whereby the pad peripheral portion 107 includes the first removal region 110 and the second removal region 111. The inner region 107a is sandwiched between the inner region 107a and the outer region 107b surrounding the inner region 107a.

  An emitter electrode 104 is formed in the inner region of the semiconductor device 101 partitioned by the gate metal 103 with the third removal region 112 interposed therebetween. The third removal region 112 is formed in a line shape along the gate metal 103. The emitter electrode 104 is formed so as to cover the active region 102. In a region below the gate metal 103 and the emitter electrode 104, a first lead wire 115, a gate finger lead wire 116, and a second lead wire 117 are formed via an interlayer insulating film 145 (see FIG. 13A).

FIG. 11 is a schematic plan view for explaining the first routing wiring 115, the gate finger routing wiring 116, and the second routing wiring 117 of the semiconductor device 101 according to the first reference example. 12 is an enlarged plan view of the first routing wiring 115, the gate finger routing wiring 116, and the second routing wiring 117 of the semiconductor device 101 shown in FIG.
As shown in FIG. 11, the first routing wiring 115 is formed in a bent structure in plan view so as to straddle the gate pad 105 and the pad peripheral portion 107 in a region below the gate pad 105. More specifically, the first routing wiring 115 is formed in a square ring shape so as to cross the first removal region 110 from the gate pad 105 to the inner region 107 a of the pad peripheral portion 107. The first routing wiring 115 is made of a material having a higher resistance value than that of the gate metal 103, and is preferably made of an electrode material such as polysilicon.

  As shown in FIG. 12, the first routing wiring 115 is electrically connected to the gate pad 105 via the gate pad contact 118 and to the pad peripheral portion 107 via the first pad peripheral portion contact 119, respectively. Has been. The gate pad contact 118 is formed in the gate pad 105 in a square ring shape in plan view surrounding the gate pad 105. On the other hand, the first pad peripheral portion contact 119 is formed in a square shape in plan view surrounding the first removal region 110 in the inner region 107 a of the pad peripheral portion 107. As described above, the gate pad 105 is electrically connected to the pad peripheral portion 107 and the gate finger 106 via the first routing wiring 115.

  The gate finger routing wiring 116 is formed in a region below the gate finger 106. The gate finger routing wiring 116 is formed narrower than the gate finger 106 and is completely covered by the gate finger 106. The gate finger routing wiring 116 is formed of the same electrode material as the first routing wiring 115. As shown in FIG. 12, the gate finger routing wiring 116 is electrically connected to the gate finger 106 through the gate finger contact 120.

  The second routing wiring 117 is formed at a predetermined interval from the first routing wiring 115 so as to selectively surround the first routing wiring 115. The second routing wiring 117 is formed so as to straddle the pad peripheral portion 107 and the active region 102. More specifically, the second routing wiring 117 is formed so as to cross from the inner region 107 a of the pad peripheral portion 107 to the second removal region 111, the outer region 107 b of the pad peripheral portion 107, and the third removal region 112. Has been. The second lead wiring 117 is integrally connected to the gate finger lead wiring 116 at the side of the region where the gate pad 105 is formed. The second routing wiring 117 is made of the same electrode material as the first routing wiring 115.

  As shown in FIG. 12, the second routing wiring 117 is connected to the inner region 107a of the pad peripheral portion 107 via the second pad peripheral portion contact 121 and to the pad periphery via the third pad peripheral portion contact 122. The outer region 107b of the portion 107 is electrically connected to each other. The second pad peripheral portion contact 121 is formed in a line shape that selectively surrounds the first pad peripheral portion contact 119 in the inner region 107 a of the pad peripheral portion 107. On the other hand, the third pad peripheral portion contact 122 is formed in a line shape surrounding the second removal region 111 in the outer region 107b of the pad peripheral portion 107, and on the side of the region where the gate pad 105 is formed. The gate finger contact 120 is integrally connected. As described above, the pad peripheral portion 107 is electrically connected to the gate finger 106 via the second lead wiring 117.

Next, a partial cross-sectional configuration of the semiconductor device 101 will be described with reference to FIG. 13A. FIG. 13A is a cross-sectional view taken along section line XIIIA-XIIIA shown in FIG.
As illustrated in FIG. 13A, the semiconductor device 101 includes a semiconductor substrate 125 as an example of a semiconductor layer. The semiconductor substrate 125 is, for example, an n ⁻ type silicon substrate, and has a structure in which a p ⁺ type collector region 126 and an n ⁻ type drain region 127 are stacked in this order from the back surface side. The p ⁺ type collector region 126 is exposed on the entire back surface of the semiconductor substrate 125, and the n ⁻ type drain region 127 is exposed on the surface of the semiconductor substrate 125. The dopant concentration of the p ⁺ -type collector region 126 is, for example, 5 × 10 ¹⁵ cm ⁻³ to 2 × 10 ¹⁹ cm ⁻³ . As the p-type dopant, for example, B (boron), Al (aluminum), or the like can be used (hereinafter the same). On the other hand, the dopant concentration of the n ⁻ -type drain region 127 is, for example, 5 × 10 ¹³ cm ⁻³ to 1 × 10 ¹⁵ cm ⁻³ . In addition, as the n-type dopant, for example, N (nitrogen), P (phosphorus), As (arsenic), or the like can be used (hereinafter the same).

A plurality of gate trenches 137 are formed in a stripe shape in the active region 102 of the semiconductor substrate 125. A region having a constant width is provided between the plurality of gate trenches 137, and one IGBT unit cell 136 is formed in this region.
The gate trench 137 is formed so as to dig up the surface of the semiconductor substrate 125. More specifically, the gate trench 137 is formed with a certain width and is flush with the side surface formed substantially perpendicular to the surface of the semiconductor substrate 125 and the surface of the semiconductor substrate 125. And a formed bottom.

The unit cell 136 is formed along the stripe direction of the gate trench 137, and includes a p-type base region 140, p ⁺ -type base contact regions 141 and n ⁺ formed in an inner region of the p-type base region 140. A mold emitter region 142.
The p-type base region 140 is shared by one gate trench 137 and the other gate trench 137 adjacent to each other. The bottom of the p-type base region 140 is located closer to the surface of the semiconductor substrate 125 than the bottom of the gate trench 137. The dopant concentration of the p-type base region 140 is, for example, 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ .

The n ⁺ -type emitter region 142 is formed on the surface of the semiconductor substrate 125. One n ⁺ -type emitter region 142 is provided on each side of the side surface of the gate trench 137, and each n ⁺ -type emitter region 142 is exposed on the side surface of the gate trench 137. The dopant concentration of the n ⁺ -type emitter region 142 is 1 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ . On the other hand, the p ⁺ type base contact region 141 is formed so as to be sandwiched between the n ⁺ type emitter regions 142. The dopant concentration of the p ⁺ type base contact region 141 is, for example, 1 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ .

An insulating film 134 is formed on the surface of the semiconductor substrate 125 and the inner surface (side surface and bottom portion) of the gate trench 137. The insulating film 134 is made of an insulating material such as silicon oxide (SiO ₂ ), silicon nitride (SiN), aluminum oxide (Al ₂ O ₃ ), for example. A gate electrode 138 is buried in the gate trench 137 with the insulating film 134 interposed therebetween.

  The gate electrode 138 is embedded in the gate trench 137 so that the surface of the gate electrode 138 exposed from the gate trench 137 is flush with the surface of the semiconductor substrate 125. The electrode material of the gate electrode 138 is preferably made of, for example, the same electrode material as that of the first and second lead wirings 115 and 117 described above. In this case, since the first and second lead wirings 115 and 117 can be formed in the same process as the gate electrode 138, the manufacturing process can be simplified.

On the surface of the semiconductor substrate 125, the first and second lead wirings 115 and 117 and the gate finger lead wiring 116 (see FIG. 11) are formed via the insulating film 134. The second routing wiring 117 includes a leading portion 117a that is led to the active region 102 along the direction crossing the stripe.
The gate electrode 138 is electrically connected to the gate finger routing wiring 116 formed so as to cross the gate trench 137 at both longitudinal ends of the gate trench 137. As a result, the gate electrode 138 is electrically connected to the gate finger 106 via the gate finger routing wiring 116. Further, the gate electrode 138 is electrically connected to the lead portion 117a as shown in FIG. 13A. Thereby, the gate electrode 138 is electrically connected to the pad peripheral part 107 through the lead part 117a. The second lead-out wiring 117 may have a lead-out portion 117a (see FIGS. 11 and 12) drawn out to the active region 102 along the stripe direction, thereby being electrically connected to the pad peripheral portion 107. May be.

An interlayer insulating film 145 is formed on the surface of the semiconductor substrate 125. The interlayer insulating film 145 in the active region 102 is formed with an emitter contact hole 147 that selectively exposes the p ⁺ type base contact region 141 and a part of the n ⁺ type emitter region 142. The interlayer insulating film 145 in the termination region 113 includes the gate pad contact 118, the first pad peripheral contact 119, the gate finger contact 120 (see FIG. 12), the second pad peripheral contact 121, A third pad peripheral portion contact 122 is formed. The interlayer insulating film 145 is made of, for example, an insulating material such as tetraethyl orthosilicate (TEOS), boron phosphorus silicate glass (BPSG), silicon oxide (SiO ₂ ), or the like.

A gate metal 103 and an emitter electrode 104 are formed on the interlayer insulating film 145. The emitter electrode 104 is electrically connected to the p ⁺ type base contact region 141 and a part of the n ⁺ type emitter region 142 via the emitter contact hole 147.
On the other hand, the gate metal 103 is electrically connected to the first and second lead wirings 115 and 117 through the contacts 118, 119, 121, and 122 as described above. As a result, the gate metal 103 is electrically connected to the gate electrode 138 via the first and second lead wires 115 and 117 and the lead portion 117a of the second lead wire 117, and the surface current is transferred from the gate pad 105 to the gate electrode. A current path leading to 138 is formed.

A surface protective film 146 is formed on the interlayer insulating film 145 so as to selectively cover a region between the gate pad 105 and the emitter electrode 104. The surface protective film 146 is made of resin, for example.
The semiconductor device 101 is represented by an electric circuit diagram shown in FIG. 13B. FIG. 13B is an electric circuit diagram for explaining the electrical structure of the semiconductor device 101 shown in FIG.

  As illustrated in FIG. 13B, the semiconductor device 101 includes a current limiting unit 139 interposed between the gate pad 105 and the gate electrode 138. The current limiting unit 139 includes a resistance component of the first routing wiring 115 connected in series to the gate pad 105, a resistance component of the gate finger routing wiring 116, and a resistance component of the second routing wiring 117. When a voltage is applied to the gate pad 105, a current flows through the gate electrode 138 through the current limiting unit 139.

  As described above, according to the configuration of the semiconductor device 101, as shown in FIGS. 12, 13A, and 13B, the first and second currents flow when the current flows from the gate pad 105 to the pad peripheral portion 107 and the gate finger 106. Since the routing wirings 115 and 117 (current limiting unit 139) are routed, the current flow to the pad peripheral portion 107 and the gate finger 106 due to the surface current can be limited at a position close to the gate pad 105. As a result, a rush current is locally applied to the gate electrode 138 of the MIS gate structure 132 at a position close to the gate pad 105 (in particular, the peripheral portion of the gate pad 105 electrically connected via the pad peripheral portion 107). (Di / dt) flows, and the MIS gate structure 132 can be prevented from being turned on locally. As a result, it is possible to suppress variation in applied current among the plurality of MIS gate structures 132 regardless of whether it is far from the gate pad 105.

  Even if a rush current flows from the gate pad 105 to the inner region 107 a of the pad peripheral portion 107, the pad peripheral portion 107 thereafter passes through the second routing wiring 117 or bypasses the third removal region 112. Will flow to the outer region 107b. That is, the current flow to the gate electrode 138 around the gate pad 105 can be restricted twice. Therefore, the inrush current flowing into the gate electrode 138 of the MIS gate structure 132 disposed in the vicinity of the gate pad 105 can be effectively limited. On the other hand, since the gate finger 106 is in contact with the gate electrode 138 of the MIS gate structure 132 at a position relatively far from the gate pad 105, the inrush current can be limited thereby.

Further, when the switching characteristics of the semiconductor device 101 were examined, the graphs shown in FIGS. 14A to 14C could be obtained.
14A to 14C are graphs showing switching characteristics of the semiconductor device 101 shown in FIG.
14A shows the relationship between the gate-emitter voltage V _GE (V) of the semiconductor device 101 and time (nsec), and FIG. 14B shows the collector-emitter voltage V _CE (V) of the semiconductor device 101. FIG. 14C shows the relationship between the collector current I _C (A) of the semiconductor device 101 and time (nsec). 14A to 14C, the characteristics of the semiconductor device 101 are indicated by solid lines, and the switching characteristics of the semiconductor device 148 according to the reference example are indicated by broken lines. The semiconductor device 148 according to the reference example is a semiconductor device in which the first and second lead wirings 115 and 117 are not formed.

Referring to FIG. 14A, in the semiconductor device 148 according to the reference example, the turn-on time t _on, the gate - noise voltage V _GE between the emitter can be confirmed that has occurred. On the other hand, in the semiconductor device 101, noise as in the semiconductor device 148 according to the reference example cannot be confirmed. Note that the turn-on time t _on, IGBT gate at turn - is defined as the time required until the voltage V _CE between the emitter is lowered to 10% of the maximum value - from the rising of the voltage V _GE between the emitter collector.

Further, referring to FIG. 14B, in the semiconductor device 148 according to the reference example, the rise time t _r, the collector - noise voltage V _CE between the emitter can be confirmed that has occurred. On the other hand, in the semiconductor device 101, noise as in the semiconductor device 148 according to the reference example cannot be confirmed. Note that the rise time t _r, from the time when the collector current I _C during turn of the IGBT is increased to 10% of the maximum value collector - the time required until the voltage V _CE between the emitter is lowered to 10% of the maximum value Defined.

Further, referring to FIG. 14C, in the semiconductor device 148 according to the reference example, the reverse recovery time t _rr, it can be confirmed that the noise occurs in the collector current I _C. On the other hand, in the semiconductor device 101, noise as in the semiconductor device 148 according to the reference example cannot be confirmed. The reverse recovery time _trr is defined as the time required for the reverse recovery current of the built-in diode to disappear. Further, in the semiconductor device 101, it can be confirmed that the value of the effective current hardly changes while the peak current value is lower than the peak current value of the semiconductor device 148 according to the reference example in the reverse recovery time _trr . . This is because a current other than the current detected as an effective current, that is, a surface current (inrush current) flowing through the gate metal 103 flows to the gate electrode 138 via the first and second routing wires 115 and 117. .

  14A to 14C, the generation of noise in the semiconductor device 148 according to the reference example is described as follows. In other words, the gate pad 105 formed in the periphery of the MIS gate structure 132, the pad peripheral portion 107, and the gate finger 106 are normally configured with an LC resonance circuit based on parasitic inductance and parasitic capacitance. Therefore, when a surface current flows, resonance noise is generated by the switching of the MIS gate structure 132 as a trigger. In the semiconductor device 148 according to the reference example, since the first and second routing wirings 115 and 117 are not formed, such a surface current cannot be limited. Therefore, in the semiconductor device 148 according to the reference example, as shown in the graphs of FIGS. 14A to 14C, the waveform of the resonance noise is detected.

  On the other hand, according to the configuration of the semiconductor device 101, since the current flow into the pad peripheral portion 107 and the gate finger 106 due to the surface current can be restricted, it is possible to suppress the MIS gate structure 132 from being turned on locally. Therefore, it is possible to suppress the generation of resonance noise triggered by the switching of the MIS gate structure 132. Therefore, switching loss caused by resonance noise can be reduced during the switching-on operation.

As described above, it is possible to provide the semiconductor device 101 that can effectively limit the inrush current and reduce the generation of switching loss and resonance noise.
FIG. 15 is a schematic plan view of a semiconductor device 151 according to the second reference example. FIG. 16 is a schematic plan view for explaining the first and second routing wirings 160 and 161 of the semiconductor device 151 according to the second reference example. The semiconductor device 151 according to the second reference example is different from the semiconductor device 101 according to the first reference example described above in that a gate metal 152 is formed instead of the gate metal 103. Other configurations are the same as those of the semiconductor device 101 according to the first reference example. 15 and FIG. 16, parts corresponding to those shown in FIGS. 10 to 13A described above are denoted by the same reference numerals, and description thereof is omitted. The semiconductor device 151 is formed in a square chip shape in plan view as in the first reference example described above, and a plurality of gate trenches 137 are formed in stripes in the active region 102.

  As shown in FIG. 15, a gate metal 152 as an example of a surface gate metal is formed in the termination region 113 of the semiconductor device 151 so as to selectively surround the active region 102. The gate metal 152 further includes a gate pad 153 as an example of a pad portion, and a wiring portion 168 including a first gate finger 154, a second gate finger 155, and a pad peripheral portion 156.

In the second reference example, the gate pad 153 is formed at one corner of the semiconductor device 151. The gate pad 153 is supplied with electric power from the outside when the bonding wire 108 is connected thereto.
The first gate finger 154, the second gate finger 155, and the pad peripheral portion 156 are formed in a line shape so as to surround the active region 102 of the semiconductor device 151.

  The first gate finger 154 is formed to be continuous with the gate pad 153. More specifically, the first gate finger 154 extends from the gate pad 153 in the stripe direction of the gate trench 137 (that is, the direction along one side 151a of the semiconductor device 151) and further intersects the one side 151a at a right angle. It extends in the direction orthogonal to the direction (that is, the direction along the other side 151b). The first gate finger 154 is formed so as to cross one end in the longitudinal direction of the gate trench 137 in a region along the side 151 b of the semiconductor device 151.

  The pad peripheral portion 156 is formed so as to selectively surround the inner periphery of the gate pad 153 with the removal region 157 interposed therebetween. The removal region 157 is formed in a line shape around the gate pad 153. That is, the pad peripheral portion 156 is formed separately from both the gate pad 153 and the first gate finger 154 by the removal region 157.

  The second gate finger 155 is formed along the side 151 c facing the other side 151 b of the semiconductor device 151. More specifically, it is formed so as to cross the other end in the longitudinal direction of the gate trench 137 from the gate pad 153, and is formed so as to be integrated with the one end 156 a of the pad peripheral portion 156. That is, the second gate finger 155 is also formed separately from both the gate pad 153 and the first gate finger 154.

As shown in FIG. 16, a first routing wiring 160 and a second routing wiring 161 are formed in a region below the gate metal 152.
The first routing wiring 160 is formed so as to straddle the first gate finger 154 and the second gate finger 155. More specifically, the first routing wiring 160 is formed along the region where the first gate finger 154, the gate pad 153, and the second gate finger 155 are formed across the region where the removal region 157 is formed. Has been. The first routing wiring 160 is formed wider than the first gate finger 154 and the second gate finger 155. The first routing wiring 160 is made of a material having a higher resistance value than that of the gate metal 152, and is preferably made of an electrode material such as polysilicon.

  The second routing wiring 161 is formed along the region where the pad peripheral portion 156 is formed. The second routing wiring 161 is formed wider than the pad peripheral portion 156. The second routing wiring 161 is formed so as to be integrated with the first routing wiring 160 on the region side where the second gate finger 155 is formed. An end portion 161 a on the gate pad 153 side of the second routing wiring 161 is formed so as to cross the removal region 157 and reach the gate pad 153.

As shown in FIGS. 15 and 16, the gate pad 153 and the first gate finger 154 are connected to the first routing wiring 160 via the first contact 162 formed along the gate pad 153 and the first gate finger 154. Electrically connected.
On the other hand, the pad peripheral portion 156 and the second gate finger 155 are electrically connected to the first lead wiring 160 through a second contact 163 formed along the second gate finger 155. That is, the gate pad 153 is electrically connected to the pad peripheral portion 156 and the second gate finger 155 through the first routing wiring 160.

  The first and second lead wirings 160 and 161 are electrically connected to the gate electrode 138 embedded in the gate trench 137 as in the first reference example. As a result, the gate metal 152 is electrically connected to the gate electrode 138 via the first and second lead wirings 160 and 161, and a current path is formed to guide the surface current from the gate pad 153 to the gate electrode 138. Yes.

  As described above, in the semiconductor device 151, the first gate finger 154 is not in contact with the gate electrode 138 in the portion extending along the MIS gate structure 132 from the corner gate pad 153 to the adjacent corner, but the gate pad. The gate electrode 138 is in contact with the side opposite to the side 153. That is, since the contact is made with the gate electrode 138 of the MIS gate structure 132 at a position relatively far from the gate pad 153, the inrush current can be limited thereby. On the other hand, the second gate finger 155 and the pad peripheral part 156 are in contact with the gate electrode 138 of the MIS gate structure 132 at a position relatively close to the gate pad 153, but the second gate finger 155 is connected to the gate pad 153. They are arranged separately. In addition, since the second gate finger 155 and the pad peripheral portion 156 are electrically connected to the gate pad 153 via the first and second routing wirings 160 and 161, it is assumed that an inrush current flows to the gate pad 153. Also, the inrush current can be limited. Therefore, the same effects as those described in the first reference example can be obtained.

As mentioned above, although embodiment of this invention and the form which concerns on the 1st and 2nd reference example were demonstrated, this invention can also be implemented with another form.
For example, in the above-described second and third embodiments, the example in which the emitter trenches 63 and 83 are formed in stripes in the longitudinal direction of the annular trench 10 has been described. However, the emitter trenches 63 and 83 are not seen in a plan view. Further, it may be formed in a stripe shape in the short direction of the annular trench 10. The emitter trenches 63 and 83 may be formed in a mesh shape in the inner region of the annular trench 10.

In each of the above-described embodiments, the example in which the gate contact trench 11 and the emitter contact trench 12 are formed in an angular arch shape in plan view has been described. However, for example, other closed curves such as a circular arch shape and a triangular arch shape are used. It may be a structure.
Further, in each of the above-described embodiments, the example in which the bottom portion of each trench 10, 11, 12, 63, 83 is formed to be rounded from the side surface has been described, but each trench 10, 11, 12, The bottoms 63 and 83 may be formed in parallel with the surface of the semiconductor substrate 15.

In each of the above-described embodiments, the example in which the IGBT is formed in the active region 4 has been described. However, in addition to the IGBT, a CMOS (Complementary MOS) may be formed. For example, an example shown in FIG. 17 may be adopted as a configuration including a MOS structure.
FIG. 17 is a schematic cross-sectional view showing a modification of the semiconductor device 1 according to the first embodiment. In FIG. 17, the same components as those of the semiconductor device 1 are denoted by the same reference numerals and description thereof is omitted.

As shown in FIG. 17, in this modification, a semiconductor device 94 employing an n ⁺ type drain region 95 instead of the p ⁺ type collector region 16 is formed. That is, in the semiconductor device 94, a MOSFET is formed instead of the IGBT. In this case, the emitter electrode 6 (n ⁺ -type emitter region 31) of the IGBT corresponds to the source electrode 96 (n ⁺ -type source region 97) of the semiconductor device 94. Of course, in each of the semiconductor devices 61, 81, 91 according to the second to fourth embodiments, an n ⁺ type drain region 95 may be adopted instead of the p ⁺ type collector region 16 to form a MOSFET structure. .

  In each of the above-described embodiments, an example in which an IGBT is formed in the active region 4 has been described. However, in addition to the IGBT, various semiconductors such as a BJT (Bipolar Junction Transistor), a JFET (Junction Field Effect Transistor), a capacitor, and a resistor are used. Elements and circuit elements may be formed. Further, depending on the combination of these semiconductor elements and circuit elements, LSI (Large Scale Integration), SSI (Small Scale Integration), MSI (Medium Scale Integration), VLSI (Very Large Scale Integration), ULSI (Ultra-Very Large Scale). An integrated circuit such as Integration) may be configured.

In each of the above-described embodiments, the conductivity type of each semiconductor region such as the p-type floating region 9, the p ⁺ -type collector region 16, and the n ⁻ -type drain region 17 may be reversed. Therefore, in this case, the p-type floating region 9 becomes an n-type floating region, the p ⁺ -type collector region 16 becomes an n ⁺ -type collector region, and the n ⁻ -type drain region 17 becomes a p-type drain region. Of course, the conductivity type of other semiconductor regions is also reversed.

Further, the semiconductor devices 1, 61, 81, 91 according to the first to fourth embodiments can be applied to an inverter circuit as shown in FIG.
FIG. 18 is a circuit diagram for explaining an inverter circuit 201 to which the semiconductor devices 1, 61, 81, 91 according to the first to fourth embodiments are applied.
The inverter circuit 201 is a three-phase inverter circuit connected to the three-phase motor 202 as a load. Inverter circuit 201 includes a DC power supply 203 and a switch unit 204.

DC power supply 203 is, for example, 700V. The DC power supply 203 has a high voltage side wiring 205 connected to the high voltage side and a low voltage side wiring 206 connected to the low voltage side. The switch unit 204 includes three arms 207 to 209 corresponding to the respective phases of the U phase 202U, the V phase 202V, and the W phase 202W of the three-phase motor 202.
The arms 207 to 209 are connected in parallel between the high-voltage side wiring 205 and the low-voltage side wiring 206. The arms 207 to 209 include high-side high-side transistors 210H to 212H (semiconductor devices 1, 61, 81, 91) and low-voltage side low-side transistors 210L to 212L (semiconductor devices 1, 61, 81, 91), respectively. I have. Regenerative diodes 213H to 215H and 213L to 215L are connected in parallel to the transistors 210H to 212H and 210L to 212L, respectively, in such a direction that a forward current flows from the low voltage side to the high voltage side.

  In the inverter circuit 201, the on / off control of the high side transistors 210H to 212H and the low side transistors 210L to 212L of the arms 207 to 209 is alternately switched, that is, one transistor is switched on and the other transistor is switched off. By alternately switching the state, the alternating current can be passed through the three-phase motor 202. On the other hand, energization to the three-phase motor 202 can be stopped by turning off both transistors. In this way, the switching operation of the three-phase motor 202 is performed.

  In the first reference example described above, an example is described in which one first removal region 110 is formed in an annular shape so as to surround the gate pad 105 (see FIG. 10). The region 110 may be formed in an annular shape so as to selectively surround the periphery of the gate pad 105. For example, in FIG. 10, the first removal region 110 may not be formed on the opposite side of the gate pad 105 from the protruding direction of the gate pad 105. In this case, both the pad peripheral portion 107 and the gate finger 106 are electrically connected to the gate pad 105 through the metal constituting the gate metal 103. Even in this case, in order for the current supplied to the gate pad 105 to flow to the pad peripheral portion 107, the first removal region 110 surrounding the three sides of the gate pad 105 must be bypassed. Can be reduced.

Further, in the first reference example described above, the example in which the second removal region 111 selectively surrounds part of the periphery of the gate pad 105 has been described (see FIG. 11). The gate pad 105 may be surrounded by the entire periphery.
In the above-described first reference example, the example in which the first routing wiring 115 is formed in a closed ring shape in a plan view in the region below the gate pad 105 has been described. If 105 is configured to be electrically connected to the pad peripheral portion 107, it may not be formed in an annular shape. Therefore, the first routing wiring 115 may be formed in a line shape in the region below the gate pad 105.

In the first reference example described above, the example in which the gate finger routing wiring 116 is formed narrower than the gate finger 106 has been described (see FIG. 11). It may be configured to be wider than 106.
In the first reference example described above, the second lead wiring 117 is described as being formed so as to selectively surround the first lead wiring 115 (see FIG. 11). 117 may be formed so as to surround the entire circumference of the first routing wiring 115. In this case, the second pad peripheral portion contact 121 (see FIG. 12) may be formed in a quadrangular annular shape in plan view so as to surround the entire periphery of the first pad peripheral portion contact 119. .

  In the second reference example described above, the example in which the removal region 157 is formed in a line along the periphery of the gate pad 153 has been described (see FIG. 15). However, the removal region 157 extends around the gate pad 153. It may be formed over the entire circumference. In this case, the first gate finger 154 is also formed separately from the gate pad 153. Even in such a configuration, since the first routing wiring 160 is formed so as to straddle the gate pad 153 and the first gate finger 154, the gate pad 153 and the first gate finger 154 are electrically connected. be able to. Therefore, the surface current flowing on the surface of the gate pad 153 can be limited even between the gate pad 153 and the first gate finger 154.

  In the first and second reference examples described above, the example in which the gate trench 137 having a stripe shape in plan view is formed in the active region 102 has been described. However, the gate trench 137 is formed in a mesh shape in plan view. May be. In this case, the IGBT unit cell 136 is formed in a region surrounded by the mesh-shaped gate trench 137.

In the first and second reference examples described above, the example in which the IGBT is formed in the active region 102 has been described. However, the example illustrated in FIG. 19 may be employed.
FIG. 19 is a schematic cross-sectional view showing a modification of the semiconductor devices 101 and 151 according to the first and second reference examples. In FIG. 19, the same components as those of the semiconductor devices 101 and 151 are denoted by the same reference numerals and description thereof is omitted.

As shown in FIG. 19, in this modification, a semiconductor device 191 employing an n ⁺ type drain region 192 instead of the p ⁺ type collector region 126 is formed. That is, in the semiconductor device 191, a MOSFET is formed instead of the IGBT. In this case, the emitter electrode 104 (n ⁺ -type emitter region 142) of the IGBT corresponds to the source electrode 193 (n ⁺ -type source region 194) of the MOSFET.

Even with such a configuration, it is possible to suppress the gate electrode 138 of the MIS gate structure 132 in the MOSFET from being turned on locally, so that the same effect as in the case of the IGBT can be obtained. Further, SiC (silicon carbide) may be employed for the semiconductor substrate 125 to form a SiC-IGBT or a SiC-MOSFET.
In the first and second reference examples described above, an example in which a trench gate type IGBT is formed in the active region 102 has been described. However, a gate electrode is formed on the surface of the semiconductor substrate 125 via an insulating film 134. A planar gate type IGBT may be adopted. Of course, a planar gate type MOSFET may be adopted instead of the planar gate type IGBT.

  In the first and second reference examples described above, the example in which the bottom portion of the gate trench 137 is formed in parallel with the surface of the semiconductor substrate 125 has been described. However, the bottom portion of the gate trench 137 is rounded from the side surface. It may be formed to take on. In the first and second reference examples described above, the example in which the side surface of the gate trench 137 is formed at a right angle to the surface of the semiconductor substrate 125 has been described. It may be formed in a tapered shape in which the width gradually decreases from the bottom toward the bottom.

  Further, in the first and second reference examples described above, the example in which the IGBT is formed in the active region 102 has been described. Various semiconductor elements such as transistors), capacitors, resistors, and circuit elements may be formed. Further, depending on the combination of these semiconductor elements and circuit elements, LSI (Large Scale Integration), SSI (Small Scale Integration), MSI (Medium Scale Integration), VLSI (Very Large Scale Integration), ULSI (Ultra-Very Large Scale). An integrated circuit such as Integration) may be configured.

In the first and second reference examples, the conductivity types of the semiconductor regions of the p ⁺ -type collector region 126, the n ⁻ -type drain region 127, the p-type base region 140, and the n ⁺ -type emitter region 142 are inverted. It may be a configuration.
Further, the semiconductor devices 101 and 151 according to the first and second reference examples can be applied to an inverter circuit 221 as shown in FIG.

FIG. 20 is a circuit diagram for explaining an inverter circuit 221 to which the semiconductor devices 101 and 151 according to the first and second reference examples are applied.
The inverter circuit 221 is different from the inverter circuit 201 shown in FIG. 18 in that, instead of the high side transistors 210H to 212H and the low side transistors 210L to 212L, the high side transistors 222H to 224H (semiconductor devices 101 and 151) and the low side transistor 222L. To 224L (semiconductor devices 101 and 151) are connected. Other configurations are the same as those of the inverter circuit 201 shown in FIG.

  As shown in FIG. 20, each of the high-side transistors 222H to 224H and the low-side transistors 222L to 224L has a current limiting unit 139 interposed between the gate pad 105 and the gate electrode 138 (FIG. 13B). See also). The current limiting unit 139 can reduce switching loss caused by resonance noise during the switching-on operation.

In addition, various design changes can be made within the scope of matters described in the claims. Features extracted from the description of this specification and the drawings are shown below.
[A1] A semiconductor layer having an active region in which a plurality of MIS gate structures are arranged, a surface gate metal disposed on the semiconductor layer, a pad portion for receiving external power supply, and the active A removal portion for extending along the periphery of the region and having a wiring portion electrically connected to the gates of the plurality of MIS gate structures and separating the pad portion and the wiring portion at least partially is formed. A semiconductor device comprising: a surface gate metal; and a lead wiring made of a material having a higher resistance value than the surface gate metal and routed from the pad portion to the adjacent wiring portion across the removal region.

  In a semiconductor device including a gate pad, there is a known problem that an inrush current (di / dt) is generated when a voltage is applied to the gate pad. This inrush current has a property of flowing on the surface of the gate pad and the gate metal wiring connected to the gate pad. Therefore, an inrush current flows into the gate structure close to the gate pad as a surface current, and as a result, the gate structure may be turned on locally. The generation of such a surface current not only causes variations in applied current among a plurality of gate structures, but is one of the causes of switching loss during the switching-on operation.

In addition, the gate pad and the gate metal wiring formed around the gate structure usually form an LC resonance circuit with parasitic inductance and capacitance, so when surface current flows, switching of the gate structure becomes a trigger. Resonance noise occurs. As a result, the switching loss during the switching-on operation increases.
Therefore, a semiconductor device that can effectively limit the inrush current and reduce the generation of switching loss and resonance noise is desired.

  According to the semiconductor device described in A1, since current flows through the lead wiring when current flows from the pad portion to the wiring portion, current flow into the wiring portion due to surface current can be limited. Thereby, a rush current (di / dt) flows locally to the gate of the MIS gate structure at a position close to the pad portion, and the MIS gate structure can be prevented from being turned on locally. As a result, it is possible to suppress variations in applied current among a plurality of MIS gate structures regardless of whether the distance is far from the pad portion. In addition, since it is possible to suppress the MIS gate structure from being turned on locally, it is possible to suppress the generation of resonance noise triggered by the switching of the MIS gate structure. Therefore, switching loss caused by resonance noise can be reduced during the switching-on operation.

[A2] The semiconductor device according to A1, wherein the removal region is formed so as to surround the pad portion.
According to this semiconductor device, since the surface current can be limited at a position close to the pad portion, local current flow into the MIS gate structure near the pad portion can be effectively suppressed.
[A3] The semiconductor device according to A2, wherein the wiring portion includes a line-shaped gate finger extending so as to surround the active region.

According to this semiconductor device, since a current whose surface current is limited flows through the gate finger, variation in current can be suppressed along the longitudinal direction of the gate finger.
[A4] The semiconductor device according to A3, wherein the wiring portion further surrounds the removal region surrounding the pad portion and includes a pad peripheral portion formed integrally with the gate finger.
According to this semiconductor device, it is possible to suppress variation in current flowing into the gate of the MIS gate structure without using the gate finger.

  [A5] The plurality of MIS gate structures are formed in a stripe shape in plan view as viewed from the normal direction of the surface of the semiconductor layer, and the gate fingers cross the stripe MIS gate structure. The semiconductor device according to A3 or A4, wherein the semiconductor device is disposed and is in contact with a gate of the MIS gate structure at both longitudinal ends of the MIS gate structure.

[A6] The pad portion is formed in the middle of a region along the stripe direction of the MIS gate structure, and the gate fingers extend from the pad portion to both sides along the stripe direction, and further, the stripe shape The semiconductor device according to A5, which is formed so as to cross the MIS gate structure.
According to this semiconductor device, since the gate finger is in contact with the gate of the MIS gate structure at a position relatively far from the pad portion, it is possible to limit the inrush current.

  [A7] The semiconductor layer is formed in a square shape in plan view, the pad portion is formed in a corner portion of the rectangular semiconductor layer, and the gate finger is integrally connected to the pad portion. A first gate finger formed and arranged so as to extend along the stripe direction of the MIS gate structure, and separated from the pad portion and the removal region, so as to cross the MIS gate structure from the pad portion. A semiconductor device according to A5, comprising a second gate finger arranged.

  According to this semiconductor device, since the first gate finger is in contact with the gate of the MIS gate structure at a position relatively far from the pad portion, it is possible to limit the inrush current. On the other hand, the second gate finger is in contact with the gate of the MIS gate structure at a position relatively close to the pad portion, but the second gate finger is disposed separately from the pad portion. In addition, since the second gate finger is connected to the pad portion through the lead wiring, even if an inrush current flows through the pad portion, the inrush current can be limited.

[A8] The semiconductor device according to any one of A2 to A7, wherein the removal region selectively surrounds a part of the periphery of the pad portion.
[A9] The semiconductor device according to any one of A2 to A7, wherein the removal region surrounds the entire periphery of the pad portion.
According to this semiconductor device, the surface current can be limited over the entire circumference around the pad portion. As a result, local current flow into the MIS gate structure in the vicinity of the pad portion can be effectively suppressed.

[A10] The semiconductor device according to any one of A1 to A9, wherein the routing wiring connects the pad portion and the wiring portion via a lower portion of the removal region.
According to this semiconductor device, the routing wiring can be formed in the same process as the gate of the MIS gate structure. Therefore, the manufacturing process can be simplified. Therefore, in this case, the routing wiring is preferably formed of the same material as the gate of the MIS gate structure.

[A11] The semiconductor device according to A10, wherein the wiring portion is made of a metal material containing Al as a main component, and the lead wiring and the gate of the MIS gate structure are made of polysilicon.
[A12] The semiconductor device according to any one of A1 to A11, wherein an IGBT including a part of the MIS gate structure is formed in the semiconductor layer.

[A13] The semiconductor device according to A12, wherein the IGBT includes a trench gate type IGBT.
[B1] a semiconductor layer in which a trench is formed, an FET structure formed on a side of the trench and having an emitter region and a drain region facing each other across a base region in the depth direction of the trench, and the trench A floating region formed on the opposite side of the FET structure across the gate, and a gate junction provided in the same trench and insulated from each other in the trench, and an emitter junction electrically connected to the emitter region Each of the gate junction and the emitter junction through an insulating film.
A semiconductor device facing the structure and the floating region.

  According to this configuration, the capacitance component due to the contact between the trench and the floating region can be changed to the capacitance component (capacitance between the collector-emitter junction) in the junction region between the emitter junction and the floating region. As a result, the gate junction is not affected by the junction with the floating region. Therefore, switching loss can be reduced as compared with the conventional semiconductor device in which the floating region and the trench gate are joined. On the other hand, if the drain region of the FET structure facing the gate junction is grounded together with the collector region, the capacitance change between the gate junction and the drain region can be kept stable during the switching operation. As a result, generation of switching noise can be suppressed.

On the other hand, the inventors of the present application have formed a semiconductor device including an IGBT having a structure in which a plurality of trench emitters are formed between adjacent trench gates and the trench emitters and the floating region are electrically joined to each other (hereinafter referred to as “reference example”). "Semiconductor device according to the present invention"). In this structure, since there is no junction region between the trench gate and the floating region, the above-described problems of switching loss and switching noise can be improved. However, in the case of the semiconductor device according to the reference example, an FET structure is formed in each region between the trench gate and the trench emitter. Therefore, the trench gate and the trench emitter face each other through the FET structure. Therefore, the carrier accumulation effect by sandwiching the FET structure between the trench gates is reduced, and accordingly, the carrier density in the semiconductor layer is also reduced. As a result, the drift resistance in the drain region increases and the on-voltage tends to increase.
On the other hand, according to the configuration of the present invention, the gate junction can be opposed to each other via the insulating film and the FET structure, so that the carrier accumulation effect by the gate junction can be enhanced. Thereby, since the carrier density in the semiconductor layer increases, the drift resistance in the drain region can be reduced. Thereby, the on-voltage of the semiconductor device can be reduced.

Furthermore, according to the configuration of the present invention, unlike the semiconductor device according to the reference example, since the gate junction and the emitter junction are formed in the same trench, it is necessary to form the trench gate and the trench emitter. Absent. Therefore, the number of FET structures to be formed is small. That is, the number of contact openings for connecting the FET structure is small. Thereby, since a contact opening ratio can be made small, the fall of the short circuit tolerance of a semiconductor device can be suppressed effectively.
[B2] Each of the gate junction and the emitter junction is formed close to one side and the other side of the trench in a cross section perpendicular to the longitudinal direction of the trench. The semiconductor device according to B1, including a central insulating film interposed between the gate junction and the emitter junction.

[B3] The semiconductor device according to B2, wherein the gate junction and the emitter junction are each formed in a film shape along a side surface of the trench that is relatively close in relation to the other junction.
[B4] Each of the semiconductor devices is formed in the semiconductor layer and is connected to a gate contact trench connected to a side surface of the trench adjacent to the gate junction and an emitter contact connected to a side surface of the trench adjacent to the emitter junction. The semiconductor device according to B2 or B3, including a contact trench, wherein the gate contact trench and the emitter contact trench are formed with a narrower width than the trench.
According to this configuration, when the electrode materials of the gate junction and the emitter junction are deposited along the inner surface of the trench in order to obtain a configuration in which each junction is close to one and the other side surfaces of the trench, the trench In the narrower width gate contact trench and the emitter contact trench, the electrode materials deposited on one and the other side surfaces can be integrated inside the trench. As a result, the gate contact trench and the emitter contact trench can each be completely backfilled with the electrode material. Thereby, since the area of the electrode material when each contact trench is viewed from above in the depth direction is at least equal to the diameter (width) of each contact trench, contact can be easily made.
[B5] The trench is formed in an annular shape that defines an inner region in which the floating region is disposed and an outer region in which the FET structure is disposed, and the gate contact trench is formed from the annular trench. The semiconductor device according to B4, wherein the emitter trench is formed by being drawn out to the outer region, and the emitter trench is formed by being drawn from the annular trench to the inner region.

  [B6] The FET structure is formed in a plurality of stripes in a plan view as viewed from the normal direction of the surface of the semiconductor layer, and the annular trench is disposed in a region between adjacent FET structures. The gate contact trench and the emitter contact trench of the annular trench disposed in the region are respectively outward and opposite to each other from one end of the annular trench in the longitudinal direction of the stripe. The semiconductor device is formed so as to cross the gate contact trench around the active region where the stripe FET structure is formed, and is electrically connected to the gate junction. Gate fingers and above the active area spaced from the gate fingers. Wherein is formed so as to cover the emitter contact trench, it said and an emitter junction and electrically connected to the emitter electrode, the semiconductor device according to B5 in.

[B7] The semiconductor device according to any one of B1 to B6, wherein the floating region is formed to wrap around below the trench.
According to this configuration, since the floating region is formed so as to go under the trench, the collector-emitter voltage applied to the trench during the switching-off operation can be reduced. Therefore, it is possible to suppress the destruction of the device against a steep voltage change (dv / dt). Thereby, the short circuit tolerance of the semiconductor device can be maintained. In addition, the floating region deeper than the base region can improve the short-circuit withstand capability, but the base region may be shallow, so the channel length is shortened by appropriately designing the depth of the base region to suppress an increase in on-voltage. You can also
[B8] The semiconductor device includes a second trench formed in the semiconductor layer so as to reach at least the floating region, an insulating film provided in the second trench, and electrically connected to the emitter region. The semiconductor device according to any one of B1 to B6, further including a second emitter junction.

[B9] The semiconductor device according to B8, wherein the floating region is formed with the same depth as the base region, and the second trench is formed so as to penetrate the floating region.
[B10] The second trench is formed to have the same width as the trench, and the second emitter junction includes a pair of junctions insulated from each other in the second trench. The semiconductor device described.
According to this configuration, the second trench can be formed in the same process as the process of forming the trench only by changing the layout of the mask. Moreover, since the second trench is formed with the same width as the trench, the second emitter junction can be formed in the same step as the step of forming the gate junction and the emitter junction. As a result, the second trench and the second emitter junction can be formed without complicating the manufacturing process.
[B11] The semiconductor device according to B8 or B9, wherein the second trench is formed to have a narrower width than the trench, and the second emitter junction is embedded in the second trench as a single body. .

  With such a configuration, the second emitter junction can be formed in the same process as the process of forming the gate junction and the emitter junction.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Gate finger 4 Active region 6 Emitter electrode 8 FET structure 9 p-type floating region 10 Annular trench 11 Contact trench for gate 12 Contact trench for emitter 15 Semiconductor substrate 17 N ^- type drain region 18 Insulating film 19 Gate junction 20 Emitter junction 21 Central insulating film 28 P-type base region 31 n ⁺ -type emitter region 41 Semiconductor device 61 according to reference example 61 Semiconductor device 62 p-type floating region 63 Trench for emitter 64 Second emitter junction 81 Semiconductor device 83 Trench for emitter 84 Second emitter junction 91 Semiconductor device 101 Semiconductor device 102 Active region 103 Gate metal 105 Gate pad 106 Gate finger 107 Pad peripheral portion 110 First removal region DESCRIPTION OF SYMBOLS 11 2nd removal area | region 115 1st routing wiring 116 routing wiring for gate fingers 117 2nd routing wiring 125 Semiconductor substrate 132 MIS gate structure 148 Semiconductor device 151 Reference device semiconductor device 152 Gate metal 153 Gate pad 154 First gate finger 155 Second gate finger 156 Pad peripheral portion 157 Removal region 160 First lead wiring 161 Second lead wiring 167 Wiring portion 168 Wiring portion W _{1 to} W ₄ width

Claims (20)

A first conductivity type semiconductor layer having a front surface and a back surface;
A collector region of a second conductivity type formed in the surface layer portion of the back surface of the semiconductor layer;
An outer peripheral surface, an inner peripheral surface, and a bottom surface connecting the outer peripheral surface and the inner peripheral surface, each of the outer peripheral surfaces is formed on the surface of the semiconductor layer spaced from each other in a manner facing each other A plurality of annular trenches;
An insulating film formed on the inner surface of each trench;
A gate junction embedded in the outer peripheral surface side of each trench with the insulating film interposed therebetween;
An emitter junction embedded in the inner peripheral surface of each of the trenches and spaced from the gate junction and sandwiching the insulating film; and
A central insulating film interposed between the gate junction and the emitter junction in each of the trenches;
Formed in a region between the outer peripheral surfaces of the plurality of trenches adjacent to each other in the surface layer portion of the surface of the semiconductor layer, and with respect to the central portion of the trench or the central portion of the trench in the thickness direction of the semiconductor layer A second conductivity type base region having a bottom located on the surface side of the semiconductor layer;
An emitter region of a first conductivity type formed in a surface layer portion of the base region;
An electrically floating state is formed in a region surrounded by the inner peripheral surface of each trench in a surface layer portion of the surface of the semiconductor layer, and with respect to the bottom surface of the trench in the thickness direction of the semiconductor layer A second conductivity type floating region having a bottom located on the back side of the semiconductor layer;
An interlayer insulating film that selectively covers the surface of the semiconductor layer;
A surface gate electrode formed on the interlayer insulating film and electrically connected to the gate junction;
A semiconductor device comprising: a surface emitter electrode formed on the interlayer insulating film and electrically connected to the emitter junction and the emitter region.   The semiconductor device according to claim 1, wherein the floating region covers the bottom surface of the trench.   The semiconductor device according to claim 2, wherein the floating region is formed below the emitter junction and covers the bottom surface of the trench so as not to be formed below the gate junction.   The semiconductor device according to claim 1, wherein the gate junction is separated from the floating region via the emitter junction and a central insulating film.   The plurality of trenches are each formed in a rectangular ring shape extending in the first direction in a plan view, and are formed at intervals along a second direction intersecting the first direction. The semiconductor device according to any one of the above. The plurality of trenches each have one end on one side and the other end on the other side in the first direction,
The semiconductor device according to claim 5, wherein the surface gate electrode is electrically connected to the gate junction in a region on the one end portion side and a region on the other end portion side of each trench.   The surface gate electrode includes a gate pad formed on the interlayer insulating film, and a gate finger drawn from the gate pad onto the interlayer insulating film and electrically connected to the gate junction. The semiconductor device as described in any one of Claims 1-6.   The semiconductor device according to claim 7, wherein the plurality of trenches include the trench formed in a region overlapping with the gate pad in plan view. The gate finger is formed along the periphery of the semiconductor layer so as to partition an inner region of the semiconductor layer in a plan view.
The semiconductor device according to claim 7 or 8, wherein the plurality of trenches are respectively formed in regions partitioned by the gate fingers in plan view. The interlayer insulating film has a contact hole exposing the emitter region,
The semiconductor device according to claim 1, wherein the surface emitter electrode is electrically connected to the emitter region through the contact hole. A contact trench formed in a region between the outer peripheral surfaces of the plurality of adjacent trenches so as to expose the emitter region on the surface of the semiconductor layer;
The contact hole communicates with the contact trench;
The semiconductor device according to claim 10, wherein the surface emitter electrode is electrically connected to the emitter region through the contact hole and the contact trench.   The semiconductor device according to claim 11, wherein the contact trench is located on the surface side of the semiconductor layer with respect to a bottom portion of the base region.   The semiconductor device according to claim 11, further comprising a second conductivity type base contact region formed in a region along the contact trench in a surface layer portion of the base region. A contact emitter electrode embedded in the contact hole and electrically connected to the emitter region;
The semiconductor device according to claim 11, wherein the surface emitter electrode is electrically connected to the emitter region via the contact emitter electrode. The surface emitter electrode enters the contact hole from above the interlayer insulating film,
The semiconductor device according to claim 14, wherein the contact emitter electrode is formed by a portion of the surface emitter electrode located in the contact hole.   The semiconductor device according to claim 15, wherein the surface emitter electrode includes aluminum.   The semiconductor device according to claim 14, wherein the contact emitter electrode includes a conductive material different from that of the surface emitter electrode. The surface emitter electrode comprises aluminum;
The semiconductor device according to claim 17, wherein the contact emitter electrode includes tungsten. A buffer region of a first conductivity type formed in a surface layer portion of the back surface of the semiconductor layer;
The semiconductor device according to claim 1, wherein the collector region is formed in a surface layer portion on the back side of the semiconductor layer in the buffer region.   The width | variety of the said trench is a semiconductor device as described in any one of Claims 1-19 which is 1.5 micrometers or more and 3.0 micrometers or less.

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