JP2019087730A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device capable of improving avalanche resistance of an edge termination region.SOLUTION: In an edge termination region 2, a carrier extraction region 5 between an active region 1 and a gate runner portion 4 is provided with a p-type contact region 53 in a surface region of a p-type well region 51. In the carrier extraction region 5, each of a plurality of second contact holes 54 formed in an interlayer insulation film 21 is embedded with a contact plug 24 via a barrier metal 23, and formed with a contact 50 between the p-type contact region 53 and an emitter potential barrier metal 23. The contact region 50 of the carrier extraction region 5 is arranged in a stripe-like layout extending along an outer periphery of the active region 1, and surrounds a periphery of the active region 1. Contact resistance Ra of the contact 50 of the carrier extraction region 5 is higher than contact resistance Rb of a contact (emitter contact) 27 of a MOS gate 20.SELECTED DRAWING: Figure 4A

Description

  The present invention relates to a semiconductor device.

  Conventionally, a MOS type semiconductor device provided with a MOS gate (insulated gate having a three-layer structure of metal-oxide film-semiconductor) is known to have an active region and an edge termination region surrounding the periphery of the active region. is there. In the MOS semiconductor device, holes near the boundary between the edge termination region and the active region, which are minority carriers generated in the edge termination region when the MOS semiconductor device is turned off, are extracted to the front electrode Contacts (electrical contacts) are provided (see, for example, Patent Documents 1 to 4 below). In the following patent documents 1 to 4, one contact surrounding the periphery of the active region is formed by the contact region and the metal electrode.

  The structure of a conventional semiconductor device will be described by taking a trench gate type IGBT (Insulated Gate Bipolar Transistor) as an example. FIG. 10 is a cross-sectional view showing the structure of a conventional semiconductor device. FIG. 11 is a cross-sectional view showing the carrier extraction area of FIG. 10 in an enlarged manner. FIG. 12 is a plan view showing a layout in which a part of FIG. 10 is viewed from the front surface side of the semiconductor substrate (semiconductor chip). FIG. 10 shows a cross-sectional structure taken along line AA-AA 'in FIG. In FIG. 10, the MOS gate 120 and the carrier extraction region 105 of the active region 101 are shown in a simplified manner.

  FIG. 11 shows a cross-sectional structure of the contact 127 of the MOS gate 120 in the active region 101 and the contact 150 in the carrier extraction region 105. FIG. 12 shows a part of the edge termination area 102 surrounding the periphery of the active area 101 in a substantially rectangular shape (not shown). Further, in FIG. 12, contacts between the interlayer insulating film 121 (hatched portion) in the gate runner portion 104 and the carrier extraction region 105, the gate runner 142 (portion between the vertical broken lines) of the gate runner portion 104, and the carrier extraction region 105. The layout of 150 and 150 is shown, and each part of the active region 101 and the pressure | voltage resistant structure part 103 is not shown in figure.

  The conventional semiconductor device shown in FIGS. 10 to 12 is a vertical IGBT having an active region 101 and an edge termination region 102 on a semiconductor substrate 110. A trench gate MOS gate 120 is provided in the active region 101 on the front surface side of the semiconductor substrate 110, and a field limiting ring (FLR) 131 or a field plate 132 is provided in the edge termination region 102. And the like are provided. Hereinafter, the portion of the edge termination region 102 where the breakdown voltage structure 130 is disposed is referred to as a breakdown voltage structure part 103.

A gate runner 142 is provided on the front surface of the semiconductor substrate 110 between the active region 101 and the breakdown voltage structure portion 103 with an insulating layer 141 interposed therebetween. The gate runner 142 surrounds the periphery of the active region 101 in a substantially rectangular shape (not shown). Gate runner 142 is electrically connected to gate metal interconnection 144 at the gate potential in contact hole 143.
Further, gate electrodes 117 of all the MOS gates 120 are electrically connected to the gate runner 142. Hereinafter, the portion where the gate runner 142 is disposed in the edge termination region 102 is referred to as a gate runner portion 104.

A p-type well region 151 is provided in the surface layer of the front surface of the semiconductor substrate 110 from the boundary between the withstand voltage structure portion 103 and the gate runner portion 104 to the boundary between the active region 101 and the edge termination region 102. It is done. The pn junction between the p-type well region 151 and the n ⁻ -type drift region 111 is a main junction 152 transmitting the voltage at turn-off of the IGBT from the active region 101 to the edge termination region 102. In the surface region of the p-type well region 151 (the surface layer on the front surface of the semiconductor substrate 110), ap ⁺ -type contact region 153 is provided substantially over the entire surface between the active region 101 and the gate runner portion 104. There is. The p ⁺ -type contact region 153 surrounds the periphery of the active region 101 in a substantially rectangular shape (not shown).

Almost the entire surface of the p ⁺ -type contact region 153 is exposed to one contact hole 154 provided in the interlayer insulating film 121. An emitter electrode 122 extending from the active region 101 is embedded in the contact hole 154. Emitter electrode 122 is in contact with p ⁺ -type contact region 153 inside contact hole 154, and is electrically connected to p-type well region 151 via p ⁺ -type contact region 153. The emitter electrode 122 is, for example, an aluminum silicon (Al-Si) electrode mainly composed of aluminum. Reference numerals 112 and 113 denote a p-type base region and ap ⁺ -type contact region of the MOS gate 120, respectively. Reference numerals 108, 109 and 128 denote an n-type field stop region, ap ⁺ -type collector region and a collector electrode, respectively.

That is, one contact hole 154 exposing substantially the entire surface of the p ⁺ -type contact region 153 is provided between the active region 101 and the gate runner portion 104. One contact (electrical contact portion) 150 between the p ⁺ -type contact region 153 and the emitter electrode 122 is formed in the contact hole 154. The contact 150 surrounds the periphery of the active region 101 in a substantially rectangular shape (not shown). The contact 150 has a function of extracting holes, which are minority carriers generated in the edge termination region 102 when the IGBT is turned off, to the emitter electrode 122. Hereinafter, a portion of the edge termination region 102 where the contact 150 is disposed is referred to as a carrier extraction region 105. By providing the contact 150, the carrier accumulated in the edge termination region 102 at the time of switching is pulled out to prevent destruction.

Also, as an IGBT in which the behavior of minority carriers during operation is controlled, a device provided with an n-type carrier accumulation region having a higher impurity concentration than the n ⁻ -type drift region has been proposed (see, for example, Patent Documents 5 to 7 below) ). FIG. 19 is a cross-sectional view showing another structure of the conventional semiconductor device. FIG. 19 is FIG. 1 of Patent Document 5 below. In the conventional semiconductor device shown in FIG. 19, an IGBT element region 201 provided with an IGBT, a diode element region 202 provided with a diode, and a boundary region 203 between the IGBT element region 201 and the diode element region 202 are the same. The reverse conducting IGBT (RC-IGBT: Reverse Conducting IGBT) built in the semiconductor substrate 210 of FIG.

In the boundary region 203, a p-type well region 213 in contact with the p-type base region 211 of the IGBT and the p-type region 212 'of the diode is provided. The p-type region 212 ′ of the diode is fixed to the anode potential via the p ⁺ -type anode region 212. The p-type well region 213 of the boundary region 203 extends deeper from the main surface on the emitter side of the semiconductor substrate 210 to the collector side than the p-type base region 211 of the IGBT and the p-type region 212 'of the diode. The diode element region 202 is separated. First and second n-type carrier accumulation regions 221 and 222 of floating potential are provided in the p-type base region 211 of the IGBT and in the p-type well region 213 of the boundary region 203, respectively.

  The first n-type carrier accumulation region 221 is provided between the portion 211a on the emitter side and the portion 211b on the collector side of the p-type base region 211 of the IGBT, in contact with both the portions 211a and 211b. The second n-type carrier accumulation region 222 is provided at a predetermined depth inside the p-type well region 213 of the boundary region 203, and penetrates the p-type well region 213 in a direction parallel to the main surface of the semiconductor substrate 210. One end of the second n-type carrier accumulation region 222 extends toward the IGBT element region 201 until it contacts the first n-type carrier accumulation region 221 of the IGBT element region 201. The other end of the second n-type carrier accumulation region 222 reaches the inside of the p-type region 212 'of the diode. Reference numeral 204 is an edge termination area.

In the conventional RC-IGBT shown in FIG. 19, the hole density in the vicinity of the boundary between the n ^-- type drift region 214 and the p-type base region 211 is increased by the first n-type carrier storage region 221 during IGBT operation. In addition, the movement of holes from the n ⁻ -type drift region 214 of the IGBT element region 201 to the diode element region 202 is suppressed by the second n-type carrier accumulation region 222. This reduces the on-voltage of the IGBT. In addition, at the time of diode operation, accumulation of holes in the n ⁻ -type drift region 214 of the boundary region 203 is suppressed by the second n-type carrier accumulation region 222. For this reason, the reverse recovery current is reduced at the time of reverse recovery of the diode, and element breakdown at the time of reverse recovery of the diode is suppressed.

In Patent Document 6 below, an n-type carrier accumulation region is provided in each of the inside of the p-type base region of the IGBT in the active region and the inside of the p-type RESURF layer in the edge termination region. These n-type carrier accumulation regions extend in a direction parallel to the main surface of the semiconductor substrate at predetermined depths inside the p-type base region and the p-type resurf layer, respectively, and contact each other. The hole concentration in the p-type base region is increased by the n-type carrier accumulation region inside the p-type base region of the IGBT, and the on-voltage of the IGBT is reduced. The n-type carrier accumulation region inside the p-type RESURF layer suppresses charge imbalance between the n ^-- type drift region and the p-type RESURF layer at the time of avalanche generation, and the breakdown voltage fluctuation of the IGBT is suppressed small .

  In Patent Document 7 below, n-type carrier accumulation is performed in the inside of the p-type base region of the IGBT, the inside of the p-type anode region of the diode, and the inside of the breakdown voltage structure formed of the p-type diffusion region of the edge termination region. An area is provided. The n-type carrier accumulation region inside the p-type base region increases the hole concentration in the p-type base region and reduces the on-voltage of the IGBT. By the n-type carrier accumulation region inside the p-type anode region, the injection amount and discharge amount of holes in the diode region are equalized, and the recovery tolerance of the diode is increased. By the n-type carrier accumulation region inside the breakdown voltage structure, it is suppressed that the current flowing in the vicinity of the breakdown voltage structure becomes uneven at the time of recovery of the diode, and the breakdown due to current concentration is suppressed.

International Publication No. 2013/035818 Japanese Patent Application Publication No. 2009-532880 International Publication No. 2013/132568 JP, 2009-200098, A International Publication No. 2010/143288 JP, 2008-227237, A JP, 2013-021104, A

  In the above-described conventional semiconductor device (see FIGS. 10 and 11), when the width w101 of the edge termination region 102 is narrowed or the thickness t101 of the semiconductor substrate 110 is reduced, adjacent gate trenches (MOS gates 120 When the distance between the buried trenches is narrow, the breakdown voltage of the edge termination region 102 is lowered and easily lower than the breakdown voltage of the active region 101, so an avalanche current is generated in the edge termination region 102. Specifically, for example, the width w101 of the edge termination region 102 is about 300 μm or less, and the thickness t101 of the semiconductor substrate 110 is 80 μm or less.

When the width w 102 of the contact 150 in the carrier extraction region 105 is increased to avoid such a problem, the contact resistance Ra ′ of the contact 150 in the carrier extraction region 105 is the n ⁺ type of the MOS gate 120 in the active region 101. Emitter area (not shown)
And the contact resistance Rb ′ of the contact 127 between the p ⁺ -type contact region 113 and the emitter electrode 122. Therefore, a hole current (open arrow: avalanche current) 160 generated at the edge termination region 102 and flowing toward the active region 101 at the turn-off time of the IGBT is drawn from the p-type well region 151 to the emitter electrode 122 The current is easily concentrated near the boundary between the gate runner 142 and the contact hole (hereinafter referred to as a current extracting portion) 154 serving as a current extracting portion.

  When the hole current 160 generated in the edge termination region 102 is concentrated in the vicinity of the boundary between the gate runner 142 and the current extracting portion 154, the avalanche resistance of the entire device tends to be reduced. For example, when moving an inductive load (L load) such as a motor by alternately turning on and off two IGBTs constituting a bridge circuit, a transient voltage due to an inductance component of the inductive load is applied to the turned-off IGBT. Therefore, the hole current 160 generated in the edge termination region 102 is concentrated in the vicinity of the boundary between the gate runner 142 and the current extracting portion 154, and the current is concentrated in the carrier extracting region 105 and the IGBT is broken.

  Further, when the two IGBTs constituting the bridge circuit are both turned on, the short circuit current flowing through the IGBTs is five to eight times the rated current. Therefore, the current change rate di / dt of the IGBT becomes high, and when the short circuit current is cut off, the voltage value of the surge voltage applied to the IGBT tends to jump up. This surge voltage causes the IGBT to self-clamp and turn off, and the avalanche state continues, whereby the hole current 160 generated in the edge termination region 102 is concentrated near the boundary between the gate runner 142 and the current extracting portion 154, and the carrier extracting region At 105, the IGBT is destroyed.

  An object of the present invention is to provide a semiconductor device capable of improving the avalanche resistance of an edge termination region in order to solve the above-mentioned problems of the prior art.

  In order to solve the problems described above and achieve the object of the present invention, a semiconductor device according to the present invention has the following features. An active region through which a main current flows is provided on a semiconductor substrate of the first conductivity type. The termination region surrounds the periphery of the active region. In the active region, a first semiconductor region of a second conductivity type is provided in the surface layer on the first main surface side of the semiconductor substrate. A second semiconductor region of the first conductivity type is selectively provided in the first semiconductor region. A third semiconductor region of the second conductivity type is selectively provided in the first semiconductor region. The third semiconductor region has a higher impurity concentration than the first semiconductor region. In the termination region, a fourth semiconductor region of the second conductivity type is selectively provided in the surface layer on the first main surface side of the semiconductor substrate. The fifth semiconductor region of the first conductivity type is a region of the semiconductor substrate other than the first semiconductor region and the fourth semiconductor region. The gate insulating film is provided in contact with a region of the first semiconductor region between the fifth semiconductor region and the second semiconductor region. The gate electrode is provided on the opposite side of the first semiconductor region with the gate insulating film interposed therebetween. An interlayer insulating film is provided on the first main surface of the semiconductor substrate. The interlayer insulating film covers the second semiconductor region, the third semiconductor region, the fourth semiconductor region, and the gate electrode. A first contact hole is opened in the interlayer insulating film to expose the second semiconductor region and the third semiconductor region. The plurality of second contact holes are opened in the interlayer insulating film, and selectively expose the fourth semiconductor regions. The first metal film is provided along the inner wall of the second contact hole. The first metal film has high adhesion to the semiconductor substrate and is in ohmic contact with the semiconductor substrate. The second metal film is embedded on the first metal film inside the second contact hole. The first electrode is provided on the interlayer insulating film. The first electrode is electrically connected to the first semiconductor region through the second semiconductor region and the third semiconductor region in the first contact hole, and the second metal film in the second contact hole And electrically connected to the fourth semiconductor region via the first metal film. The second electrode is provided on the second main surface of the semiconductor substrate.

  In the semiconductor device according to the present invention, in the semiconductor device according to the above-mentioned invention, a sixth semiconductor region of a second conductivity type, which is selectively provided inside the fourth semiconductor region, has a higher impurity concentration than the third semiconductor region. Further comprising The first electrode is electrically connected to the fourth semiconductor region through the second metal film, the first metal film, and the sixth semiconductor region in the second contact hole. .

  In the semiconductor device according to the present invention, in the semiconductor device according to the above-described invention, a seventh semiconductor region of a second conductivity type, which is selectively provided inside the third semiconductor region, has a higher impurity concentration than the third semiconductor region. Further comprising The first electrode is electrically connected to the first semiconductor region through the seventh semiconductor region and the third semiconductor region in the first contact hole.

  In the semiconductor device according to the present invention, in the above-described invention, the fourth semiconductor region surrounds the periphery of the active region along the outer periphery of the active region. The plurality of second contact holes may be disposed in a stripe-like layout extending along the outer periphery of the active region, and may surround the periphery of the active region.

  The semiconductor device according to the present invention is characterized in that, in the above-described invention, the width of the second contact hole is 0.3 μm or more and 1.0 μm or less.

  The semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the width between the adjacent second contact holes is the same as the width of the second contact holes.

  In the semiconductor device according to the present invention, in the above-described invention, the semiconductor device according to the present invention is provided on the first main surface of the semiconductor substrate via an insulating layer in the termination region, and sandwiching the insulating layer in the depth direction. The semiconductor device further includes a gate pad facing the four semiconductor regions. The gate electrode is electrically connected to the gate pad. The plurality of second contact holes are provided between the boundary between the active region and the termination region and the gate pad.

  The semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the distance from the boundary between the active region and the termination region to the gate pad is 5 μm or more.

  In the semiconductor device according to the present invention as set forth above, the first electrode is in ohmic contact with the second semiconductor region and the third semiconductor region.

  In the semiconductor device according to the present invention, in the above-mentioned invention, the first metal film is provided along the inner wall of the first contact hole. The second metal film may be embedded on the first metal film inside the first contact hole.

  A semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the first metal film contains titanium as a main component.

  A semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the second metal film contains tungsten as a main component.

  In the semiconductor device according to the present invention, in the above-described invention, the semiconductor device further includes a trench extending from the upper surface of the first semiconductor region to the fifth semiconductor region. The gate insulating film is provided along the inner wall of the trench. The gate electrode is embedded inside the gate insulating film inside the trench.

  In the semiconductor device according to the present invention, in the semiconductor device according to the above-mentioned invention, an eighth semiconductor of a first conductivity type having a higher impurity concentration than the fifth semiconductor region between the first semiconductor region and the fifth semiconductor region. It further features an area.

  In the semiconductor device according to the present invention, in the above-described invention, the semiconductor device faces the second contact hole in a depth direction away from the first main surface of the semiconductor substrate in the fourth semiconductor region. The semiconductor device may further include a ninth semiconductor region of a first conductivity type having an impurity concentration higher than that of the fifth semiconductor region.

  In the semiconductor device according to the present invention, in the above-described invention, the semiconductor device according to the present invention is provided on the first main surface of the semiconductor substrate via an insulating layer in the termination region, and sandwiching the insulating layer in the depth direction. The semiconductor device further includes a gate pad facing the semiconductor region, the gate electrode being electrically connected. The ninth semiconductor region extends from the active region side to the gate pad side, and is terminated on the active region side with respect to the gate pad.

  The semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the ninth semiconductor region is located at the same depth from the first main surface of the semiconductor substrate as the eighth semiconductor region.

  The semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the ninth semiconductor region is located at a depth shallower than the first main surface of the semiconductor substrate than the eighth semiconductor region.

  In the semiconductor device according to the present invention, in the above-described invention, the semiconductor device further includes a trench extending from the upper surface of the first semiconductor region to the fifth semiconductor region. The gate insulating film is provided along the inner wall of the trench. The gate electrode is embedded inside the gate insulating film inside the trench. The trenches are arranged in stripes extending in a direction parallel to the first major surface of the semiconductor substrate. The second semiconductor region is provided between all the adjacent trenches.

  According to the invention described above, the contact resistance of the contact (electrical contact portion) between the fourth semiconductor region of the termination region and the first electrode is set to the third semiconductor region (second conductivity type contact region) of the MOS gate of the active region. It can be higher than the contact resistance of the contact with the first electrode. Therefore, when the MOS gate type semiconductor device is turned off, the hole current generated in the termination region and flowing toward the active region can be mainly extracted from the contact of the MOS gate in the active region to the first electrode. Accordingly, it is possible to suppress concentration of the hole current generated in the termination region at the time of turn-off of the MOS gate type semiconductor device in the fourth semiconductor region having the potential of the first electrode in the termination region.

  According to the semiconductor device of the present invention, the avalanche withstand capability of the edge termination region of the IGBT can be improved.

FIG. 1 is a plan view showing a layout of a semiconductor device according to a first embodiment viewed from the front surface side of a semiconductor substrate (semiconductor chip). It is a top view which expands and shows a part of FIG. FIG. 1 is a cross-sectional view showing a structure of a semiconductor device according to a first embodiment. It is sectional drawing which expands and shows the carrier extraction area | region of FIG. It is sectional drawing which expands and shows the carrier extraction area | region of FIG. It is sectional drawing which expands and shows the carrier extraction area | region of FIG. It is sectional drawing which expands and shows the carrier extraction area | region of FIG. FIG. 6 is an explanatory view showing a flow of hole current at turn-off of the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing a structure of a semiconductor device according to a second embodiment. It is a characteristic view showing the relation between temperature and avalanche capacity. It is sectional drawing which shows the structure of the conventional semiconductor device. It is sectional drawing which expands and shows the carrier extraction area | region of FIG. FIG. 11 is a plan view showing a layout in which a part of FIG. 10 is viewed from the front surface side of the semiconductor substrate. FIG. 7 is a cross-sectional view showing a structure of a semiconductor device according to a third embodiment. FIG. 16 is a cross-sectional view showing the structure of the semiconductor device according to Fourth Embodiment; FIG. 16 is a cross-sectional view showing the structure of the semiconductor device according to Fourth Embodiment; FIG. 18 is a plan view showing a layout of the semiconductor device according to the fourth embodiment as viewed from the front surface side of a semiconductor substrate. FIG. 18 is a cross-sectional view showing a structure of a semiconductor device according to a fifth embodiment. FIG. 18 is a cross-sectional view showing a structure of a semiconductor device according to a sixth embodiment. FIG. 20 is a cross-sectional view showing another structure of the conventional semiconductor device.

  Hereinafter, preferred embodiments of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, in the layer or region having n or p, it is meant that electrons or holes are majority carriers, respectively. Further, + and-attached to n and p mean that the impurity concentration is higher and the impurity concentration is lower than that of the layer or region to which it is not attached, respectively. In the following description of the embodiments and the accompanying drawings, the same components are denoted by the same reference numerals and redundant description will be omitted.

Embodiment 1
The structure of the semiconductor device according to the first embodiment will be described by taking a trench gate type IGBT as an example. FIG. 1 is a plan view showing a layout of the semiconductor device according to the first embodiment as viewed from the front surface side of a semiconductor substrate (semiconductor chip). FIG. 2 is a plan view showing a part of FIG. 1 in an enlarged manner. FIG. 3 is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment. 4A, 4B, 5 and 6 are enlarged cross-sectional views of the carrier drawing area of FIG. FIG. 7 is an explanatory view showing the flow of hole current (avalanche current) at turn-off of the semiconductor device according to the first embodiment.

  FIG. 2 is a portion surrounded by the rectangular frame A in FIG. 1, and shows a part of each of the active region 1 and the edge termination region 2 from near the boundary between the active region 1 and the edge termination region 2 from the chip end . In FIG. 2, the interlayer insulating film 21 (hatched portion) in the gate runner portion 4 and the carrier extraction region 5, the gate runner 42 (portion between the vertical broken lines) of the gate runner portion 4 and the contact (electrically) of the carrier extraction region 5 The layout of the contact portion 50) is shown.

  Further, in FIG. 2, the respective portions of the active region 1 and the withstand voltage structure portion 3 and the electrode pad (emitter electrode (first electrode) 25) and the polyimide protective film 26 in the gate runner portion 4 and the carrier extraction region 5 are not shown. Do. The cutting lines B-B 'and C-C' in FIG. 2 are cutting lines passing through the gate insulating film 16 and the gate electrode 17 provided in each of the plurality of trenches 15.

Specifically, for example, when the trenches 15 are arranged in stripes extending in a direction (hereinafter, referred to as a first direction) X parallel to the front surface of the semiconductor substrate 10, the cutting line B-B in FIG. The 'and the cutting line CC' are cutting lines parallel to the front surface of the semiconductor substrate 10 and in a direction (hereinafter, referred to as a second direction) Y orthogonal to the first direction X. Further, the cutting line B-B 'in FIG. 2 is a cutting line not passing through the n ⁺ -type emitter region 29, and the cutting line C-C' is a cutting line passing through the n ⁺ -type emitter region 29.

For example, it is assumed that the trenches 15 are arranged in stripes extending in the first direction X, and the n ⁺ -type emitter regions 29 and the p ⁺ -type contact regions 13 are alternately repeatedly arranged in the first direction X. In this case, the cross-sectional structure along the cutting line BB 'in FIG. 2 and the cross-sectional structure along the cutting line CC' are alternately and repeatedly arranged in the first direction X. In FIG. 3, each cross-sectional structure in cutting-plane line BB 'of FIG. 2 and cutting-plane line CC' is shown. Further, FIG. 3 shows the MOS gate 20 and the carrier extraction region 5 of the active region 1 in a simplified manner.

  In FIG. 4A and 4B, the carrier extraction area | region of FIG. 3 is expanded and shown. That is, FIG. 4A is a part of the cross-sectional structure along the cutting line B-B 'of FIG. FIG. 4B is a part of the cross-sectional structure taken along line C-C 'in FIG. 5 and 6 show another example of part of the cross-sectional structure taken along the line B-B 'of FIG. That is, FIGS. 5 and 6 show another example different from the cross-sectional structure of the carrier extraction region 5 of FIG. 4A.

Figure 1～3,4A, the semiconductor device according to the first embodiment shown in 4B is, n ^- -type a drift region (fifth semiconductor region) 11 n ^- active region 1 type semiconductor substrate 10 and of the edge termination region 2 It is a vertical IGBT having When the IGBT has a breakdown voltage of 600 V, the thickness t1 of the semiconductor substrate 10 may be, for example, about 60 μm to 80 μm. The active region 1 has, for example, a substantially rectangular planar shape, and is provided at the central portion of the semiconductor substrate 10. The active region 1 is a region through which a main current flows when the element (IGBT) is in an on state.

In the active region 1, one or more general trench gate MOS gates 20 are provided on the front surface side of the semiconductor substrate 10. One MOS gate 20 constitutes one unit cell (constituent unit of elements) of the IGBT. The MOS gate 20 includes a p-type base region (first semiconductor region) 12, an n ⁺ -type emitter region (second semiconductor region) 29, a p ⁺ -type contact region (third semiconductor region) 13, a trench 15, and a gate insulating film 16. And the gate electrode 17.

The p-type base region 12 is provided on the surface layer on the front surface of the semiconductor substrate 10 over the entire active region 1. The depth d1 of the p-type base region 12 may be, for example, about 2 μm to 3 μm. A portion of the semiconductor substrate 10 other than the p-type base region 12, the p ⁺ -type collector region 19 described later, the field limiting ring 31 and the n ⁺ -type stopper region 35 is the n ⁻ -type drift region 11.

The n ⁺ -type emitter region 29 and the p ⁺ -type contact region 13 are selectively provided on the surface region of the p-type base region 12 (surface layer on the front surface of the semiconductor substrate 10). The n ⁺ -type emitter region 29 may be opposed to the gate electrode 17 with the gate insulating film 16 on the side wall of the trench 15 interposed therebetween, and the arrangement can be variously changed. For example, when the trenches 15 are arranged in stripes extending in the first direction X, the n ⁺ -type emitter regions 29 and the p ⁺ -type contact regions 13 may be alternately repeatedly arranged in the first direction X. The portion where the n ⁺ -type emitter region 29 is disposed is shown in FIG. 4B (also in FIG. 17).

In a portion of active region 1 close to carrier extraction region 5, p ⁺ -type contact region 13 (a p ⁺ -type contact region 13 and a p ⁺⁺ -type surface in FIGS. Only the implantation region 14) is provided, and the n ⁺ -type emitter region 29 is not provided. The portion of active region 1 close to carrier extraction region 5 is, for example, when trenches 15 are arranged in a stripe extending in the first direction X, both ends of adjacent trenches 15 (mesa region) in the first direction X They are several mesa regions arranged in the vicinity of the portion and at the outermost side in a direction (second direction Y) orthogonal to the first direction X.

That is, when the trenches 15 are arranged in a stripe shape extending in the first direction X, the surface region of the p-type base region 12 is p in the several mesa regions arranged on the outermost side in the second direction Y. Only the ⁺ type contact region 13 and the p ⁺⁺ type surface implantation region 14 extend in the first direction X. In the remaining mesa regions other than the several mesa regions arranged outermost in the second direction Y, only the p ⁺ -type contact region 13 and the p ⁺⁺ -type surface implantation region 14 near both ends in the first direction X Extends in the first direction X, and an n ⁺ -type emitter region 29 is provided in a portion closer to the central portion in the first direction X than near both ends in the first direction X (FIG. 4B).

The reason why the n ⁺ -type emitter region 29 is not provided in the portion near the carrier extraction region 5 of the active region 1 is the following two points. One reason is that when forming the ion implantation mask for forming the n ⁺ -type emitter region 29, the gate formed on the front surface of the semiconductor substrate 10 prior to the ion implantation mask. The polysilicon layer of the runner 42 or the like causes irregularities in the ion implantation mask. The unevenness of the mask for ion implantation may cause variations in the layout of the n ⁺ -type emitter region 29 in a portion close to the polysilicon layer. The second reason is that the contact of the mesa region in which the n ⁺ -type emitter region 29 of the active region 1 is not provided can be made to function in the same manner as the contact 50 of the carrier extraction region 5. It is because it can control.

The depth d21 of the p ⁺ -type contact region 13 is preferably as shallow as about 0.4 μm to 0.6 μm, for example. The reason is that, generally, as the depth d21 of the p ⁺ -type contact region 13 is made smaller, the impurity concentration of the p ⁺ -type contact region 13 has a peak value (maximum value) nearer to the front surface of the semiconductor substrate 10 To reduce the contact resistance Rb (see FIG. 7 described later) of the contact 27 between the p ⁺ -type contact regions 13 and 61 of the active region 1 and the barrier metal (first metal film) 23 to a predetermined resistance value. It is easy to secure

When the depth d21 'of the p ⁺ -type contact region 13' exceeds about 0.6 μm, for example, about 1.0 μm (FIG. 5), the depth d21 'of the p ⁺ -type contact region 13' is about 0.6 μm As compared with the case, the impurity concentration of the p ⁺ -type contact region 13 exhibits a peak value at a position deep from the front surface of the semiconductor substrate 10. In addition, the peak value of the impurity concentration of the p ⁺ -type contact region 13 is lower than when the depth d 21 ′ of the p ⁺ -type contact region 13 ′ is about 0.6 μm.

That is, when the depth d21 'of the p ⁺ -type contact region 13' is more than 0.6 μm, there is a possibility that the predetermined contact resistance Rb of the p ⁺ -type contact region 13 'can not be obtained. In addition, there is a possibility that the latch-up tolerance of the active region 1 is reduced. Therefore, the p ^{+ +} type region (hereinafter referred to as the p ⁺⁺ type surface implantation region (seventh semiconductor region) and the p ^{+ +} type region (hereinafter referred to as the seventh semiconductor region) ) Is preferably provided (FIG. 5). Thus, the p-type impurity concentration in the surface region of the p ⁺ -type contact region 13 ′ can be increased.

The p ⁺⁺ -type surface implantation region 14 is formed, for example, as follows. In the interlayer insulating film 21, a contact hole 22 which penetrates the interlayer insulating film 21 in the depth direction Z and reaches the front surface of the semiconductor substrate 10 is formed. The depth direction Z is a direction from the front surface to the back surface of the semiconductor substrate 10. Then, a p-type impurity such as boron difluoride (BF ₂ ) is ion-implanted into the surface region of the p ⁺ -type contact region 13 ′ from the contact hole 22 of the interlayer insulating film 21 to a high impurity concentration. Thereafter, the ion-implanted p-type impurity is activated, for example, by heat treatment at about 600 ° C. to 900 ° C. without being substantially diffused. In this manner, a shallow p ⁺⁺ -type surface implantation region 14 can be formed in the surface region of the p ⁺ -type contact region 13 '.

Adjacent p ⁺⁺ -type surface implantation regions 14 may be in contact with each other. Also, even when the depth d21 of the p ⁺ -type contact region 13 is as shallow as about 0.6 μm (FIG. 4), the p ⁺⁺ -type surface implantation region 14 may be provided inside the p ⁺ -type contact region 13.

By providing the p ⁺⁺ -type surface implantation region 14, a predetermined contact resistance Rb of the contact 27 of the MOS gate 20 in the active region 1 and a predetermined latch-up resistance of the active region 1 can be secured. Instead of the p ⁺ -type contact region 13, 13 ', to each only partially p ⁺ -type contact region 61 exposed in the contact holes 22 of the p-type base region 12 may be provided, further, the p ⁺ A p ⁺⁺ -type surface implantation region 62 may be provided inside the mold contact region 61 (FIG. 6).

Trench 15 penetrates n ⁺ -type emitter region 29 and p-type base region 12 to reach n ⁻ -type drift region 11. The trenches 15 may be provided in a stripe-like layout extending in a direction (first direction X) parallel to the front surface of the semiconductor substrate 10 or the matrix viewed from the front surface side of the semiconductor substrate 10. It may be provided in the shape layout. The gate electrode 17 is provided inside the trench 15 via the gate insulating film 16. The depth d2 of the trench 15 may be, for example, about 3 μm to 8 μm.

An n-type field stop region 18 may be provided from the active region 1 to the edge termination region 2 on the p ⁺ -type collector region 19 side inside the n ⁻ -type drift region 11. n-type field stop region 18, p-type base region 12 and n when IGBT off ^- to reach the type depletion layer extending into the p ⁺ -type collector region 19 side from the pn junction between the drift region 11 is p ⁺ -type collector region 19 Have the function of suppressing

The n-type field stop region 18 may be disposed at a position deeper than the p ⁺ -type collector region 19 from the back surface of the semiconductor substrate 10 and may be in contact with the p ⁺ -type collector region 19. Also, a plurality of n-type field stop regions 18 may be arranged at different depths from the back surface of the semiconductor substrate 10. FIG. 3 shows the case where one n-type field stop region 18 deep from the back surface of the semiconductor substrate 10 is disposed.

The interlayer insulating film 21 is provided over the entire front surface of the semiconductor substrate 10 so as to cover the gate electrode 17, the gate runner 42 described later, and the polysilicon electrode 33. The interlayer insulating film 21 is provided with a contact hole 22 exposing the n ⁺ -type emitter region 29 and the p ⁺ -type contact region 13. The contact hole 22 is provided to slightly remove the semiconductor portion (silicon (Si) portion, that is, the semiconductor substrate 10) and to project from the interface between the interlayer insulating film 21 and the semiconductor substrate 10 to the semiconductor substrate 10 side. It is also good.

  A barrier metal 23 is provided along the inner wall of the contact hole 22 (the side surface of the interlayer insulating film 21 and the front surface of the semiconductor substrate 10) from the surface of the interlayer insulating film 21. The barrier metal 23 is made of a metal having high adhesion to the semiconductor portion and in ohmic contact with the semiconductor portion. Specifically, the barrier metal 23 may be, for example, a titanium (Ti) film, or may be a metal laminated film in which a titanium film and a titanium nitride (TiN) film are sequentially laminated.

A contact plug (second metal film) 24 is provided on the barrier metal 23 so as to fill the inside of the contact hole 22. The contact plug 24 is, for example, a metal film made of tungsten (W) having high embeddability. Emitter electrode 25 is provided on the entire front surface of semiconductor substrate 10 in active region 1. Emitter electrode 25 is electrically connected to n ⁺ -type emitter region 29 and p ⁺ -type contact region 13 via contact plug 24 and barrier metal 23, and to p-type base region 12 via p ⁺ -type contact region 13. It is electrically connected.

  Thus, by forming an electrode structure in which the emitter electrode 25 and the semiconductor portion are electrically connected through the contact plug 24 and the barrier metal 23 embedded in the contact hole 22, the trench pitch (the interval at which the trench 15 is disposed) ) Can be narrowed. The emitter electrode 25 extends to the carrier extraction region 5 as described later. Emitter electrode 25 is electrically insulated from gate electrode 17 by interlayer insulating film 21.

The emitter electrode 25 is, for example, an aluminum silicon (Al-Si) electrode mainly composed of aluminum. In the surface layer on the back surface of the semiconductor substrate 10, ap ⁺ -type collector region 19 is provided with a uniform thickness from the active region 1 to the edge termination region 2. The collector electrode (second electrode) 28 is provided on the entire back surface of the back surface of the semiconductor substrate 10 and is electrically connected to the p ⁺ -type collector region 19.

  The edge termination region 2 is a region between the active region 1 and the side surface (tip end) of the semiconductor substrate 10, and is disposed so as to surround the periphery of the active region 1. The edge termination region 2 adjusts the electric field so as to expand the depletion layer extending from the active region 1 to the edge termination region 2 and maintains the breakdown voltage of the entire device. The breakdown voltage is a voltage when an avalanche current is generated. The width w1 of the edge termination region 2 may be, for example, about 200 μm to 300 μm or less.

The edge termination region 2 is provided with a pressure resistant structure 30. Here, although the case where the field limiting ring 31, the field plate 32, the n ⁺ -type stopper region 35, and the stopper electrode 37 are provided as the pressure resistant structure 30 is described as an example, the present invention is not limited thereto. It is possible to change variously according to. Hereinafter, a portion of the edge termination region 2 where the withstand voltage structure 30 is disposed is referred to as a withstand voltage structure portion 3.

  The breakdown voltage structure portion 3 is a region from the end portion (chip end portion side) end of the p-type well region (fourth semiconductor region) 51 described later to the chip end portion. A plurality of field limiting rings 31 are floating (potentially floating) p-type regions, and a plurality of field limiting rings 31 are provided separately in the surface layer of the front surface of the semiconductor substrate 10 in the breakdown voltage structure portion 3. The plurality of field limiting rings 31 are provided apart from the p-type well region 51, and surround the periphery of the p-type well region 51 in a substantially rectangular shape along the outer periphery of the p-type well region 51.

In the pressure resistant structure 3, the n ⁺ -type stopper region 35 is selectively formed on the surface layer on the front surface of the semiconductor substrate 10 outside the field limiting ring 31 and away from the field limiting ring 31. Provided in The n ⁺ -type stopper region 35 surrounds the periphery of the field limiting ring 31 in a substantially rectangular shape along the outer periphery of the substantially outermost field limiting ring 31. The n ⁺ -type stopper region 35 is exposed at the tip end.

For example, polysilicon (poly-Si) electrodes 33 may be provided on the field limiting rings 31 separately from each other. The polysilicon electrode 33 may be formed, for example, by leaving a part of the polysilicon layer deposited on the semiconductor substrate 10 to form the gate runner 42. The polysilicon electrode 33 and the n ⁺ -type stopper region 35 are covered with the interlayer insulating film 21 and a part thereof is exposed to each contact hole provided in the interlayer insulating film 21.

  In each of the contact holes of the interlayer insulating film 21 in the breakdown voltage structure portion 3, a barrier metal and a contact plug may be provided, for example, similarly to the barrier metal 23 and the contact plug 24 of the active region 1 (barrier Collectively, the metal and the contact plug are attached with reference numeral 34). The barrier metal and the contact plug of the pressure resistant structure 3 may be formed simultaneously with, for example, the barrier metal 23 and the contact plug 24 of the active region 1, respectively.

  A field plate 32 which is a floating metal film is electrically connected to each of the field limiting rings 31 via, for example, a polysilicon electrode 33, a barrier metal and a contact plug. Each field plate 32 surrounds the periphery of the p-type well region 51 in a substantially rectangular shape along the field limiting ring 31 electrically connected to itself.

A stopper electrode 37 is electrically connected to the n ⁺ -type stopper region 35 via a barrier metal and a contact plug (the barrier metal and the contact plug are collectively denoted by reference numeral 36). The stopper electrode 37 is provided apart from the field plate 32 and fixed to the potential of the collector electrode 28. Further, the stopper electrode 37 surrounds the periphery of the outermost field limiting ring 31 in a substantially rectangular shape as in the n ⁺ -type stopper region 35.

A gate runner 42 made of, for example, polysilicon is provided between the active region 1 and the breakdown voltage structure 3 on the front surface of the semiconductor substrate 10 with the insulating layer 41 interposed therebetween. The gate runners 17 are electrically connected to the gate electrodes 17 of all the MOS gates 20.
Hereinafter, a portion of the edge termination region 2 where the gate runner 42 is disposed is referred to as a gate runner portion 4. The gate runner portion 4 is a region from the end on the inner side (the active region 1 side) of the gate runner 42 to the end on the outer side of the p-type well region 51.

The gate runner 42 is electrically insulated from the semiconductor substrate 10 by the insulating layer 41.
For example, when the gate insulating film 16 of the MOS gate 20 is formed, the gate insulating film 16 may be partially left in the gate runner portion 4 to form the insulating layer 41. The gate runner 42 surrounds the periphery of the active region 1 in a substantially rectangular shape along the outer periphery of the active region 1. Gate runner 42 is electrically insulated from barrier metal 23 in active region 1, contact plug 24 and emitter electrode 25 by interlayer insulating film 21.

  The gate runner 42 is exposed to a contact hole 45 provided in the interlayer insulating film 21 of the gate runner portion 4. The contact hole 45 exposing the gate runner 42 may be provided with a barrier metal and a contact plug similarly to, for example, the barrier metal 23 and the contact plug 24 of the active region 1 (collectively the barrier metal and the contact plug) Code 43 is attached. The barrier metal and the contact plug of the gate runner portion 4 may be formed simultaneously with, for example, the barrier metal 23 and the contact plug 24 of the active region 1, respectively.

In the gate runner 42, a barrier metal and a contact plug (layer indicated by reference numeral 43)
The gate metal interconnection 44 of the gate potential is electrically connected through The gate metal interconnection 44 is disposed apart from the emitter electrode 25. Although the case where gate metal wiring 44 is arrange | positioned so that the gate runner 42 may be electrically connected to the gate runner part 4 is shown in FIG. 3, arrangement | positioning of the gate metal wiring 44 can be variously changed. For example, although not shown in FIG. 1, the gate metal interconnection 44 may be arranged to surround the active region 1.

  Further, the gate runner 42 is electrically connected to a gate pad 46 (not shown in FIG. 3) at a gate potential at a portion not shown. The gate pad 46 has, for example, a substantially rectangular planar shape and is disposed apart from the emitter electrode 25 (FIG. 1). The emitter electrode 25 is not shown in FIG. Further, FIG. 1 shows the case where the gate pad 46 is disposed so as to extend from the active region 1 to the carrier extraction region 5, the gate pad 46 may be, for example, the center of the active region 1 or the end of the active region 1 Or at the corner of the active region 1.

A p-type well region 51 is provided in the surface layer of the front surface of the semiconductor substrate 10 from the boundary between the breakdown voltage structure portion 3 and the gate runner portion 4 to the boundary between the active region 1 and the edge termination region 2. There is. The p-type well region 51 may be in contact with the outer sidewall of the trench 15 arranged outermost in the active region 1. In addition, p type well region 51 may be provided in contact with the outer sidewall of trench 15 arranged outermost in active region 1 and between trench 15 arranged outermost and adjacent trench 15. . The p-type well region 51 surrounds the periphery of the active region 1 in a substantially rectangular shape along the outer periphery of the active region 1. The pn junction between the p-type well region 51 and the n ⁻ -type drift region 11 is a main junction 52 that transmits the voltage at turn-off of the IGBT from the active region 1 to the edge termination region 2.

  The depth d 3 of the p-type well region 51 is deeper than the depth d 1 of the p-type base region 12. Also, the depth d3 of the p-type well region 51 may be deeper than the depth d2 of the trench 15. Specifically, the depth d3 of the p-type well region 51 may be, for example, 3 μm or more at the deepest portion. The reason is that the present invention is applied to two IGBTs constituting a bridge circuit, and an inductive load (L load) such as a motor can be moved by alternately turning on / off the two IGBTs. This is because current concentration in the carrier extraction region 5 described later due to the inductance component of L load) can be suppressed.

In the surface region of the p-type well region 51 (the surface layer on the front surface of the semiconductor substrate 10), the p ⁺ -type contact region 53 is provided substantially over the entire surface between the active region 1 and the gate runner portion 4 (See Figures 4A and 4B). The p ⁺ -type contact region 53 is in contact with the outer sidewall of the trench 15 arranged outermost in the active region 1. The p ⁺ -type contact region 53 surrounds the periphery of the active region 1 in a substantially rectangular shape (not shown). The depth d22 of the p ⁺ -type contact region 53 is preferably shallow, for example, about 0.4 μm to 0.6 μm. The reason is as follows.

The p ⁺ -type contact region 53 is formed simultaneously with, for example, the p ⁺ -type contact region 13 of the active region 1. In this case, the depth d22 of the p ⁺ -type contact region 53 is substantially the same as the depth d21 of the p ⁺ -type contact region 13 of the active region 1. Therefore, when the depth d22 of the p ⁺ -type contact region 53 is more than 0.6 μm, the depth d21 of the p ⁺ -type contact region 13 of the active region 1 is also more than 0.6 μm. As a result, when the depth of the p ⁺ -type contact region 13 in the active region 1 is reduced according to the depth of the p ⁺ -type contact region 53, the extraction of the hole current in the p ⁺ -type contact region 13 in the active region 1 is weakened. This is because there is a possibility that the latch-up tolerance of the active region 1 may be reduced as described above.

Further, the p ⁺⁺ -type surface implantation region is not provided inside the p ⁺ -type contact region 53. That is, by setting the depth d21 'of the p ⁺ -type contact region 13' of the active region 1 to more than 0.6 μm, even when the depth d22 'of the p ⁺ -type contact region 53' becomes more than 0.6 μm. (FIG. 5) The p ⁺⁺ -type surface implantation region 14 is provided only inside the p ⁺ -type contact region 13 ′ of the active region 1. Therefore, 'since the surface deep concentration depth d22 of the drops, p ⁺ -type contact region 13' p ⁺ -type contact region 53 increases the resistance, but the latch-up tolerance is reduced, further p ⁺⁺ type surface on the surface By forming the implantation region 14, the contact resistance with the p ⁺ -type contact region 13 ′ is reduced, and latch-up resistance can be secured. On the other hand, if the p ⁺⁺ -type surface implantation region 14 is not disposed at the contact 50 of the carrier extraction region 5 as described later, the contact resistance Ra can be made higher than Rb.

Instead of the p ⁺ -type contact regions 53 and 53 ′, the p ⁺ -type contact regions 63 are provided only in the portions of the p-type well region 51 exposed to the contact holes (second contact holes) 54 described later. Good (Figure 6).

A plurality of contact holes 54 for selectively exposing the p ⁺ -type contact region 53 is provided in a portion of the interlayer insulating film 21 facing the p ⁺ -type contact region 53 in the depth direction Z. The plurality of contact holes 54 respectively penetrate the interlayer insulating film 21 in the depth direction Z to reach the front surface of the semiconductor substrate 10. The plurality of contact holes 54 are arranged in a striped layout extending along the outer periphery of the active region 1 and surround the periphery of the active region 1 in a substantially rectangular shape along the outer periphery of the active region 1.

  A barrier metal 23 extending from the active region 1 is provided along the inner wall of each of the contact holes 54 in the same manner as the active region 1. Then, in the inside of each contact hole 54, a contact plug 24 is provided on the barrier metal 23 as in the active region 1. The barrier metal 23 and the contact plug 24 inside the contact hole 54 are formed simultaneously with, for example, the barrier metal 23 and the contact plug 24 in the active region 1, respectively. The dimensions of the contact holes 54 may be the same as the contact holes 22 of the active region 1.

  Specifically, the depth d11 of the contact hole 54 may be, for example, about 0.5 μm to 1 μm. The width w11 of the contact hole 54 is, for example, 0.3 μm or more, which is the minimum value of the etching processing limit, and is about 1.0 μm or less that can completely embed the inside of the contact hole 54 with the contact plug 24. Is good. The width w12 between adjacent contact holes 54 may be equal to or greater than the width w11 of the contact holes 54, and preferably, may be approximately the same as the width w11 of the contact holes 54.

  The contact holes 54 may have a substantially rectangular cross-sectional shape having sidewalls substantially perpendicular to the front surface of the semiconductor substrate 10. The contact hole 54 has a side surface inclined at a predetermined angle with respect to the front surface of the semiconductor substrate 10, and has a substantially tapered cross section whose bottom width is narrower than the opening width on the interface with the emitter electrode 25. It may have a shape. When the contact hole 54 has a substantially tapered cross-sectional shape, the width w 11 of the contact hole 54 is the opening width on the interface side with the emitter electrode 25.

The titanium silicide (TiSi ₂ ) is formed between the p ⁺ -type contact region 53 and the barrier metal 23 by the reaction of silicon in the p-type well region 51 (p ⁺ -type contact region 53) and titanium in the barrier metal 23. A membrane is being produced. That is, in each contact hole 54, an ohmic contact 50 between the p ⁺ -type contact region 53 and the barrier metal 23 is formed. Hereinafter, a portion of the edge termination region 2 where the contact 50 is disposed is referred to as a carrier extraction region 5.

The carrier extraction region 5 is a region between the active region 1 and the gate runner portion 4. Emitter electrode 25 extends from active region 1 to the outside (for example, onto interlayer insulating film 21 of gate runner portion 4) and is embedded in all contact holes 54 of carrier extraction region 5. Emitter electrode 25 is electrically connected to p type well region 51 via contact plug 24 and barrier metal 23 inside the plurality of contact holes 54 of carrier extraction region 5 and p ⁺ type contact region 53. There is.

  Each contact 50 (contact hole 54) of the carrier extraction region 5 surrounds the periphery of the active region 1 in a substantially rectangular shape along the outer periphery of the active region 1, respectively. The contact 50 of the carrier extraction region 5 has a function of extracting holes, which are minority carriers generated in the edge termination region 2 when the IGBT is turned off, to the emitter electrode 25. A carrier extraction region in edge termination region 2 is provided by providing contact 50 for extracting holes from p type well region 51 to emitter electrode 25 in p type well region 51 forming main junction 52 in edge termination region 2. The current concentration to 5 can be suppressed.

Contact resistance Ra of the contact 50 of the carrier extraction region 5 (see FIG. 7 described later)
Is higher than the contact resistance Ra ′ of the contact 150 of the carrier extraction region 105 of the conventional structure (see FIGS. 10 and 11) (Ra> Ra ′). The reason is as follows. In the conventional structure, the main component of the emitter electrode 122 forming the contact 150 with silicon (p-type well region 151) is aluminum. In the present invention, the contact 50 of the carrier extraction region 5 is formed of a metal film (barrier metal 23) whose main component is titanium, in which the contact resistance with silicon (p-type well region 51) tends to be higher than aluminum. It is because

  Further, in the present invention, the p-type well region 51 is partially covered with the interlayer insulating film 21 so that the surface area is smaller than the contact 150 of the carrier extraction region 105 of the conventional structure. Thereby, the contact resistance Ra of the contact 50 of the carrier extraction region 5 can be made higher than the contact resistance Ra 'of the contact 150 of the carrier extraction region 105 of the conventional structure. Specifically, the contact resistance Ra of the contact 50 of the carrier extraction region 5 is preferably more than 100 times the contact resistance Ra 'of the contact 150 of the carrier extraction region 105 of the conventional structure (Ra> 100Ra').

Further, the contact resistance Ra of the contact 50 of the carrier extraction region 5 is higher than the contact resistance Rb of the contact 27 of the MOS gate 20 of the active region 1 (Ra> Rb). As described above, the condition of the contact resistance Ra is such that the p ⁺⁺ -type surface implantation region 14 is provided only in the p ⁺ -type contact region 13 ′ of the active region 1, and the p ⁺ -type contact region 53 is provided with p ⁺ It is obtained by not providing the ⁺ type surface implantation region. Further, the condition of the contact resistance Ra covers the surface area of the contact 50 of the carrier extraction region 5 with respect to the surface area of the contact 27 of the MOS gate 20 of the active region 1 by partially covering the p-type well region 51 with the interlayer insulating film 21. It is obtained by adjusting the ratio of

By setting the contact resistance Ra of the contact 50 of the carrier extraction region 5 in this way, as shown in FIG. 7, holes generated in the edge termination region 2 and flowing toward the active region 1 when the IGBT is turned off The current 70 mainly flows into the active region 1 through the portion directly below the p-type well region 51 (portion facing in the depth direction Z) of the n ⁻ -type drift region 11, and the contact 27 of the MOS gate 20. Are drawn out to the emitter electrode 25 (white arrows shown by reference numeral 71). Therefore, the hole current 70 does not easily flow into the p-type well region 51 of the carrier extraction region 5 whose contact resistance Ra is higher than that of the active region 1 (open arrow thinner than the reference numeral 71 indicated by the reference numeral 72). Therefore, the hole current 70 can be prevented from being concentrated in the p-type well region 51.

Further, the active region 1 occupies a larger area with respect to the chip area (surface area of the semiconductor substrate 10) than the edge termination region 2, and the number of contacts 27 of the MOS gate 20 is also large.
Therefore, the hole current 72 which has flowed into the active region 1 is dispersed to the plurality of contacts 27 so as to flow from under the p-type well region 51 to the inside of the n ⁻ -type drift region 11 and to the emitter electrode 25. It is pulled out. As a result, the hole current 72 can be prevented from concentrating in the p-type well region 51, and most of the hole current can be extracted to the contact 27 of the active region 1, so that self-clamp breakdown occurs. This makes it difficult to improve avalanche resistance.

  The width w2 of the carrier extraction region 5 may be, for example, 5 μm or more and 100 μm or less. The reason is as follows. By narrowing the width w2 of the carrier extraction region 5 and bringing the active region 1 closer to the gate runner portion 4, the hole current 72 can be extracted to the active region. On the other hand, when the width w2 of the carrier extraction region 5 exceeds 100 μm, it becomes difficult for current to flow in the active region 1, and most of the hole current 72 concentrates on the contact 27 of the p-type well region 51. It is from.

As described above, according to the first embodiment, a plurality of contact holes for selectively exposing the p ⁺ -type contact region inside the p-type well region are formed in the carrier extraction region, and A plurality of contacts of the p ⁺ -type contact region and the barrier metal mainly composed of titanium are formed inside. And, p ⁺⁺ type surface implantation region only in the p-type base region of the active region is provided, the carrier extracting region not provided p ⁺⁺ type surface implantation region. Thereby, the contact resistance of the contact of the carrier extraction region can be made higher than the contact resistance of the contact of the MOS gate of the active region. Therefore, when the IGBT is turned off, the hole current generated in the edge termination region and flowing toward the active region can be mainly extracted from the contact of the MOS gate in the active region to the emitter electrode. As a result, the hole current generated in the edge termination region during turn-off of the IGBT is not concentrated in the p-type well region of the carrier extraction region, and the avalanche tolerance of the edge termination region can be improved. It can be improved. Therefore, even when the IGBT is self-clamped, the edge termination region (carrier extraction region) is obtained by blocking the short circuit current flowing to the IGBT when the two IGBTs constituting the bridge circuit are both turned on. Can yield an IGBT that does not break down.

Second Embodiment
Next, the structure of the semiconductor device according to the second embodiment will be described. FIG. 8 is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment. The layout of the active region 1, the breakdown voltage structure portion 3, the gate runner portion 4 and the carrier extraction region 5 as viewed from the front surface side of the semiconductor substrate 10 is the same as that of the first embodiment (FIGS. 1 and 2). The configuration of the edge termination area 2 is similar to that of the edge termination area 2 of FIG. FIG. 8 is a part of the cross-sectional structure taken along the line B-B 'of FIG. 2, and shows the carrier extraction region 5 of FIG. 3 in an enlarged manner. The cross-sectional structure along the cutting line CC 'in FIG. 2 is the same as that in FIG. 4B.

The semiconductor device according to the second embodiment differs from the semiconductor device according to the first embodiment shown in FIG. 5 in that the p ⁺ -type contact region is not provided in the p-type well region 51 of the edge termination region 2. That is, the p ⁺ -type contact region 13 ′ is provided only in the p-type base region 12 of the active region 1. A p ⁺⁺ -type surface implantation region 14 may be provided inside the p ⁺ -type contact region 13 '. The contact 50 ′ of the carrier extraction region 5 is formed by the p-type well region 51 and the barrier metal 23 inside the contact hole 54.

The configuration in which the p ⁺ -type contact region is not provided in the p-type well region 51 of the edge termination region 2 as in the second embodiment may be applied to the semiconductor device according to the first embodiment shown in FIGS.

As described above, according to the second embodiment, the same effect as that of the first embodiment can be obtained. Further, according to the second embodiment, the p ⁺ -type contact region is not provided in the p-type well region of the carrier extraction region, as compared to the case where the p ⁺ -type contact region is provided in the p-type well region of the carrier extraction region. The contact resistance of the contact in the carrier extraction region can be increased. Therefore, current concentration due to hole current can be further suppressed in the carrier extraction region, and avalanche tolerance can be improved.

(Example)
Next, the avalanche resistance of the semiconductor device according to the above-described embodiment was verified.
FIG. 9 is a characteristic diagram showing the relationship between the temperature and the avalanche resistance. The horizontal axis of FIG. 9 is the junction temperature Tj of the embodiment (IGBT), and the vertical axis of FIG. 9 is the avalanche energy generated in the embodiment.

In the trench gate type IGBT having the structure of the semiconductor device according to the above-described embodiment (hereinafter referred to as an example), the junction temperature Tj of the pn junction between the p type base region 12 and the n ⁻ type drift region 11 The measurement results of avalanche resistance (allowable avalanche energy [mJ]) were shown in FIG. 9 while changing in the range of 40 ° C., 25 ° C., and 125 ° C. FIG. 9 also shows the avalanche resistance of the conventional trench gate type IGBT (hereinafter referred to as the conventional example: see FIGS. 10 to 12 and 19).

  According to the results of the example shown in FIG. 9, the avalanche energy value, which is less than 50 mJ in the conventional example, for example, in the range of -40.degree. C. to 125.degree. C. which is the junction temperature Tj is higher than 50 mJ with the structure of the present invention. It has been confirmed that it is possible to significantly improve the avalanche resistance.

Third Embodiment
Next, the structure of the semiconductor device according to the third embodiment will be described. FIG. 13 is a cross-sectional view showing the structure of the semiconductor device according to the third embodiment. The layout of the active region 1, the breakdown voltage structure portion 3, the gate runner portion 4 and the carrier extraction region 5 as viewed from the front surface side of the semiconductor substrate 10 is the same as that of the first embodiment (FIGS. 1 and 2). The configuration of the edge termination area 2 is similar to that of the edge termination area 2 of FIG. FIG. 13 is a part of the cross-sectional structure taken along the line B-B ′ of FIG. 2 and shows the structure near the boundary between the active region 1 and the carrier extraction region 5. The cross-sectional structure along the cutting line CC 'in FIG. 2 is obtained by adding an n-type carrier accumulation region 81 described later to FIG. 4B.

The semiconductor device according to the third embodiment is different from the semiconductor device according to the second embodiment in that an n-type carrier accumulation region 81 having an impurity concentration higher than that of the n ⁻ -type drift region 11 is provided in the active region 1. is there. The n-type carrier accumulation region 81 is p-type at a position deeper from the top surface of the semiconductor substrate 10 than the p-type base region 12 and shallower than the bottom surface of the trench 15 from the top surface of the semiconductor substrate 10. It is provided in contact with the base region 12.

Specifically, the n-type carrier accumulation region 81 is provided between the n ⁻ -type drift region 11 and the p-type base region 12 between the adjacent trenches 15 (mesa region). The n-type carrier storage region 81 extends in the second direction Y, and reaches the two trenches 15 adjacent to each other across the mesa region in which the n-type carrier storage region 81 is disposed. The n-type carrier accumulation region 81 is provided, for example, in all mesa regions.

Further, n-type carrier accumulation region 81 extends to the outside of n ⁺ -type emitter region 29 in the first direction X in which trenches 15 extend in a stripe shape, and from p-type well region 51 of carrier extraction region 5. Also ends inside. That is, the n-type carrier accumulation region 81 is not in contact with the p-type well region 51. In the third embodiment, the depth d 3 of the p-type well region 51 is deeper than the depth d 2 of the trench 15.

By arranging the n-type carrier accumulation region 81 immediately below the p-type base region 12, the hole density of the n ^-- type drift region 11 near the boundary with the p-type base region 12 can be increased during IGBT operation. it can. Thereby, the on voltage of the IGBT can be reduced. The n-type carrier accumulation region 81 may have a two-layer structure in which two n-type regions having different impurity concentrations in contact with each other are disposed to face in the depth direction Z.

Although not particularly limited, the impurity concentration of each portion of the semiconductor device according to the third embodiment takes the following values. The impurity concentration of the n ⁻ -type drift region 11 is about 1 × 10 ¹⁴ / cm ³ or less. For example, in the case of a withstand voltage of 700 V to 750 V class, the impurity concentration of the n ⁻ -type drift region 11 is about 1 × 10 ¹⁴ / cm ³ . The impurity concentration of the p-type base region 12 is about 1 × 10 ¹⁷ / cm ³ . The impurity concentration of the p-type well region 51 of the carrier extraction region 5 is about 1 × 10 ¹⁸ / cm ³ or more and 1 × 10 ¹⁹ / cm ³ or less. The impurity concentration of the n-type carrier accumulation region 81 is about 1 × 10 ¹⁶ / cm ³ .

  As described above, according to the third embodiment, even when the n-type carrier accumulation region is provided in the active region, the same effect as that of the first embodiment can be obtained. Further, according to the third embodiment, the on-voltage of the IGBT can be reduced by the n-type carrier accumulation region of the active region.

Embodiment 4
Next, the structure of the semiconductor device according to the fourth embodiment will be described by taking the case where the trenches 15 are arranged in a stripe extending in the first direction X as an example. 14 and 15 are cross-sectional views showing the structure of the semiconductor device according to the fourth embodiment. FIG. 16 is a plan view showing a layout of the semiconductor device according to the fourth embodiment as viewed from the front surface side of the semiconductor substrate.

  The layout of the active region 1, the breakdown voltage structure portion 3, the gate runner portion 4 and the carrier extraction region 5 as viewed from the front surface side of the semiconductor substrate 10 is the same as that of the first embodiment (FIGS. 1 and 2). The configuration of the edge termination region 2 is the same as that in which a second n-type carrier accumulation region 82 described later is added to the edge termination region 2 of FIG. 3. In the fourth embodiment, the enlarged view of the rectangular frame A of FIG. 1 is FIG. 2, and the enlarged view of the rectangular frame A ′ of FIG. 1 is FIG.

  A rectangular frame A in FIG. 1 is a portion of the edge termination region 2 surrounding the periphery of the active region 1 where the active region 1 and the edge termination region 2 are adjacent in the second direction Y. The rectangular frame A ′ in FIG. 1 is a portion of the edge termination region 2 surrounding the periphery of the active region 1, in which the active region 1 and the edge termination region 2 are adjacent in the first direction X. FIG. 16 shows a portion from the vicinity of the boundary between the active region 1 and the edge termination region 2 to a part of the gate runner portion 4.

  FIG. 14 is a part of the cross-sectional structure taken along the line B-B ′ of FIG. 2 and shows the structure near the boundary between the active region 1 and the carrier extraction region 5. The cross-sectional structure along the cutting line C-C 'in FIG. 2 is obtained by adding an n-type carrier storage region 81 and adding a second n-type carrier storage region 82 described later to FIG. 4B as in the third embodiment. is there. FIG. 15 shows a cross-sectional structure taken along line D-D 'in FIG. In FIG. 15, the gate electrode 17 inside the coupling portion 15 'at the end of the trench 15 is not shown.

  The semiconductor device according to the fourth embodiment is different from the semiconductor device according to the third embodiment in not only the active region 1 but also the second n-type carrier storage region 82 in the p-type well region 51 of the carrier extraction region 5. Point is provided. The second n-type carrier accumulation region 82 is the inside of the p-type well region 51 of the carrier extraction region 5 from the inside to the outside in the direction parallel to the front surface of the semiconductor substrate 10 (first and second directions X and Y) It is extended.

  The inner end of the second n-type carrier accumulation region 82 is located at the boundary between the active region 1 and the edge termination region 2 and is in contact with the outer sidewall of the trench 15 disposed outermost in the second direction Y . The outer end of the second n-type carrier accumulation region 82 ends at a position not facing the gate runner 42 in the depth direction Z. The outer end of the second n-type carrier accumulation region 82 may extend to the boundary between the gate runner portion 4 and the carrier extraction region 5.

  That is, the second n-type carrier accumulation region 82 is disposed between the active region 1 and the gate runner portion 4. The second n-type carrier accumulation region 82 is disposed apart from the contact 50 of the carrier extraction region 5 and is opposed to the contact 50 in the depth direction. The second n-type carrier accumulation region 82 separates the p-type well region 51 in the carrier extraction region 5 into a portion on the emitter side and a portion on the collector side.

  For example, when the end portions of the trenches 15 are connected to form a U-shape or an annular shape, the trenches 15 are extended to the gate runner portion 4 and the connection portions 15 ′ of the end portions of the trenches 15 are disposed in the gate runner portion 4 Do. As a result, the outer end of the second n-type carrier accumulation region 82 can be extended to the boundary between the gate runner 4 and the carrier extraction region 5 in the first direction X (FIGS. 15 and 16).

In this case, the entire coupling portion 15 ′ at the end of the trench 15 is covered with the p-type well region 51 of the carrier extraction region 5. The p ⁺ -type contact region 13 ′ of the MOS gate and the p ⁺⁺ -type surface implantation region 14 are extended in the first direction X to the inside of the carrier extraction region 5. In the carrier extraction region 5, the inner end of the p-type well region 51 may be located outside the boundary between the active region 1 and the carrier extraction region 5 in the first direction X (FIG. 16).

  In FIG. 16, the ends of the trenches 15 are alternately connected to every other one of the plurality of trenches 15 adjacent in the second direction Y, and the ends are connected between the trenches 15 connecting the ends to each other. 7 shows a state in which no trench 15 is disposed. The trench 15 having the end portions connected to each other is electrically connected to the gate metal interconnection 44 through the gate runner 42 at the connection portion 15 ′. The trench 15 not connected at the end is electrically connected to the gate metal interconnection 48 through the polysilicon layer 47 at the end.

  Also, the second n-type carrier storage region 82 is formed simultaneously with, for example, the n-type carrier storage region (hereinafter, referred to as a first n-type carrier storage region) 81 of the active region 1. The second n-type carrier storage region 82 is a portion in which the first n-type carrier storage region 81 is extended into the p-type well region 51 of the carrier extraction region 5. That is, the second n-type carrier storage region 82 has the same depth from the front surface of the semiconductor substrate 10 as the first n-type carrier storage region 81, and the thickness thereof is the same as the thickness of the first n-type carrier storage region 81 .

  The first and second n-type carrier accumulation regions 81 and 82 are formed, for example, after forming a gate runner 42 or the like by a polysilicon layer on the front surface of the semiconductor substrate 10. On the other hand, in the case where the first and second n-type carrier accumulation regions 81 and 82 are formed before the formation of the gate runner 42 etc., the second n-type carrier accumulation region 82 Y may penetrate from the inside to the outside, and may face the gate runner 42 in the depth direction X.

  In the fourth embodiment, p-type well region 51 of carrier extraction region 5 is in contact with the outer sidewall of trench 15 disposed outermost in second direction Y, and active region 1 in the first direction X. And the edge termination area 2 is reached.

  As described above, according to the fourth embodiment, by providing the second n-type carrier accumulation region in the p-type well region of the carrier extraction region, carrier extraction is performed as compared to the case where the second n-type carrier accumulation region is not provided. The resistance of the p-type well region of the region can be increased. As a result, as in the first to third embodiments, the avalanche resistance of the edge termination region can be improved, and therefore the avalanche resistance of the entire element can be improved. Further, according to the fourth embodiment, as in the first to third embodiments, since the avalanche resistance of the entire element is determined by the avalanche resistance of the active region, it is possible to obtain an IGBT which is not broken in the edge termination region (carrier extraction region). Can.

  For example, if the avalanche resistance of the entire edge termination region is determined by the avalanche resistance of the edge termination region, the element breakdown occurs in the edge termination region at the moment when a surge voltage exceeding the clamping voltage of the protection device occurs at the time of turning off the IGBT. On the other hand, when the avalanche resistance of the entire element is determined by the avalanche resistance of the active region, the avalanche resistance in the edge termination region is higher than the avalanche resistance in the active region, so a surge exceeding the clamp voltage of the protection element at turn-off of the IGBT. Even if a voltage is generated, the element is not broken in the edge termination region.

  However, in the conventional structure, when the avalanche resistance of the entire device is determined by the avalanche resistance of the active region, the length of the edge termination region is increased to increase the avalanche resistance of the edge termination region. The size increases and the cost increases. Further, in the RC-IGBT described in Patent Document 1 (see FIG. 19), since the second n-type carrier accumulation region 222 is disposed in the boundary region 203 where there is no electrode for extracting a carrier, the boundary region 203 is It does not become a carrier extraction area.

  On the other hand, according to the fourth embodiment, the second n-type carrier accumulation region is provided in the carrier extraction region where the emitter electrode for extracting carriers is present. Thus, when a surge voltage exceeding the clamp voltage of the protection element is generated at turn-off of the IGBT, carriers can be extracted to the emitter electrode in both the active region and the carrier extraction region. In addition, when a surge voltage exceeding the clamp voltage of the protection element is generated at the time of turn-off of the IGBT, it is possible to increase the ratio of carriers being pulled out in the active region as compared with the edge termination region.

  Thus, by increasing the rate at which carriers are extracted in the active region as compared with the edge termination region, even if a surge voltage exceeding the clamp voltage of the protection element is generated at the time of turn-off of the IGBT, the device is not destroyed in the edge termination region. Therefore, by providing the second n-type carrier accumulation region in the p-type well region of the carrier extraction region, the avalanche resistance in the edge termination region is higher than the avalanche resistance in the active region while maintaining the length of the edge termination region. It can be raised. Therefore, the avalanche resistance in the edge termination region can be improved without increasing the cost.

  Therefore, according to the fourth embodiment, the avalanche resistance of the entire element can be improved.

Fifth Embodiment
Next, the structure of the semiconductor device according to the fifth embodiment will be described. FIG. 17 is a cross-sectional view showing the structure of the semiconductor device according to the fifth embodiment. The layout of the active region 1, the breakdown voltage structure portion 3, the gate runner portion 4 and the carrier extraction region 5 as viewed from the front surface side of the semiconductor substrate 10 is the same as that of the first embodiment (FIGS. 1 and 2). FIG. 17 is a part of the cross-sectional structure along the cutting line C-C 'in FIG. 2, and shows the structure in the vicinity of the boundary between the active region 1 and the carrier extraction region 5. The cross-sectional structure along the cutting line B-B 'of FIG. 2 is the same as that of FIG.

The semiconductor device according to the fifth embodiment is different from the semiconductor device according to the fourth embodiment in that n ⁺ -type emitter regions 29 ′ are disposed in all the mesa regions. That is, the n ⁺ -type emitter region 29 ′ is provided up to the mesa region disposed outermost in the second direction Y. The reason why the n ⁺ -type emitter regions 29 'can be arranged in all the mesa regions in this way is that the second n-type carrier accumulation region 82 is arranged in the p-type well region 51 of the carrier extraction region 5 .

Since the second n-type carrier accumulation region 82 is disposed in the p-type well region 51 of the carrier extraction region 5, the contact of the mesa region on the carrier extraction region 5 side of the active region 1 is made with the contact 50 of the carrier extraction region 5. Even without functioning, a predetermined avalanche resistance of the edge termination region can be obtained. As a result, it is possible to reduce the chip size by eliminating the mesa region where the n ⁺ -type emitter region 29 of the active region 1 is not provided. Alternatively, the n ⁺ -type emitter regions 29 ′ can be arranged in all the mesa regions to increase the area operating as an IGBT.

As described above, according to the fifth embodiment, even when n ⁺ -type emitter regions are arranged in all the mesa regions, the same effect as in the first to fourth embodiments can be obtained.

Sixth Embodiment
Next, the structure of the semiconductor device according to the sixth embodiment will be described. FIG. 18 is a cross-sectional view showing the structure of the semiconductor device according to the sixth embodiment. The layout of the active region 1, the breakdown voltage structure portion 3, the gate runner portion 4 and the carrier extraction region 5 as viewed from the front surface side of the semiconductor substrate 10 is the same as that of the first embodiment (FIGS. 1 and 2). As in the fourth embodiment, the enlarged view of the rectangular frame A of FIG. 1 is FIG. 2, and the enlarged view of the rectangular frame A ′ of FIG. 1 is FIG.

  FIG. 18 is a part of the cross-sectional structure taken along the line B-B ′ of FIG. 2 and shows the structure near the boundary between the active region 1 and the carrier extraction region 5. The sectional structure along the cutting line C-C 'in FIG. 2 is the same as the fourth embodiment except that the first n-type carrier storage region 81 is added and the second n-type carrier storage region 82 is added to FIG. 4B. is there. The sectional structure taken along the section line D-D 'of FIG. 16 is the same as that of the fourth embodiment (FIG. 15).

  The semiconductor device according to the sixth embodiment is different from the semiconductor device according to the third embodiment in that the second n-type carrier storage region 82 ′ of the carrier extraction region 5 is more semiconductor than the first n-type carrier storage region 81 of the active region 1. It is a point disposed at a depth close to the front surface of the substrate 10. That is, the depth of the second n-type carrier storage region 82 ′ of the carrier extraction region 5 is shallower than the depth of the first n-type carrier storage region 81 of the active region 1 from the front surface of the semiconductor substrate 10.

  As the second n-type carrier accumulation region 82 'of the carrier extraction region 5 approaches the contact 50 of the carrier extraction region 5, the ratio of carriers extracted in the active region can be increased compared to the edge termination region. In the sixth embodiment, the second n-type carrier storage region 82 ′ is formed at a timing different from that of the first n-type carrier storage region 81. The thickness t12 of the second n-type carrier storage region 82 'may be different from the thickness t11 of the first n-type carrier storage region 81.

  As described above, according to the sixth embodiment, as the second n-type carrier accumulation region in the carrier extraction region is closer to the contact in the carrier extraction region, it occurs in the edge termination region at the time of turn-off of the IGBT and moves to the active region side The hole current flowing toward it becomes difficult to be extracted from the contact of the carrier extraction region. As a result, the rate at which carriers are extracted in the active region can be increased as compared with the edge termination region, so that the same effect as in the first to fifth embodiments can be obtained.

  The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. For example, the present invention is not limited to IGBTs, but MOSFETs (Metal Oxide Semiconductor Field Effect Transistors: MOS type field effect transistors provided with an insulating gate consisting of a three-layer structure of metal-oxide film-semiconductor) and semiconductors identical to IGBTs It is applicable also to RC-IGBT (Reverse Conducting-IGBT: reverse conduction type IGBT) which provided the diode in the substrate (semiconductor chip).

Further, according to the present invention, only in the carrier extraction region, the semiconductor portion (p ⁺ -type contact region) and the barrier metal mainly composed of titanium are in ohmic contact to form a contact, and in the active region, the MOS gate is formed. The semiconductor portion (p ⁺ -type contact region) of the above may be in direct contact with an emitter electrode mainly composed of aluminum to form an ohmic contact. In the present invention, the MOS gate in the active region may be replaced with a trench gate structure to be a planar gate structure. Further, the present invention is similarly applicable even when the conductivity type (n type, p type) is reversed.

  As described above, the semiconductor device according to the present invention has an active region and an edge termination region surrounding the periphery of the active region, and is useful for a power semiconductor device used for a power conversion device, etc. Suitable for gate type IGBT.

DESCRIPTION OF SYMBOLS 1 active region 2 edge termination region 3 breakdown voltage structure portion 4 gate runner portion 5 carrier extraction region 10 semiconductor substrate 11 n ⁻ type drift region 12 p type base region of MOS gate 13, 13 ′, 61 p ⁺ type contact region of MOS gate 14, 62 MOS gate p ⁺⁺ type surface implantation region 15 MOS gate trench 15 'MOS gate trench connection portion 16 MOS gate gate insulating film 17 MOS gate gate electrode 18 n type field stop region 19 p ⁺ type collector region 20 MOS gate 21 interlayer insulating film 22 active region of the contact hole 23 barrier metal 24 contact plug 25 emitter electrode 26 polyimide protective film 27 MOS gate contact 28 collector electrode 29, 29 'n ⁺ -type emitter region 30 the breakdown voltage structure 3 Field limiting ring 32 field plate 33 of polysilicon electrodes 34,36,43 barrier metal and the contact plugs 35 n ⁺ -type stopper region 37 stopper electrode 41 insulating layer 42 gate runner 44 gate metal wiring 45 contact hole 46 gate pad 50, 50 ' Contacts of carrier extraction region 51 p-type well regions of carrier extraction region 52 main junctions 53, 53 ', 63 p ⁺ -type contact region of carrier extraction region 54 contact holes of carrier extraction region 70-72 hole current 81 active region n-type carrier storage area (first n-type carrier storage area)
82, 82 'n-type carrier accumulation region (second n-type carrier accumulation region) of carrier extraction region
d1 depth of p-type base region of MOS gate d2 depth of trench of MOS gate d3 depth of p-type well region of carrier extraction region d11 depth of contact hole of carrier extraction region d21, d21 'p ^{+ of} active region Contact area depth d22, d22 'carrier extraction area depth p ⁺ type contact area depth Ra carrier extraction area contact resistance contact Rb active area MOS gate contact resistance t1 semiconductor substrate thickness t11 active area Thickness of n-type carrier storage area t12 Thickness of n-type carrier storage area of carrier extraction area w1 Width of edge termination area w2 Width of carrier extraction area w11 Width of contact hole of carrier extraction area w12 Contact adjacent to carrier extraction area Width between holes

Claims (19)

An active region provided in a semiconductor substrate of a first conductivity type, in which a main current flows;
An end region surrounding the periphery of the active region;
In the active region, a first semiconductor region of a second conductivity type provided in a surface layer on the first main surface side of the semiconductor substrate;
A second semiconductor region of a first conductivity type selectively provided inside the first semiconductor region;
A second semiconductor type third semiconductor region which is selectively provided inside the first semiconductor region and has a higher impurity concentration than the first semiconductor region;
A second conductive fourth semiconductor region selectively provided in the surface layer on the first main surface side of the semiconductor substrate in the termination region;
A fifth semiconductor region of the first conductivity type, which is a region other than the first semiconductor region and the fourth semiconductor region, of the semiconductor substrate;
A gate insulating film provided in contact with a region between the fifth semiconductor region and the second semiconductor region in the first semiconductor region;
A gate electrode provided on the opposite side of the first semiconductor region with the gate insulating film interposed therebetween;
An interlayer insulating film provided on the first main surface of the semiconductor substrate and covering the second semiconductor region, the third semiconductor region, the fourth semiconductor region, and the gate electrode;
A first contact hole opened in the interlayer insulating film and exposing the second semiconductor region and the third semiconductor region;
A plurality of second contact holes which are opened in the interlayer insulating film and selectively expose the fourth semiconductor regions, respectively;
A first metal film provided along the inner wall of the second contact hole, having high adhesion to the semiconductor substrate and in ohmic contact with the semiconductor substrate;
A second metal film embedded on the first metal film inside the second contact hole;
It is provided on the interlayer insulating film, is electrically connected to the first semiconductor region through the second semiconductor region and the third semiconductor region in the first contact hole, and is connected to the first contact region in the second contact hole. A first electrode electrically connected to the fourth semiconductor region via a second metal film and the first metal film;
A second electrode provided on a second main surface of the semiconductor substrate;
A semiconductor device comprising: The semiconductor device further comprises a sixth semiconductor region of a second conductivity type which is selectively provided inside the fourth semiconductor region and has a higher impurity concentration than the third semiconductor region.
The first electrode is electrically connected to the fourth semiconductor region through the second metal film, the first metal film, and the sixth semiconductor region in the second contact hole. The semiconductor device according to claim 1. The semiconductor device further includes a seventh semiconductor region of a second conductivity type, which is selectively provided inside the third semiconductor region, having a higher impurity concentration than the third semiconductor region.
3. The semiconductor device according to claim 1, wherein the first electrode is electrically connected to the first semiconductor region through the seventh semiconductor region and the third semiconductor region in the first contact hole. The semiconductor device of description. The fourth semiconductor region surrounds the periphery of the active region along the periphery of the active region,
The plurality of second contact holes are arranged in a striped layout extending along the outer periphery of the active region, and surround the periphery of the active region. Semiconductor devices.   The semiconductor device according to any one of claims 1 to 4, wherein a width of the second contact hole is 0.3 μm or more and 1.0 μm or less.   The semiconductor device according to any one of claims 1 to 5, wherein a width between the adjacent second contact holes is the same as a width of the second contact holes. In the termination region, the gate electrode is provided on the first main surface of the semiconductor substrate with an insulating layer interposed therebetween, the gate electrode facing the fourth semiconductor region across the insulating layer in the depth direction, and electrically connected Further equipped with a gate pad
The semiconductor according to any one of claims 1 to 6, wherein the plurality of second contact holes are provided between the boundary between the active region and the termination region and the gate pad. apparatus.   The semiconductor device according to claim 7, wherein a distance between a boundary between the active region and the termination region and the gate pad is 5 μm or more.   The semiconductor device according to any one of claims 1 to 8, wherein the first electrode is in ohmic contact with the second semiconductor region and the third semiconductor region. The first metal film is provided along the inner wall of the first contact hole,
10. The semiconductor device according to any one of claims 1 to 9, wherein the second metal film is embedded on the first metal film inside the first contact hole.   The semiconductor device according to any one of claims 1 to 10, wherein the first metal film contains titanium as a main component.   The semiconductor device according to any one of claims 1 to 11, wherein the second metal film contains tungsten as a main component. The semiconductor device further includes a trench extending from the top surface of the first semiconductor region to the fifth semiconductor region,
The gate insulating film is provided along the inner wall of the trench,
The semiconductor device according to any one of claims 1 to 12, wherein the gate electrode is embedded inside the gate insulating film inside the trench.   The semiconductor device according to claim 1, further comprising: an eighth semiconductor region of a first conductivity type having an impurity concentration higher than that of the fifth semiconductor region, between the first semiconductor region and the fifth semiconductor region. Semiconductor device.   A first conductivity type having an impurity concentration higher than that of the fifth semiconductor region, which faces the second contact hole in the depth direction away from the first main surface of the semiconductor substrate inside the fourth semiconductor region The semiconductor device according to claim 14, further comprising a ninth semiconductor region. In the termination region, the gate electrode is provided on the first main surface of the semiconductor substrate with an insulating layer interposed therebetween, the gate electrode facing the fourth semiconductor region across the insulating layer in the depth direction, and electrically connected Further equipped with a gate pad
The semiconductor device according to claim 15, wherein the ninth semiconductor region extends from the active region side to the gate pad side and terminates on the active region side with respect to the gate pad.   17. The semiconductor device according to claim 15, wherein the ninth semiconductor region is located at the same depth as the eighth semiconductor region from the first main surface of the semiconductor substrate.   17. The semiconductor device according to claim 15, wherein the ninth semiconductor region is located at a depth shallower than the first main surface of the semiconductor substrate than the eighth semiconductor region. The semiconductor device further includes a trench extending from the top surface of the first semiconductor region to the fifth semiconductor region,
The gate insulating film is provided along the inner wall of the trench,
The gate electrode is embedded inside the gate insulating film inside the trench,
The trenches are arranged in stripes extending in a direction parallel to the first major surface of the semiconductor substrate,
The semiconductor device according to any one of claims 15 to 18, wherein the second semiconductor region is provided between all the adjacent trenches.

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