JP2013251464A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can reduce on-state voltage and reduce a time change rate di/dt of a collector current in an on-state.SOLUTION: A semiconductor device comprises: projected semiconductor regions 2 provided on a first principal surface of a semiconductor substrate which is to become an ntype drift layer 1; p type base layers 3 and ntype emitter layers 4 which are provided inside the projected semiconductor regions 2, in which the p type base layers 3 are sandwiched by the ntype emitter layers 4 and the ntype drift layer 1 at lateral faces of the projected semiconductor regions 2; a first gate electrode 7-1 is opposite to a part of the p type base layer 3, which is sandwiched by the ntype emitter layers 4 and the ntype drift layer 1 via a gate insulation film 6; a second gate electrode 7-2 which is provided at a distance from the first gate electrode 7-1 and which is opposite to the ntype drift layer 1 via the gate insulation film 6; and a gate (G) terminal to which the first gate electrode 7-1 is directly connected and the second gate electrode 7-2 is connected via an internal resistance R.

Description

  The present invention relates to a semiconductor device.

  2. Description of the Related Art Conventionally, as a power semiconductor device used for a power conversion device or the like, one MOS (metal-oxide-semiconductor-insulated gate) is provided in a semiconductor region protruding from a main surface of a semiconductor substrate (hereinafter referred to as a protruding semiconductor region). An IGBT (insulated gate bipolar transistor) having a convex cross-sectional structure (hereinafter referred to as a convex cell structure) in which a structure is formed is known. As a semiconductor device having such a convex cell structure, a step is provided at the boundary between the guard ring portion and the connecting portion in the peripheral portion of the element in the semiconductor substrate, and the peripheral portion is separated from the element portion by the step. An apparatus that is one step lower than the wafer reference surface has been proposed (see, for example, Patent Document 1 below).

As such a convex cell structure IGBT, an IGBT having a structure in which only one MOS layer emitter layer structure is provided in one protruding semiconductor region (hereinafter referred to as a convex emitter structure) is known. . FIG. 13 is a cross-sectional view showing a conventional semiconductor device. In the IGBT having the conventional convex emitter structure shown in FIG. 13, the p-type base layer 3 is formed inside the semiconductor region (projected semiconductor region) 2 protruding from the first main surface of the semiconductor substrate to be the n ⁻ -type drift layer 1. , N ⁺⁺ type emitter layer 4 and p ⁺ type contact layer 5 are provided so as to be in contact with each other.

On the side surface of the protruding semiconductor region 2, the p-type base layer 3 is sandwiched between the n ⁺⁺ -type emitter layer 4 and the n ⁻ -type drift layer 1. A portion of the p-type base layer 3 sandwiched between the n ⁺⁺ -type emitter layer 4 and the n ⁻ -type drift layer 1 is formed from the side surface of the protruding semiconductor region 2 to the first main surface of the semiconductor substrate continuous to the side surface. A gate electrode 107 is provided on the most part of the device surface so as to cover the gate insulating film 106. Emitter electrode 8 is in contact with n ⁺⁺ -type emitter layer 4 and p ⁺ -type contact layer 5 and is electrically insulated from gate electrode 107 by interlayer insulating film 9. A collector layer and a collector electrode are provided on a second main surface (not shown) of the semiconductor substrate.

By adopting the convex emitter structure, since the area ratio of the p-type base layer 3 to the surface area on the emitter side is reduced, the IE (Injection Enhancement) effect is improved and the on-voltage is reduced. Further, since the area ratio of the p-type base layer 3 is reduced, the cell pitch is reduced while keeping the area ratio of the p-type base layer 3 low. Thereby, since the number of cells incorporated in the chip can be increased, the current value to be borne per cell is reduced. Further, by reducing the cell pitch, the width of the region (hereinafter referred to as an electron storage layer) in which the electrons facing the gate electrode 107 of the n ⁻ type drift layer 1 are stored is reduced. Therefore, the voltage drop in the electron storage layer is reduced, and electrons are easily injected from the electron storage layer.

As a semiconductor device having such a convex emitter structure, a surface of an n-type semiconductor substrate has a plurality of parallel trenches and a protruding semiconductor region narrower than the trench between the parallel trenches, and the protruding semiconductor region In addition, a device having a p-type base layer and an n ⁺⁺ region on the surface side of the p-type base layer and having a gate electrode on the side wall of the protruding semiconductor region via a gate insulating film has been proposed (for example, , See Patent Document 2 below).

  Further, as another semiconductor device, a semiconductor substrate, a high-resistance first-conductivity-type semiconductor layer formed on the main surface of the semiconductor substrate, and a second-conductivity-type semiconductor layer formed on the surface layer portion of the semiconductor layer A base region; a source region of a first conductivity type formed at a surface layer portion of the base region with a junction depth shallower than the base region; and an upper portion of the base region sandwiched between the source region and the semiconductor layer. In addition, a device including a gate electrode formed through a gate insulating film has been proposed (for example, see Patent Document 3 below).

JP 2002-164541 A JP 2010-141310 A Japanese Patent No. 3985358

However, in Patent Documents 1 to 3 described above, most of the device surface is covered with the gate electrode 107 in order to improve the IE effect. Therefore, n during on ^- the carrier to type drift layer 1 is implanted, n ^- -type drift layer 1, when the potential of the portion facing the gate electrode 107 is increased, n ^- type space charge in the drift layer 1 The distribution changes under the influence of the electric field generated by the gate electrode 107. Then, a displacement current flows into a portion of the gate electrode 107 facing the n ⁻ type drift layer 1. Since this displacement current flows as a discharge current to a gate drive circuit (not shown), a voltage drop occurs in a gate resistance (not shown), which is a DC resistance from the gate terminal to the gate electrode 107, and the gate voltage rises.

  As the gate voltage rises, the collector current suddenly rises, so that the time change rate di / dt of the collector current increases. As a result, for example, in an inverter circuit (not shown) configured by bridging IGBTs, a current reduction rate of a free wheel diode (FWD) that is connected in reverse parallel to the opposite arm and returns a load current increases. The reverse recovery peak current of the freewheeling diode increases. As a result, the time change rate di / dt of the reverse recovery peak current increases, and the surge voltage applied to the freewheeling diode increases. For this reason, there is a problem that noise increases due to vibration of the reverse recovery waveform of the freewheeling diode, or the freewheeling diode is destroyed by overvoltage.

By increasing the gate resistance and slowing down the turn-on operation of the IGBT, the displacement current flowing from the n ⁻ type drift layer 1 to the gate drive circuit via the gate electrode 107 can be reduced. However, even if the displacement current decreases, the gate resistance increases, so the potential difference between both ends of the gate resistance caused by the displacement current does not change much. Therefore, even if the gate resistance is increased, an increase in the gate voltage due to a voltage drop generated in the gate resistance cannot be prevented, and the time change rate di / dt of the collector current cannot be reduced.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device capable of reducing an on-voltage in order to solve the above-described problems caused by the prior art. Another object of the present invention is to provide a semiconductor device capable of reducing the rate of time change of collector current at the time of on-state in order to eliminate the above-mentioned problems caused by the prior art.

  In order to solve the above-described problems and achieve the object of the present invention, a semiconductor device according to the present invention includes a semiconductor substrate of a first conductivity type, and a projecting second provided on a first main surface of the semiconductor substrate. A first semiconductor region of a conductive type, a second semiconductor region of a first conductive type provided in the first semiconductor region away from the first main surface of the semiconductor substrate, and the first semiconductor region, A first control electrode provided via a dielectric film in a portion sandwiched between the second semiconductor region and the semiconductor substrate, to which a control signal is supplied; and apart from the first control electrode, the first control electrode of the semiconductor substrate A second control electrode having the same potential as that of the first control electrode, a first main electrode in contact with the first semiconductor region and the second semiconductor region, and a first main electrode in contact with the first semiconductor electrode; A third semiconductor region of the second conductivity type provided on the second main surface; A second main electrode in contact with the serial third semiconductor region, characterized in that it comprises a.

  The semiconductor device according to the present invention is characterized in that, in the above-described invention, the second control electrode is electrically connected to the first control electrode via a resistor.

  In the semiconductor device according to the present invention, the first metal layer surrounding the active region and in contact with the first control electrode provided so as to extend to the periphery of the active region in the above-described invention, and the first metal Surrounding the layer, is in contact with an end of the second control electrode provided so as to extend to the periphery of the active region, and is electrically connected to the first metal layer through the resistor made of a metal film. And a second metal layer.

  In the semiconductor device according to the present invention as set forth in the invention described above, the area of the portion of the first control electrode facing the first main surface of the semiconductor substrate is the second control electrode of the semiconductor substrate. It is smaller than the area of the part facing 1 main surface.

  The semiconductor device according to the present invention is characterized in that, in the above-described invention, the second control electrode is provided apart from the first semiconductor region.

  In the semiconductor device according to the present invention, the first semiconductor region is provided in plural on the first main surface of the semiconductor substrate, and the first control electrode and the second control electrode are It is characterized by being sandwiched between the adjacent first semiconductor regions.

According to the above-described invention, by providing the first and second control electrodes apart from each other, the displacement control generated due to the potential rise of the n ⁻ type drift layer at the time of on-state is mainly controlled by the second control facing the n ⁻ type drift layer. It can flow to the electrode. N of the first control electrode ^- opposing area between -type drift layer n of the second control electrode ^- smaller than the facing area between the type drift layer, the displacement current does not substantially flow into the first control electrode. Thereby, it is possible to avoid a voltage drop from occurring in the gate resistance, which is a direct current resistance from the gate terminal to the first control electrode.

  Furthermore, according to the above-described invention, since the second control electrode is connected to the gate terminal via the resistor, the current from the second control electrode to the gate drive circuit hardly flows. Thereby, the displacement current flowing from the second control electrode to the gate drive circuit at the time of ON can be reduced, and the potential difference between both ends of the gate resistance caused by the displacement current can be reduced. As a result, an increase in the gate voltage is suppressed, and an increase in the collector current can be suppressed.

  Further, according to the embodiment, a structure (convex emitter structure) in which only one MOS structure emitter layer structure is provided in one projecting semiconductor region is opposed to the first and second control electrodes, respectively. Since the electron storage layer is formed in the semiconductor region to be processed, the electron storage layer can be made larger than a general IGBT. Thereby, the IE effect can be improved.

  According to the semiconductor device of the present invention, the on-voltage can be reduced. Further, according to the semiconductor device of the present invention, it is possible to reduce the time change rate of the collector current at the on time.

1 is a cross-sectional view showing a semiconductor device according to an embodiment. FIG. 2 is a plan view showing a gate wiring structure of the semiconductor device of FIG. 1. It is sectional drawing which shows the semiconductor device in the middle of manufacture concerning embodiment. It is sectional drawing which shows the semiconductor device in the middle of manufacture concerning embodiment. It is sectional drawing which shows the semiconductor device in the middle of manufacture concerning embodiment. It is sectional drawing which shows the semiconductor device in the middle of manufacture concerning embodiment. It is sectional drawing which shows the semiconductor device in the middle of manufacture concerning embodiment. It is sectional drawing which shows the semiconductor device in the middle of manufacture concerning embodiment. It is sectional drawing which shows the semiconductor device in the middle of manufacture concerning embodiment. It is sectional drawing which shows the semiconductor device in the middle of manufacture concerning embodiment. It is sectional drawing which shows the semiconductor device in the middle of manufacture concerning embodiment. It is explanatory drawing which shows the time change rate of the collector current of the semiconductor device concerning embodiment. It is sectional drawing which shows the conventional semiconductor device.

  Hereinafter, preferred embodiments of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + and − attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region where it is not attached. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

(Embodiment)
FIG. 1 is a cross-sectional view illustrating a semiconductor device according to an embodiment. The semiconductor device according to the embodiment shown in FIG. 1 has a layer structure of an emitter having one MOS structure in a semiconductor region (projected semiconductor region) 2 protruding from a first main surface of a semiconductor substrate to be an n ⁻ type drift layer 1. This is an IGBT provided with a (convex emitter structure). In the IGBT having the convex emitter structure according to the embodiment shown in FIG. 1, a plurality of protruding semiconductor regions 2 are provided on the first main surface of the n-type semiconductor substrate to be the n ⁻ -type drift layer 1 apart from each other. It has been. For example, the plurality of protruding semiconductor regions 2 are preferably arranged in a stripe shape extending in a direction orthogonal to the direction in which the protruding semiconductor regions 2 are arranged. In FIG. 1, only the cross-sectional structure near one protruding semiconductor region 2 is shown.

  The apex portion of the protruding semiconductor region 2 is a flat surface. The side surface of the protruding semiconductor region 2 may have an inclination with respect to the first main surface of the semiconductor substrate between the adjacent protruding semiconductor regions 2. Specifically, for example, the protruding semiconductor region 2 may have a trapezoidal cross-sectional shape that widens from the apex side toward the semiconductor substrate side. An angle (recess angle) θ between the side surface of the protruding semiconductor region 2 and the first main surface of the semiconductor substrate between the adjacent protruding semiconductor regions 2 is preferably 150 degrees or less, and more preferably 90 degrees. The closer it is to the better. The reason is as follows.

  As the angle θ between the side surface of the protruding semiconductor region 2 and the first main surface of the semiconductor substrate between the adjacent protruding semiconductor regions 2 approaches 180 degrees, the flat surface of the apex portion on the side surface of the protruding semiconductor region 2 Therefore, the area ratio of the semiconductor substrate side to the apex side of the protruding semiconductor region 2 is increased. Therefore, even when the area of the flat top surface (emitter side) of the protruding semiconductor region 2 is small, the area ratio of the p-type base layer 3 described later with respect to the surface area on the emitter side increases. This is because the average carrier concentration on the emitter side is reduced compared to the collector side (the second main surface side of the semiconductor substrate), and the IE effect is reduced.

Each protruding semiconductor region 2 is provided with only one emitter layer structure of MOS structure. One MOS structure (hereinafter referred to as a unit cell) is formed between adjacent protruding semiconductor regions 2. Specifically, a p-type base layer (first semiconductor region) 3 is provided in the surface layer on the apex side inside the protruding semiconductor region 2. The p-type base layer 3 is provided over almost the entire protruding semiconductor region 2 from one side surface to the other side surface of the protruding semiconductor region 2. In other words, the protruding semiconductor region 2 is constituted by a protruding p-type base layer 3 in contact with the n ⁻ -type drift layer 1.

Inside the p-type base layer 3, an n ⁺⁺ -type emitter layer (second semiconductor region) 4 is provided on the surface layer on the apex side of the protruding semiconductor region 2. The impurity concentration of the n ⁺⁺ type emitter layer 4 is higher than the impurity concentration of the n ⁻ type drift layer 1. Inside the p-type base layer 3 is provided a p ⁺ -type contact layer 5 that contacts the n ⁺⁺ -type emitter layer 4 and penetrates the p-type base layer 3 to reach the n ⁻ -type drift layer 1. . The impurity concentration of the p ⁺ -type contact layer 5 is higher than the impurity concentration of the p-type base layer 3.

The p ⁺ type contact layer 5 reduces the contact resistance between the p type base layer 3 and an emitter electrode 8 described later. The p ⁺ -type contact layer 5 prevents latch-up due to the operation of the parasitic thyristor. The p-type base layer 3, the n ⁺⁺ -type emitter layer 4, and the p ⁺ -type contact layer 5 provided inside each protruding semiconductor region 2 are, for example, in a direction orthogonal to the direction in which the protruding semiconductor regions 2 are arranged. It is preferable to arrange in an extending stripe shape.

A portion of the p-type base layer 3 sandwiched between the n ⁺⁺ -type emitter layer 4 and the n ⁻ -type drift layer 1 is provided with a first gate electrode 7-1 (first control electrode) via a gate insulating film 6. Is provided. The first gate electrode 7-1 is provided across the first main surface of the semiconductor substrate between the side surface of the protruding semiconductor region 2 and another adjacent protruding semiconductor region 2. The first gate electrode 7-1 is directly connected to the gate (G) terminal.

Between the adjacent protruding semiconductor regions 2, a second gate electrode 7-2 (second control electrode) is provided on the first main surface of the semiconductor substrate via the gate insulating film 6. That is, the second gate electrode 7-2 is opposed to the n ⁻ -type drift layer 1 through the gate insulating film 6. The second gate electrode 7-2 is provided apart from the first gate electrode 7-1. The second gate electrode 7-2 is provided away from the p-type base layer 3 so as not to face the p-type base layer 3. The second gate electrode 7-2 is connected to the gate (G) terminal via an internal resistance R made of, for example, polysilicon, and has the same potential as the first gate electrode 7-1. In FIG. 1, the internal resistance R is illustrated so as to overlap the emitter electrode 8, but the internal resistance R is electrically insulated from the emitter electrode 8 by an interlayer insulating film 9, for example. The wiring structure between the first and second gate electrodes 7-1 and 7-2 and the internal resistance R will be described later.

The area of the portion of the first gate electrode 7-1 facing the n ⁻ type drift layer 1 (hereinafter referred to as the area of the first gate electrode 7-1 facing the n ⁻ type drift layer 1) is the second gate. electrodes 7-2, n ^- area type drift layer 1 and the opposing portions (hereinafter, n of the second gate electrode 7-2 ^- the opposing area between -type drift layer 1) is smaller than. The first and second gate electrodes 7-1 and 7-2 are preferably arranged in stripes extending in a direction orthogonal to the direction in which the protruding semiconductor regions 2 are arranged, for example.

At the apex of the protruding semiconductor region 2, a groove 10 that penetrates the n ⁺⁺ type emitter layer 4 and reaches the p ⁺ type contact layer 5 is provided. The p ⁺ -type contact layer 5 is exposed on the bottom surface of the groove 10. The emitter electrode (first main electrode) 8 is in contact with the n ⁺⁺ type emitter layer 4 and the p ⁺ type contact layer 5 through the groove 10, and is electrically connected to the p type base layer 3 through the p ⁺ type contact layer 5. It is connected to the. The emitter electrode 8 is electrically insulated from the first and second gate electrodes 7-1 and 7-2 by the interlayer insulating film 9.

A p-type collector layer (third semiconductor region) 12 is provided on the second main surface of the semiconductor substrate to be the n ⁻ -type drift layer 1. An n-type buffer layer 11 is provided between the n ⁻ -type drift layer 1 and the p-type collector layer 12. N-type buffer layer 11 is in contact with n ⁻ -type drift layer 1 and p-type collector layer 12. The impurity concentration of the n-type buffer layer 11 is higher than the impurity concentration of the n ⁻ -type drift layer 1. The collector electrode (second main electrode) 13 is in contact with the p-type collector layer 12.

  Next, the wiring structure between the first and second gate electrodes 7-1 and 7-2 and the internal resistance R will be described. FIG. 2 is a plan view showing a gate wiring structure of the semiconductor device of FIG. As shown in FIG. 2, a ring-shaped metal wiring (hereinafter referred to as a first gate ring) 14-1 for supplying a gate signal to the gate electrode is provided around the active region where the IGBT MOS structure is formed. Is provided. That is, the first gate ring 14-1 is a gate pad connected to a gate terminal (not shown). The first gate ring 14-1 surrounds the active region. The active region is a region through which a current flows when the semiconductor device is turned on, and is a region where the first and second gate electrodes 7-1 and 7-2 formed for each unit cell are arranged in a stripe shape. A ring-shaped metal wiring (hereinafter referred to as a second gate ring) 14-2 is provided so as to surround the first gate ring 14-1. The first gate ring 14-1 and the second gate ring 14-2 are made of, for example, aluminum silicon (AlSi).

  The first and second gate electrodes 7-1 and 7-2 are made of polysilicon. And each edge part of the longitudinal direction of the 1st gate electrode 7-1 formed for every unit cell is each connected to the 1st gate ring 14-1 via the contact hole 15-1. Each end in the longitudinal direction of the second gate electrode 7-2 formed for each unit cell is connected to the second gate ring 14-2 through a contact hole 15-2. An internal resistance R made of polysilicon (poly-Si) is connected to the first gate ring 14-1 and the second gate ring 14-2 through a contact hole 15-3. That is, the first gate ring 14-1 and the second gate ring 14-2 are connected to each other by the internal resistance R. For this reason, the second gate electrode 7-2 is electrically connected to the first gate ring 14-1 via the internal resistance R.

Next, the operation of the semiconductor device according to the embodiment shown in FIG. 1 will be described. The turn-on operation of the IGBT is as follows. In the off state, the collector electrode 13 is set to a high potential with respect to the emitter electrode 8 while the first gate electrode 7-1 is set to the same potential with respect to the emitter electrode 8. In this state, n ^- the reverse-biased junction between the type drift layer 1 and the p-type base layer 3, below its Gyaku耐voltage the n ^- depletion from the pn junction between the type drift layer 1 and the p-type base layer 3 And the IGBT is in a blocking state. In this state, when the first gate electrode 7-1 is set to a high potential with respect to the emitter electrode 8, charges start to be accumulated in the first gate electrode 7-1. At the same time, an n-channel region (not shown) inverted to the n-type is formed in a region of the p-type base layer 3 in contact with the gate insulating film 6.

When the n channel region is formed between the n ⁺⁺ type emitter layer 4 and the n ⁻ type drift layer 1, the reverse bias junction disappears in the path passing through the n channel region. Therefore, electrons are injected from emitter electrode 8 into n ⁻ type drift layer 1 through n ⁺⁺ type emitter layer 4 and the n channel region. When this electron injection occurs, the collector-side pn junction is forward-biased, so that holes, which are minority carriers, are injected from the p-type collector layer 12 into the n ⁻ -type drift layer 1. Holes the n ^- when injected into the mold drift layer 1, n ^- number electron density that is a carrier to keep the neutral conditions for carriers in type drift layer 1 is increased, n ^- -type drift layer 1 of the resistor Becomes lower. So-called conductivity modulation occurs. At this time, the voltage drop due to the current flowing between the collector electrode 13 and the emitter electrode 8 is the ON voltage.

Since the second gate electrode 7-2 has the same potential as the first gate electrode 7-1, both the first gate electrode 7-1 and the second gate electrode 7-2 are at the gate potential when turned on. As a result, an electron storage layer is formed on the portion of the p-type base layer 3 facing the first gate electrode 7-1 and the portion of the n ⁻ -type drift layer 1 facing the second gate electrode 7-2, The on-voltage is reduced (IE effect).

Also, turn-on, n ^- displacement current caused by the rise of the first main surface side of the potential of the type drift layer 1 is mainly the n ^- via -type drift layer 1 and the second gate electrode 7-2 facing gate drive It flows into a circuit (not shown). The reason is, n of the first gate electrode 7-1 ^- because smaller than the facing area between the type drift layer 1 ^- opposing area between -type drift layer 1 is n of the second gate electrode 7-2. Since the second gate electrode 7-2 is connected to the gate terminal via the internal resistance R, the displacement current flowing from the second gate electrode 7-2 to the gate drive circuit is reduced by passing through the internal resistance R. Become. Thereby, the potential difference between both ends of the gate resistance which is a direct current resistance from the gate terminal to the first gate electrode 7-1 can be reduced, and an increase in the gate voltage can be suppressed.

On the other hand, the turn-off operation of the IGBT is as follows. In the ON state, when the voltage between the emitter electrode 8 and the first and second gate electrodes 7-1 and 7-2 is equal to or lower than the threshold value, the charge accumulated in the first and second gate electrodes 7-1 and 7-2 Is discharged to the gate drive circuit through the gate resistor. Thereby, the channel region that has been inverted to the n-type in the p-type base layer 3 returns to the p-type, and the n-channel region disappears. Therefore, the supply of electrons from the emitter electrode 8 to the n ⁻ type drift layer 1 is eliminated. However, current continues to flow until the electrons and holes accumulated in the n ⁻ -type drift layer 1 are swept out to the collector electrode 13 and the emitter electrode 8, respectively, or recombine and disappear. Then, after electrons and holes in the n ⁻ -type drift layer 1 disappear, current does not flow, and the IGBT is turned off.

Next, a method for manufacturing the semiconductor device according to the embodiment shown in FIG. 1 will be described. 3 to 11 are cross-sectional views illustrating the semiconductor device in the middle of manufacture according to the embodiment. For example, a case of manufacturing (manufacturing) a field stop (FS) type IGBT having a 1200 V breakdown voltage class will be described as an example. First, for example, an n ⁻ type FZ silicon (FZ-Si) substrate 1-1 having a (100) plane as a first main surface and a specific resistance of about 60 Ωcm is prepared. Next, as shown in FIG. 3, a thermal oxide film 21 is grown on the first main surface of the FZ silicon substrate 1-1 to a thickness of about 350 mm by, for example, a thermal oxidation method.

Next, for example, phosphorus (P) ions are implanted into the first main surface of the FZ silicon substrate 1-1 through the thermal oxide film 21. The ion implantation conditions at this time may be, for example, a dose amount of 1.0 × 10 ¹³ cm ⁻² and an acceleration energy of 100 KeV. Next, phosphorus added to the first main surface of the FZ silicon substrate 1-1 by heat treatment is thermally diffused (drive-in), and the FZ silicon substrate 1 is formed on the surface layer of the first main surface of the FZ silicon substrate 1-1. Surface n layer 1-2 having an impurity concentration higher than −1 is formed.

Next, as shown in FIG. 4, for example, arsenic (As) ions are implanted into the first main surface of the FZ silicon substrate 1-1 through the thermal oxide film 21. The ion implantation conditions at this time may be, for example, a dose amount of 4.0 × 10 ¹⁵ cm ⁻² and an acceleration energy of 120 KeV. Next, arsenic introduced into the first main surface of the FZ silicon substrate 1-1 by thermal annealing is activated, and the surface n layer 1-2 has a surface layer closer to the thermal oxide film 21 than the surface n layer 1-2. Also, the n ⁺⁺ type emitter layer 4 having a high impurity concentration is formed with a thickness of about 0.2 μm.

Next, as shown in FIG. 5, for example, boron (B) ions are implanted into the first main surface of the FZ silicon substrate 1-1 through the thermal oxide film 21. The ion implantation conditions at this time may be, for example, a dose amount of 9.0 × 10 ¹³ cm ⁻² and an acceleration energy of 150 KeV. Next, boron introduced into the first main surface of the FZ silicon substrate 1-1 by thermal annealing is activated, and a p-type base layer 3 is formed between the surface n layer 1-2 and the n ⁺⁺ type emitter layer 4. Form. The portion of the FZ silicon substrate 1-1 excluding the p-type base layer 3 and the n ⁺⁺ type emitter layer 4, that is, the portion remaining as the n ⁻ layer of the FZ silicon substrate 1-1 and the surface n layer 1-2 are n ⁻ type. This is the drift layer 1.

Next, as shown in FIG. 6, a resist mask 23 having openings 22 opened in a stripe shape, for example, is formed on the surface of the thermal oxide film 21. In the opening 22 of the resist mask 23, the thermal oxide film 21 on the formation region of the p ⁺ -type contact layer 5 is exposed. Next, using the resist mask 23 as a mask, the thermal oxide film 21 is selectively removed by dry etching, for example, and the n ⁺⁺ type emitter layer 4 is selectively exposed.

Further, etching is performed using the resist mask 23 and the thermal oxide film 21 as a mask, and the silicon semiconductor exposed in the opening 22 is removed to a depth t1 of about 0.3 μm. As described above, since the n ⁺⁺ type emitter layer 4 is formed with a thickness of about 0.2 μm, the portion of the n ⁺⁺ type emitter layer 4 exposed to the opening 22 of the resist mask 23 is completely. Removed. As a result, a groove (hereinafter referred to as a first groove) 10 that penetrates the n ⁺⁺ type emitter layer 4 and reaches the p type base layer 3 is formed. The depth t1 of the first groove 10 may be a depth at which the p-type base layer 3 is exposed on the bottom surface of the first groove 10.

Next, as shown in FIG. 7, boron (B) ions are implanted into at least the bottom surface of the first groove 10 using the remaining resist mask 23 as a mask. The ion implantation conditions at this time may be, for example, a dose amount of 1.0 × 10 ¹⁵ cm ⁻² and an acceleration energy of 80 KeV. Next, boron introduced into the silicon semiconductor exposed in the first groove 10 by thermal annealing is activated, and a p ⁺ type contact layer 5 that penetrates the p type base layer 3 and reaches the surface n layer 1-2 is formed. .

The p ⁺ -type contact layer 5 is arranged in a stripe shape extending in a direction orthogonal to the direction in which the p ⁺ -type contact layers 5 are arranged, similarly to the planar shape of the opening 22 of the resist mask 23. In Figure 7, p ⁺ -type contact layer 5 is the side wall upper end portion in the vicinity of the first groove 10 is formed to overlap the end of the n ⁺⁺ type emitter layer 4, the n ⁺⁺ type emitter layer 4 The conductivity type of the portion where the p ⁺ -type contact layer 5 overlaps is maintained at the n-type. Thereafter, the resist mask 23 and the thermal oxide film 21 are completely removed.

Next, the silicon semiconductor on the first main surface side of the FZ silicon substrate 1-1 is selectively removed to a depth t2 of 1.5 μm, for example, by etching using, for example, an isotropic plasma etcher, and arranged in stripes. A plurality of second grooves 24 are formed. As shown in FIG. 8, the silicon semiconductor remaining between the adjacent second grooves 24 becomes the protruding semiconductor region 2. By the etching for forming the second groove 24, the n ⁺⁺ type emitter layer 4 and the p type base layer 3 between the adjacent protruding semiconductor regions 2 (second groove 24 portion) are completely removed.

  The depth of the silicon semiconductor removed by etching (the depth of the second groove 24) t2 is preferably 2 μm or less. The reason is that, when the depth of the silicon semiconductor removed by etching becomes larger than 2 μm, resist unevenness occurs in the subsequent patterning process, and the patterning accuracy deteriorates. By forming the second groove 24 by isotropic etching, the angle (recess angle) θ formed between the side wall of the second groove 24 and the bottom surface of the second groove 24 becomes an obtuse angle. The angle θ formed between the side wall of the second groove 24 and the bottom surface of the second groove 24 depends on the dose amount of boron for forming the p-type base layer 3, the annealing conditions for activating this boron, and the second It can be controlled by etching conditions for forming the groove 24.

  Next, the entire surface of the FZ silicon substrate 1-1 on the first main surface side, that is, the apex portion of the protruding semiconductor region 2, the side surface of the protruding semiconductor region 2 (side wall of the second groove 24), and the second are subjected to thermal oxidation treatment. A thermal oxide film (not shown) is grown on the bottom surface of the trench 24 as a sacrificial oxide film with a thickness of 1000 mm. Next, the sacrificial oxide film is removed, and processing damage on the surface of the silicon semiconductor due to etching is removed and planarized. Next, as shown in FIG. 9, the gate insulating film 6 is grown to a thickness of 800 mm on the entire first main surface side of the FZ silicon substrate 1-1 by, for example, thermal oxidation at 900.degree. Next, a polysilicon film to be the first and second gate electrodes 7-1 and 7-2 is grown on the gate insulating film 6 to a thickness of about 0.5 μm.

Next, the polysilicon film is selectively removed by photolithography to form first and second gate electrodes 7-1 and 7-2. The removal of the polysilicon film may be performed, for example, by etching using an isotropic plasma etcher. As a result, the first and second gate electrodes 7-1 and 7-2 are formed apart from each other in the unit cell. At this time, for example, the p-type base layer 3, n ⁺ formed inside the protruding semiconductor region 2 by heat treatment for forming the gate insulating film 6 and the first and second gate electrodes 7-1 and 7-2. ^{The +} type emitter layer 4 and the p ⁺ type contact layer 5 are diffused to increase the diffusion depth.

Next, as shown in FIG. 10, an HTO (High Temperature Oxide) film and a BPSG (Boron Phosphorate Silicate Glass) film are formed as an interlayer insulating film 9 so as to cover the first and second gate electrodes 7-1 and 7-2. Deposit sequentially. Then, the interlayer insulating film 9 and the gate insulating film 6 are selectively removed to form contact holes, and the n ⁺⁺ type emitter layer 4 and the p ⁺ type contact layer 5 are selectively exposed.

  Next, as shown in FIG. 11, an aluminum silicon electrode film is deposited as the emitter electrode 8 on the first main surface side of the FZ silicon substrate 1-1 by a physical vapor deposition (PVD) method such as sputtering. To do. Then, the emitter electrode 8 is patterned by photolithography to form a desired emitter wiring structure.

  As shown in FIG. 2, first and second gate rings 14-1 and 14-2 made of aluminum silicon are formed around the active region so as to surround the region where the MOS structure is formed. The first and second gate rings 14-1 and 14-2 may be formed simultaneously with the emitter electrode 8, for example. The first gate ring 14-1 (gate terminal) is, for example, in the longitudinal direction of the first gate electrodes 7-1 arranged in a stripe shape via a plurality of contact holes 15-1 formed in the interlayer insulating film 9. Connected directly to the end of the.

  The second gate ring 14-2 is, for example, at the end in the longitudinal direction of each of the second gate electrodes 7-2 arranged in a stripe shape via a plurality of contact holes 15-2 formed in the interlayer insulating film 9. Connected. The first and second gate rings 14-1 and 14-2 are connected via an internal resistor R made of polysilicon. Accordingly, each second gate electrode 7-2 is electrically connected to the first gate ring 14-1 (gate terminal) via the internal resistance R.

Next, using a spin coater, a polyimide film (not shown) is deposited as a surface protection film on the first main surface side of the FZ silicon substrate 1-1 to cover the emitter electrode 8. Then, the polyimide film is patterned by photolithography to form an electrode pad structure on the first main surface side of the FZ silicon substrate 1-1. Next, the second main surface of the FZ silicon substrate 1-1 is ground to reduce the thickness of the FZ silicon substrate 1-1 to, for example, 120 μm. Next, for example, protons (H ⁺ ) and boron ions are sequentially implanted into the ground second main surface of the FZ silicon substrate 1-1.

  Next, thermal annealing is performed at a temperature of 400 ° C. to activate the impurities implanted into the second main surface of the FZ silicon substrate 1-1. Thereby, as shown in FIG. 1, the n-type buffer layer 11 is formed on the surface layer of the second main surface of the FZ silicon substrate 1-1. A p-type collector layer 12 in contact with the n-type buffer layer 11 is formed in a portion shallower than the n-type buffer layer 11 on the surface layer of the second main surface of the FZ silicon substrate 1-1. Thereafter, the collector electrode 13 having a four-layer structure of, for example, aluminum-titanium (Ti) -nickel (Ni) -gold (Au) is formed by a physical vapor deposition method such as sputtering. By dicing the FZ silicon substrate 1-1 into a chip, the semiconductor device having the convex cell structure shown in FIG. 1 is completed.

  Next, in the above-described semiconductor device shown in FIG. 1, the relationship between the collector current time change rate di / dt and the gate resistance was verified. FIG. 12 is an explanatory diagram illustrating a time change rate of the collector current of the semiconductor device according to the embodiment. First, according to the embodiment, as shown in FIG. 1, a first gate electrode 7-1 directly connected to the gate terminal, and a second gate electrode 7-2 connected to the gate terminal via the internal resistance R (Hereinafter referred to as “Example”). As a comparison, a conventional IGBT having one gate electrode 107 covering most of the device surface as shown in FIG. 13 was fabricated (hereinafter referred to as a conventional example).

Both the embodiment and the conventional example are configured so that the resistance value of the gate resistance can be freely changed. In each of the example and the conventional example, the resistance value of the gate resistance was variously changed, and the time change rate di / dt of the collector current at the time of ON was measured. Conditions for measuring the time change rate di / dt of the collector current are as follows. The junction temperature Tj of the IGBT was set to 150 ° C. The collector current density Jc of IGBT was set to 150 A / cm ² . The saturation current Isat of the IGBT was set to 800 A / cm ² .

  From the results shown in FIG. 12, it was confirmed that the example has a smaller time change rate di / dt of the collector current at the time of ON than the conventional example. In addition, as in the conventional example, it was confirmed that the time change rate di / dt of the collector current can be further reduced by increasing the resistance value of the gate resistance in the example. Therefore, it was confirmed that when the first gate electrode 7-1 and the second gate electrode 7-2 are connected via the internal resistance R, the time change rate di / dt of the collector current is reduced.

As described above, according to the embodiment, by disposing the first and second gate electrodes apart from each other, the displacement current generated by the potential rise of the n ⁻ type drift layer at the time of ON is mainly used for the n ⁻ type drift. It can flow to the second gate electrode facing the layer. N of the first gate electrode ^- opposing area between -type drift layer n of the second gate electrode ^- smaller than the facing area between the type drift layer, the displacement current does not substantially flow into the first gate electrode. Thereby, it is possible to avoid a voltage drop in the gate resistance. Thereby, the time change rate di / dt of the collector current can be reduced.

  Furthermore, according to the embodiment, since the second gate electrode is connected to the gate terminal via the internal resistance, the current from the second gate electrode to the gate drive circuit hardly flows. Thereby, the displacement current flowing into the gate drive circuit via the second gate electrode at the time of ON can be reduced. Thereby, the potential difference between the both ends of the gate resistance caused by the displacement current can be reduced, and the increase in the gate voltage can be suppressed. Therefore, it is possible to suppress the collector current from increasing, and it is possible to reduce the time change rate di / dt of the collector current. Further, since the increase in collector current can be suppressed by reducing the potential difference between both ends of the gate resistance, the rate of increase in collector current can be controlled by changing the resistance value of the gate resistance.

  In addition, according to the embodiment, since the collector current time change rate di / dt can be reduced, for example, in an inverter circuit (not shown) configured by bridging IGBTs, it is connected in antiparallel to the opposite arm. Thus, the reverse recovery operation of the freewheeling diode that circulates the load current can be moderated, and the reverse recovery peak current can be reduced. As a result, the rate of time change di / dt of the reverse recovery peak current is reduced, and the surge voltage applied to the freewheeling diode can be suppressed, so that the generation of noise during reverse recovery of the freewheeling diode is reduced and the element is destroyed. Can be avoided.

  Further, according to the embodiment, since the electron emitter layer is formed in the semiconductor regions facing the first and second gate electrodes by adopting the convex emitter structure, the electron emitter layer is made larger than a general IGBT. The on-voltage can be reduced. Therefore, it is possible to control the ON voltage to be reduced and the time rate of change di / dt of the collector current to be reduced by the internal resistance provided between the second gate electrode and the gate terminal.

As described above, in the present invention, the first conductivity type is n-type and the second conductivity type is p-type. However, the present invention is similarly established when the first conductivity type is p-type and the second conductivity type is n-type. . In this case, holes that are majority carriers are accumulated in the portion of the p ⁻ -type drift layer facing the second gate electrode. In the present invention, an IGBT including a semiconductor region (protruded semiconductor region) protruding from the main surface of the semiconductor substrate by a groove provided in the main surface of the semiconductor substrate is described as an example. The present invention can also be applied to a planar structure IGBT which is not provided. Further, although an FS type IGBT is described as an example, the present invention can also be applied to a non-punch through (NPT) type or punch through (PT) type IGBT.

  As described above, the semiconductor device according to the present invention is useful for a power semiconductor device used for a power conversion device such as an inverter.

1 n ⁻ type drift layer (semiconductor substrate)
2 protruding semiconductor region 3 p-type base layer (first semiconductor region)
4 n ⁺⁺ type emitter layer (second semiconductor region)
5 p ⁺ type contact layer 6 gate insulating film 7-1 first gate electrode (first control electrode)
7-2 Second gate electrode (second control electrode)
8 Emitter electrode (first main electrode)
9 Interlayer insulating film 10 Groove 11 N-type buffer layer 12 p-type collector layer (third semiconductor region)
13 Collector electrode (second main electrode)
G Gate terminal R Internal resistance

Claims (6)

A first conductivity type semiconductor substrate;
A first semiconductor region of a projecting second conductivity type provided on the first main surface of the semiconductor substrate;
A second semiconductor region of a first conductivity type provided inside the first semiconductor region and spaced apart from the first main surface of the semiconductor substrate;
A first control electrode provided via a dielectric film on a portion of the first semiconductor region sandwiched between the second semiconductor region and the semiconductor substrate, to which a control signal is supplied;
A second control electrode having the same potential as the first control electrode, provided on the first main surface of the semiconductor substrate via an insulating film apart from the first control electrode;
A first main electrode in contact with the first semiconductor region and the second semiconductor region;
A third semiconductor region of a second conductivity type provided on the second main surface of the semiconductor substrate;
A second main electrode in contact with the third semiconductor region;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the second control electrode is electrically connected to the first control electrode via a resistor. A first metal layer surrounding the active region and in contact with the first control electrode provided to extend to the periphery of the active region;
The first metal layer is electrically connected to the end of the second control electrode provided so as to surround the first metal layer and extend to the periphery of the active region and through the resistor made of a metal film. Connected second metal layers,
The semiconductor device according to claim 2, further comprising:   The area of the portion of the first control electrode facing the first main surface of the semiconductor substrate is smaller than the area of the portion of the second control electrode facing the first main surface of the semiconductor substrate. The semiconductor device according to claim 1.   The semiconductor device according to claim 1, wherein the second control electrode is provided apart from the first semiconductor region. A plurality of the first semiconductor regions are provided on a first main surface of the semiconductor substrate;
The semiconductor device according to claim 1, wherein the first control electrode and the second control electrode are sandwiched between the adjacent first semiconductor regions.

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