WO2024070164A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2024070164A1
WO2024070164A1 PCT/JP2023/027048 JP2023027048W WO2024070164A1 WO 2024070164 A1 WO2024070164 A1 WO 2024070164A1 JP 2023027048 W JP2023027048 W JP 2023027048W WO 2024070164 A1 WO2024070164 A1 WO 2024070164A1
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WO
WIPO (PCT)
Prior art keywords
gate
region
trench
source
insulating film
Prior art date
Application number
PCT/JP2023/027048
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French (fr)
Japanese (ja)
Inventor
景 千賀
誠悟 森
翔悟 小川
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ローム株式会社
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Publication of WO2024070164A1 publication Critical patent/WO2024070164A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to a semiconductor device.
  • Patent document 1 discloses a semiconductor device including a semiconductor layer, a gate insulating film selectively formed on the surface of the semiconductor layer, a built-in resistor formed on the gate insulating film, an interlayer film formed on the surface of the semiconductor layer so as to cover the built-in resistor, a gate metal formed on the interlayer film and electrically connected to the built-in resistor, and a gate finger formed on the interlayer insulating film and electrically connected to the gate metal via the built-in resistor.
  • a relatively large source-drain voltage V DS /dt generated during switching may damage the gate insulating film between the semiconductor layer and the built-in resistor, resulting in an increase in leakage current.
  • the objective of one embodiment of the present disclosure is to provide a semiconductor device that can suppress leakage current.
  • An embodiment of the present disclosure provides a semiconductor device including a chip having a main surface and made of a semiconductor of a first conductivity type, a first region of a second conductivity type selectively formed on a surface layer portion of the main surface side of the chip, a trench gate structure formed on the main surface, a trench source structure formed on the main surface, an insulating film selectively formed on the main surface of the chip, an interlayer insulating film selectively arranged on the insulating film, a gate electrode arranged on the interlayer insulating film and applying a gate potential to the trench gate structure, a source electrode arranged on the interlayer insulating film and applying a source potential to the trench source structure, a gate connection conductive film formed on the insulating film and electrically connected to the gate electrode, and a contact region of a second conductivity type selectively formed on a surface layer portion of the first region and electrically connected to the source electrode, where the region of the contact region to which the source electrode is joined is defined as a source/contact junction region, and
  • This configuration helps to suppress leakage current.
  • FIG. 1 is a plan view showing a semiconductor device according to an embodiment.
  • FIG. 2 is a cross-sectional view taken along the line II-II shown in FIG.
  • FIG. 3 is a plan view showing the layout of the gate electrodes and source electrodes.
  • FIG. 4 is a plan view showing the layout of the first main surface.
  • FIG. 5 is an enlarged plan view showing the layout of the active regions.
  • FIG. 6 is an enlarged plan view showing the layout of the peripheral region.
  • FIG. 7 is a cross-sectional view taken along line VII-VII shown in FIG.
  • FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG.
  • FIG. 9 is a cross-sectional view taken along line IX-IX shown in FIG.
  • FIG. 1 is a plan view showing a semiconductor device according to an embodiment.
  • FIG. 2 is a cross-sectional view taken along the line II-II shown in FIG.
  • FIG. 3 is a plan view showing the layout
  • FIG. 10 is a cross-sectional view taken along line X-X shown in FIG.
  • FIG. 11 is a cross-sectional view taken along the line XI-XI shown in FIG.
  • FIG. 12 is a cross-sectional view taken along line XII-XII shown in FIG.
  • FIG. 13 is an enlarged plan view showing the layout of the termination region.
  • FIG. 14 is an enlarged plan view showing the layout of the gate resistors.
  • FIG. 15 is an enlarged plan view showing the inner part of the gate resistor.
  • FIG. 16 is an enlarged plan view showing the periphery of the gate resistor.
  • 17 is a cross-sectional view taken along line XVII-XVII shown in FIG.
  • FIG. 18 is a cross-sectional view taken along line XVIII-XVIII shown in FIG. 15.
  • FIG. 19 is a cross-sectional view taken along line XIX-XIX shown in FIG.
  • FIG. 20 is a cross-sectional view taken along the line XX-XX shown in FIG. 21 is a cross-sectional view taken along line XXI-XXI shown in FIG. 16.
  • FIG. 22 is a cross-sectional view taken along line XXII-XXII shown in FIG. 16.
  • FIG. 23 is an enlarged plan view showing a main part of the gate resistor.
  • FIG. 24 is an enlarged plan view showing the layout of the termination dummy structure.
  • FIG. 24 is an enlarged plan view showing the layout of the termination dummy structure.
  • FIG. 25 is a further enlarged plan view showing the layout of the termination dummy structure.
  • 26 is a cross-sectional view taken along line XXVI-XXVI shown in FIG. 25.
  • FIG. FIG. 27 is an electrical circuit diagram showing a connection form of the gate electrode and the gate resistor.
  • FIG. 28 is a cross-sectional view showing the structure of the outer periphery region.
  • FIG. 29 is a cross-sectional view taken along line XXIX-XXIX in FIG.
  • FIG. 30 is an enlarged plan view showing a part of the region E3 in FIG. 31 is a cross-sectional view taken along line XXXI-XXXI in FIG. 30.
  • this phrase includes a numerical value (shape) equal to the numerical value (shape) of the comparison target, as well as a numerical error (shape error) within a range of ⁇ 10% based on the numerical value (shape) of the comparison target.
  • the words “first,” “second,” “third,” etc. are used, but these are symbols added to the names of each structure to clarify the order of explanation, and are not added with the intention of limiting the names of each structure.
  • FIG. 1 is a plan view showing a semiconductor device 1 according to one embodiment.
  • FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. 1.
  • FIG. 3 is a plan view showing the layout of a gate electrode 100 and a source electrode 120.
  • FIG. 4 is a plan view showing the layout of a first main surface 3.
  • the semiconductor device 1 is a semiconductor switching device including a MISFET (Metal Insulator Semiconductor Field Effect Transistor).
  • MISFET Metal Insulator Semiconductor Field Effect Transistor
  • the semiconductor device 1 includes a chip 2 that includes a single crystal of a wide bandgap semiconductor and is formed in a hexahedral shape (specifically, a rectangular parallelepiped shape).
  • the semiconductor device 1 is a "wide bandgap semiconductor device.”
  • the chip 2 may also be referred to as a “semiconductor chip” or a "wide bandgap semiconductor chip.”
  • a wide bandgap semiconductor is a semiconductor that has a bandgap that exceeds the bandgap of Si (silicon). Examples of wide bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond).
  • the chip 2 is a "SiC chip” that includes hexagonal SiC single crystal as an example of a wide band gap semiconductor.
  • the semiconductor device 1 is a "SiC semiconductor device.”
  • the semiconductor device 1 may also be referred to as a "SiC-MISFET.”
  • the hexagonal SiC single crystal has multiple polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, and the like.
  • the chip 2 includes 4H-SiC single crystal, but the chip 2 may include other polytypes.
  • the chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4.
  • the first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed in a plan view from their normal direction Z (hereinafter simply referred to as "plan view").
  • the normal direction Z is also the thickness direction of the chip 2.
  • the first main surface 3 and the second main surface 4 are preferably formed by the c-plane of a SiC single crystal.
  • the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal
  • the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.
  • the first main surface 3 and the second main surface 4 may have an off angle inclined at a predetermined angle in a predetermined off direction with respect to the c-plane.
  • the off direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal.
  • the off angle may be greater than 0° and less than or equal to 10°.
  • the off angle is preferably less than or equal to 5°.
  • the first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects (specifically, perpendicular to) the first direction X.
  • the third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.
  • the first direction X may be the m-axis direction ([1-100] direction) of the SiC single crystal
  • the second direction Y may be the a-axis direction of the SiC single crystal.
  • the first direction X may be the a-axis direction of the SiC single crystal
  • the second direction Y may be the m-axis direction of the SiC single crystal.
  • the chip 2 may have a thickness of 5 ⁇ m or more and 200 ⁇ m or less.
  • the thickness of the chip 2 may be 150 ⁇ m or less, 100 ⁇ m or less, 80 ⁇ m or less, 50 ⁇ m or less, or 40 ⁇ m or less.
  • the first to fourth sides 5A to 5D may have a length of 0.5 mm or more and 10 mm or less in a plan view. It is preferable that the length of the first to fourth sides 5A to 5D is 1 mm or more.
  • the length of the first to fourth side surfaces 5A to 5D is 2 mm or more.
  • the chip 2 has a planar area of 1 mm square or more (preferably 2 mm square or more) and a thickness of 100 ⁇ m or less (preferably 50 ⁇ m or less) in a cross-sectional view.
  • the length of the first to fourth side surfaces 5A to 5D is set in the range of 4 mm or more and 6 mm or less.
  • the semiconductor device 1 includes an n-type first semiconductor region 6 formed in a region (surface layer) on the first main surface 3 side of the chip 2.
  • the first semiconductor region 6 is formed in a layer extending along the first main surface 3, and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D.
  • the first semiconductor region 6 is made of an epitaxial layer (specifically, a SiC epitaxial layer).
  • the first semiconductor region 6 may have a thickness of 1 ⁇ m or more and 50 ⁇ m or less.
  • the thickness of the first semiconductor region 6 is preferably 3 ⁇ m or more and 30 ⁇ m or less. It is particularly preferable that the thickness of the first semiconductor region 6 is 5 ⁇ m or more and 25 ⁇ m or less.
  • the semiconductor device 1 includes an n-type second semiconductor region 7 formed in a region (surface layer) on the second main surface 4 side within the chip 2.
  • the second semiconductor region 7 is formed in a layer extending along the second main surface 4, and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D.
  • the second semiconductor region 7 has a higher n-type impurity concentration than the first semiconductor region 6, and is electrically connected to the first semiconductor region 6.
  • the second semiconductor region 7 is made of a semiconductor substrate (specifically, a SiC semiconductor substrate). That is, the chip 2 has a layered structure including a semiconductor substrate and an epitaxial layer.
  • the second semiconductor region 7 may have a thickness of 1 ⁇ m or more and 200 ⁇ m or less.
  • the thickness of the second semiconductor region 7 may be 150 ⁇ m or less, 100 ⁇ m or less, 50 ⁇ m or less, or 40 ⁇ m or less.
  • the thickness of the second semiconductor region 7 may be 5 ⁇ m or more.
  • the thickness of the second semiconductor region 7 is preferably 10 ⁇ m or more.
  • the second semiconductor region 7 has a thickness that exceeds the thickness of the first semiconductor region 6.
  • the semiconductor device 1 includes an active surface 8, an outer surface 9, and first to fourth connecting surfaces 10A-10D formed on the first main surface 3.
  • the active surface 8, the outer surface 9, and the first to fourth connecting surfaces 10A-10D define an active plateau 11 on the first main surface 3.
  • the active surface 8 may be referred to as the "first surface portion,” the outer surface 9 as the “second surface portion,” and the first to fourth connecting surfaces 10A-10D as the "connecting surface portion.”
  • the active surface 8, the outer surface 9, and the first to fourth connecting surfaces 10A-10D (i.e., the active plateau 11) may be considered as components of the chip 2 (first main surface 3).
  • the active surface 8 is formed at a distance inward from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3.
  • the active surface 8 has a flat surface extending in the first direction X and the second direction Y.
  • the active surface 8 is formed by a c-plane (Si-plane).
  • the active surface 8 is formed in a quadrangle shape having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view.
  • the outer peripheral surface 9 is located outside the active surface 8 and is recessed from the active surface 8 in the thickness direction of the chip 2 (towards the second main surface 4). Specifically, the outer peripheral surface 9 is recessed to a depth less than the thickness of the first semiconductor region 6 so as to expose the first semiconductor region 6.
  • the outer peripheral surface 9 extends in a band shape along the active surface 8 in a plan view and is formed in a ring shape (specifically a square ring shape) surrounding the active surface 8.
  • the outer peripheral surface 9 has a flat surface extending in the first direction X and the second direction Y, and is formed approximately parallel to the active surface 8.
  • the outer peripheral surface 9 is formed by a c-plane (Si-plane).
  • the outer peripheral surface 9 is continuous with the first to fourth side surfaces 5A to 5D.
  • the outer peripheral surface 9 has a outer peripheral depth DO.
  • the outer peripheral depth DO may be 0.5 ⁇ m or more and 5 ⁇ m or less. It is preferable that the outer peripheral depth DO is 2.5 ⁇ m or less.
  • the first to fourth connection surfaces 10A to 10D extend in the normal direction Z and connect the active surface 8 and the outer peripheral surface 9.
  • the first connection surface 10A is located on the first side surface 5A side
  • the second connection surface 10B is located on the second side surface 5B side
  • the third connection surface 10C is located on the third side surface 5C side
  • the fourth connection surface 10D is located on the fourth side surface 5D side.
  • the first connection surface 10A and the second connection surface 10B extend in the first direction X and face the second direction Y.
  • the third connection surface 10C and the fourth connection surface 10D extend in the second direction Y and face the first direction X.
  • the first to fourth connection surfaces 10A to 10D may extend approximately vertically between the active surface 8 and the outer peripheral surface 9 so as to define a square-prism-shaped active plateau 11.
  • the first to fourth connection surfaces 10A to 10D may be inclined downward from the active surface 8 toward the outer peripheral surface 9 so as to define a square-prism-shaped active plateau 11.
  • the semiconductor device 1 includes an active plateau 11 that is defined in a protruding shape in the first semiconductor region 6 on the first main surface 3.
  • the active plateau 11 is formed only in the first semiconductor region 6, and is not formed in the second semiconductor region 7.
  • the semiconductor device 1 includes an active region 12, an outer peripheral region 13, a peripheral region 14, and a termination region 15.
  • the active region 12 is provided on the active surface 8.
  • the active region 12 is provided in the inner portion of the active surface 8 at a distance from the peripheral edge (first to fourth connection surfaces 10A to 10D) of the active surface 8.
  • the active region 12 is provided in a quadrangle shape having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view.
  • the outer peripheral region 13 is provided on the outer peripheral surface 9.
  • the outer peripheral region 13 is provided in a ring shape (specifically a quadrangular ring shape) surrounding the active surface 8 (active plateau 11) in a plan view.
  • the peripheral region 14 is provided on the active surface 8 in the region between the active region 12 and the outer peripheral region 13.
  • the peripheral region 14 is provided to sandwich the active region 12 from both sides in the first direction X, and extends in a strip shape in the second direction Y.
  • the peripheral region 14 includes a first peripheral region 14A and a second peripheral region 14B.
  • the first peripheral region 14A is provided on the third side surface 5C side (third connection surface 10C side) of the active region 12, and the second peripheral region 14B is provided on the fourth side surface 5D side (fourth connection surface 10D side) of the active region 12.
  • the termination region 15 is provided on the active surface 8 in the region between the active region 12 and the peripheral region 13.
  • the termination region 15 is provided to sandwich the active region 12 from both sides in the second direction Y, and extends in a strip shape in the first direction X.
  • the termination region 15 includes a first termination region 15A and a second termination region 15B.
  • the first termination region 15A is provided on the first side surface 5A side (first connection surface 10A side) of the active region 12, and the second termination region 15B is provided on the second side surface 5B side (second connection surface 10B side) of the active region 12.
  • the semiconductor device 1 includes a main surface insulating film 16 that covers the first main surface 3.
  • the main surface insulating film 16 selectively covers the active surface 8, the outer peripheral surface 9, and the first to fourth connection surfaces 10A to 10D.
  • the main surface insulating film 16 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the main surface insulating film 16 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the main surface insulating film 16 includes a silicon oxide film made of an oxide of the chip 2. In this embodiment, the main surface insulating film 16 is continuous with the first to fourth side surfaces 5A to 5D. Of course, the wall portion of the main surface insulating film 16 may be formed at a distance inward from the periphery of the outer peripheral surface 9, exposing the first semiconductor region 6 from the periphery of the outer peripheral surface 9.
  • FIG. 5 is an enlarged plan view showing the layout of the active region 12.
  • FIG. 6 is an enlarged plan view showing the layout of the peripheral region 14.
  • FIG. 7 is a cross-sectional view taken along line VII-VII shown in FIG. 5.
  • FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG. 5.
  • FIG. 9 is a cross-sectional view taken along line IX-IX shown in FIG. 6.
  • FIG. 10 is a cross-sectional view taken along line X-X shown in FIG. 6.
  • FIG. 11 is a cross-sectional view taken along line XI-XI shown in FIG. 6.
  • FIG. 12 is a cross-sectional view taken along line XII-XII shown in FIG. 6.
  • FIG. 6 the layout on the first peripheral region 14A side is shown. Since the layout on the second peripheral region 14B side is almost the same as the layout on the first peripheral region 14A side, the layout on the first peripheral region 14A side will be mainly described below.
  • the layout on the second peripheral region 14B side can be obtained by replacing "third connection surface 10C" with "fourth connection surface 10D" in the following description.
  • the semiconductor device 1 includes a p-type (second conductivity type) body region 17 formed in a surface layer portion of the first main surface 3 (active surface 8).
  • the body region 17 is formed at a distance from the bottom of the first semiconductor region 6 toward the active surface 8.
  • the body region 17 is formed in a layer extending along the active surface 8.
  • the body region 17 is formed over the entire active surface 8, and may be exposed from the first to fourth connection surfaces 10A to 10D.
  • the semiconductor device 1 includes an n-type source region 18 formed in a surface layer portion of the first main surface 3 (active surface 8) in the active region 12. Specifically, the source region 18 is formed in the surface layer portion of the body region 17 with a gap from the bottom of the body region 17 toward the active surface 8. The source region 18 is not formed in the peripheral region 14 or the termination region 15.
  • the source region 18 may be formed in the peripheral region 14 and the termination region 15 to the extent that it does not affect the control of the channel.
  • the source region 18 has a higher n-type impurity concentration than the first semiconductor region 6.
  • the source region 18 forms a channel of the MISFET together with the first semiconductor region 6 in the body region 17.
  • the semiconductor device 1 includes a plurality of trench gate structures 20 formed on the first main surface 3 (active surface 8) in the active region 12.
  • a gate potential VG is applied to the plurality of trench gate structures 20 as a first potential.
  • the plurality of trench gate structures 20 control the inversion and non-inversion of the channel in the body region 17.
  • the plurality of trench gate structures 20 are each formed in a band shape extending in the first direction X in a plan view, and are arranged at intervals in the second direction Y.
  • the multiple trench gate structures 20 are arranged inward of the active surface 8 at intervals from the periphery of the active surface 8. Specifically, the multiple trench gate structures 20 are arranged at intervals in the first direction X and the second direction Y from the first to fourth connection surfaces 10A to 10D.
  • the multiple trench gate structures 20 define an active region 12 in the inner part of the active surface 8, and at the same time define a peripheral region 14 and a termination region 15 together with the periphery of the active surface 8.
  • the multiple trench gate structures 20 penetrate the body region 17 and the source region 18 to reach the first semiconductor region 6.
  • the multiple trench gate structures 20 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.
  • the trench gate structure 20 has a first width W1 in the second direction Y and a first depth D1 in the normal direction Z.
  • the first width W1 may be 0.1 ⁇ m or more and 3 ⁇ m or less.
  • the first width W1 is preferably 0.5 ⁇ m or more and 2 ⁇ m or less.
  • the first depth D1 is less than the outer circumferential depth DO of the outer circumferential surface 9.
  • the first depth D1 may be 0.1 ⁇ m or more and 3 ⁇ m or less.
  • the first depth D1 is preferably 0.5 ⁇ m or more and 1.5 ⁇ m or less.
  • the trench gate structure 20 includes a gate trench 21, a gate insulating film 22, and a gate buried electrode 23.
  • the gate trench 21 is formed in the active surface 8 and defines the wall surface of the trench gate structure 20.
  • the gate insulating film 22 covers the wall surface of the gate trench 21 and is connected to the main surface insulating film 16 at the active surface 8.
  • the gate insulating film 22 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the gate insulating film 22 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the gate insulating film 22 contains a silicon oxide film made of an oxide of the chip 2.
  • the gate buried electrode 23 is buried in the gate trench 21 with the gate insulating film 22 in between, and faces the channel with the gate insulating film 22 in between.
  • the gate buried electrode 23 may contain conductive polysilicon.
  • the semiconductor device 1 includes a plurality of first trench source structures 25 formed in the first main surface 3 (active surface 8) in the active region 12.
  • a source potential VS is applied to the plurality of first trench source structures 25 as a second potential different from the first potential.
  • the source potential VS may be a reference potential (e.g., ground potential) that serves as an operating reference.
  • the multiple first trench source structures 25 are each disposed in a region between two adjacent trench gate structures 20.
  • the multiple first trench source structures 25 are arranged alternately with the multiple trench gate structures 20 in the second direction Y in a plan view, and are each formed in a strip shape extending in the first direction X.
  • the multiple first trench source structures 25 are drawn out from the active region 12 to the peripheral region 14.
  • the multiple first trench source structures 25 are exposed from at least one of the third connection surface 10C and the fourth connection surface 10D.
  • the multiple first trench source structures 25 penetrate both the third connection surface 10C and the fourth connection surface 10D and are exposed from both the third connection surface 10C and the fourth connection surface 10D.
  • the multiple first trench source structures 25 face the trench gate structure 20 in the second direction Y in the active region 12, and do not face the trench gate structure 20 in the second direction Y in the peripheral region 14.
  • the multiple first trench source structures 25 penetrate the body region 17 and source region 18 in the active region 12 to reach the first semiconductor region 6, and penetrate the body region 17 in the peripheral region 14.
  • the multiple first trench source structures 25 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.
  • the first trench source structure 25 has a second width W2 in the second direction Y and a second depth D2 in the normal direction Z.
  • the second width W2 is preferably approximately equal to the first width W1.
  • the second width W2 may be 0.1 ⁇ m or more and 3 ⁇ m or less.
  • the second width W2 is preferably 0.5 ⁇ m or more and 2 ⁇ m or less.
  • the second depth D2 is equal to or greater than the first depth D1. In this embodiment, the second depth D2 is greater than the first depth D1. It is preferable that the second depth D2 is 1.5 to 3 times the first depth D1. In this embodiment, the second depth D2 is approximately equal to the outer circumferential depth DO of the outer circumferential surface 9.
  • the second depth D2 may be 0.5 ⁇ m to 5 ⁇ m. It is particularly preferable that the second depth D2 is 2.5 ⁇ m or less.
  • the first trench source structure 25 is disposed in the second direction Y at a first distance I1 from the trench gate structure 20. It is preferable that the first distance I1 is 0.5 to 2 times the first width W1 (second width W2). It is particularly preferable that the first distance I1 is less than the first width W1 (second width W2).
  • the first distance I1 may be 0.1 ⁇ m to 2.5 ⁇ m. It is preferable that the first distance I1 is 0.5 ⁇ m to 1.5 ⁇ m.
  • the first trench source structure 25 includes a first source trench 26, a first source insulating film 27, and a first source buried electrode 28.
  • the first source trench 26 is formed in the active surface 8 and defines the wall surface of the first trench source structure 25.
  • the sidewall of the first source trench 26 is in communication with the third connection surface 10C and the fourth connection surface 10D.
  • the bottom wall of the first source trench 26 is in communication with the outer peripheral surface 9.
  • the first source insulating film 27 covers the wall surface of the first source trench 26 and is connected to the main surface insulating film 16 at the active surface 8.
  • the first source insulating film 27 is connected to the main surface insulating film 16 at the communicating portion of the third connection surface 10C, the communicating portion of the fourth connection surface 10D, and the communicating portion of the outer peripheral surface 9.
  • the first source insulating film 27 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the first source insulating film 27 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the first source insulating film 27 includes a silicon oxide film made of an oxide of the chip 2.
  • the first source buried electrode 28 is buried in the first source trench 26 with the first source insulating film 27 in between.
  • the first source buried electrode 28 may include conductive polysilicon.
  • the semiconductor device 1 includes a plurality of second trench source structures 30 formed in the first main surface 3 (active surface 8) in the peripheral region 14.
  • a source potential VS is applied to the plurality of second trench source structures 30.
  • the plurality of second trench source structures 30 are arranged in a region between the periphery (third connection surface 10C) of the active surface 8 and the plurality of trench gate structures 20.
  • the plurality of second trench source structures 30 are arranged in a region between two first trench source structures 25 adjacent to each other in the second direction Y, and face the plurality of trench gate structures 20 in a one-to-one correspondence in the first direction X.
  • the multiple second trench source structures 30 are each formed in a band shape extending in the first direction X in a plan view. In this embodiment, the multiple second trench source structures 30 penetrate the third connection surface 10C and are exposed from the third connection surface 10C. The multiple second trench source structures 30 penetrate the body region 17 to reach the first semiconductor region 6. The multiple second trench source structures 30 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.
  • the second trench source structure 30 has a third width W3 in the second direction Y and a third depth D3 in the normal direction Z.
  • the third width W3 is preferably approximately equal to the first width W1 of the trench gate structure 20.
  • the third width W3 is preferably approximately equal to the second width W2 of the first trench source structure 25.
  • the third width W3 may be 0.1 ⁇ m or more and 3 ⁇ m or less.
  • the third width W3 is preferably 0.5 ⁇ m or more and 2 ⁇ m or less.
  • the third depth D3 is equal to or greater than the first depth D1 of the trench gate structure 20. In this embodiment, the third depth D3 is greater than the first depth D1. It is preferable that the third depth D3 is equal to or greater than 1.5 times and equal to or less than 3 times the first depth D1. In this embodiment, the third depth D3 is approximately equal to the second depth D2 of the first trench source structure 25. The third depth D3 is approximately equal to the outer circumferential depth DO of the outer circumferential surface 9. The third depth D3 may be equal to or greater than 0.5 ⁇ m and equal to or less than 5 ⁇ m. It is particularly preferable that the third depth D3 is equal to or less than 2.5 ⁇ m.
  • the second trench source structure 30 is disposed in the second direction Y at a second distance I2 from the first trench source structure 25.
  • the second distance I2 is preferably 0.5 to 2 times the second width W2 (third width W3). It is particularly preferable that the second distance I2 is less than the second width W2 (third width W3). It is preferable that the second distance I2 is approximately equal to the first distance I1.
  • the second distance I2 may be 0.1 ⁇ m to 2.5 ⁇ m. It is preferable that the second distance I2 is 0.5 ⁇ m to 1.5 ⁇ m.
  • the second trench source structure 30 is disposed in the first direction X at a third interval I3 from the trench gate structure 20.
  • the third interval I3 is preferably 0.5 to 2 times the first width W1 (third width W3).
  • the third interval I3 is preferably 0.5 to 2 times the first interval I1 (second interval I2). It is particularly preferable that the third interval I3 is 1.5 times or less the first interval I1 (second interval I2).
  • the third interval I3 may be approximately equal to the first interval I1 (second interval I2).
  • the third interval I3 may be 0.1 ⁇ m to 2.5 ⁇ m. It is preferable that the third interval I3 is 0.5 ⁇ m to 1.5 ⁇ m.
  • the second trench source structure 30 includes a second source trench 31, a second source insulating film 32, and a second source buried electrode 33.
  • the second source trench 31 is formed in the active surface 8 and defines the wall surface of the second trench source structure 30.
  • the side wall of the second source trench 31 is connected to the third connection surface 10C.
  • the bottom wall of the second source trench 31 is connected to the outer peripheral surface 9.
  • the second source insulating film 32 covers the wall surface of the second source trench 31 and is connected to the main surface insulating film 16 at the active surface 8.
  • the second source insulating film 32 is connected to the main surface insulating film 16 at the communicating portion of the third connection surface 10C and the communicating portion of the outer peripheral surface 9.
  • the second source insulating film 32 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the second source insulating film 32 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the second source insulating film 32 includes a silicon oxide film made of an oxide of the chip 2.
  • the second source buried electrode 33 is buried in the second source trench 31 with the second source insulating film 32 in between.
  • the second source buried electrode 33 may include conductive polysilicon.
  • the semiconductor device 1 includes a plurality of p-type first well regions 35 formed in the active region 12 in a region along the plurality of trench gate structures 20.
  • the first well regions 35 have a higher p-type impurity concentration than the body region 17.
  • the p-type impurity concentration of the first well regions 35 may be lower than that of the body region 17.
  • the multiple first well regions 35 cover the wall surfaces of the corresponding trench gate structures 20 at intervals from the adjacent first trench source structures 25, and are electrically connected to the body region 17 at the surface portion of the active surface 8.
  • the multiple first well regions 35 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 with a part of the first semiconductor region 6 in between.
  • the multiple first well regions 35 form pn junctions with the first semiconductor region 6.
  • the semiconductor device 1 includes a plurality of p-type second well regions 36 formed in the active region 12 and the peripheral region 14 in regions along the plurality of first trench source structures 25.
  • the second well regions 36 have a higher p-type impurity concentration than the body region 17.
  • the p-type impurity concentration of the second well regions 36 may be lower than the body region 17. It is preferable that the p-type impurity concentration of the second well regions 36 is approximately equal to the p-type impurity concentration of the first well region 35.
  • the second well regions 36 cover the walls of the corresponding first trench source structures 25 at intervals from the adjacent trench gate structures 20 and are electrically connected to the body region 17 at the surface portion of the active surface 8.
  • the second well regions 36 cover the walls of the corresponding first trench source structures 25 in the active region 12 and the peripheral region 14 and are exposed from the third connection surface 10C and the fourth connection surface 10D.
  • the multiple second well regions 36 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 across a portion of the first semiconductor region 6.
  • the bottoms of the multiple second well regions 36 are located on the bottom side of the first semiconductor region 6 relative to the depth positions of the bottoms of the multiple first well regions 35.
  • the multiple second well regions 36 form pn junctions with the first semiconductor region 6.
  • the semiconductor device 1 includes a plurality of p-type third well regions 37 formed in the peripheral region 14 in a region along the plurality of second trench source structures 30.
  • the third well region 37 has a higher p-type impurity concentration than the body region 17.
  • the p-type impurity concentration of the third well region 37 may be lower than the body region 17. It is preferable that the p-type impurity concentration of the third well region 37 is approximately equal to the p-type impurity concentration of the first well region 35 (second well region 36).
  • the multiple third well regions 37 cover the walls of the corresponding second trench source structures 30 at intervals from the adjacent trench gate structures 20 and the adjacent first trench source structures 25, and are electrically connected to the body region 17 in the surface portion of the active surface 8.
  • the third well regions 37 may be integrated with the first well region 35 in the region between the trench gate structures 20 and the second trench source structures 30.
  • the multiple third well regions 37 are exposed from the third connection surface 10C.
  • the multiple third well regions 37 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 across a portion of the first semiconductor region 6.
  • the bottoms of the multiple third well regions 37 are located on the bottom side of the first semiconductor region 6 relative to the depth position of the bottoms of the multiple first well regions 35.
  • the bottoms of the multiple third well regions 37 are formed at approximately the same depth as the bottoms of the multiple second well regions 36.
  • the multiple third well regions 37 form pn junctions with the first semiconductor region 6.
  • the semiconductor device 1 includes a plurality of first contact regions 38 of p-type formed in the active region 12 in a region along the plurality of first trench source structures 25.
  • the first contact regions 38 have a higher p-type impurity concentration than the body region 17.
  • the p-type impurity concentration of the first contact regions 38 is higher than that of the second well region 36.
  • the multiple first contact regions 38 cover the wall surfaces of the corresponding first trench source structures 25 in the corresponding second well regions 36.
  • the multiple first contact regions 38 are formed in a one-to-many correspondence with each first trench source structure 25.
  • the multiple first contact regions 38 are formed at intervals along the corresponding first trench source structures 25.
  • the multiple first contact regions 38 are pulled out from within the corresponding second well region 36 along the wall surface of the corresponding first trench source structure 25 to the surface layer of the body region 17 and exposed from the active surface 8.
  • the multiple first contact regions 38 are formed in the active region 12 and are not formed in the peripheral region 14. In other words, the multiple first contact regions 38 face the trench gate structure 20 in the second direction Y, but do not face the second trench source structure 30 in the second direction Y.
  • the first contact regions 38 are not formed in the third well region 37.
  • the multiple first contact regions 38 are each formed in a band shape extending in the first direction X in a plan view.
  • the length of the multiple first contact regions 38 in the first direction X is preferably equal to or greater than the second width W2 of the first trench source structure 25.
  • the length of the multiple first contact regions 38 is preferably greater than the distance between two adjacent first contact regions 38 in the first direction X.
  • the first contact regions 38 along one first trench source structure 25 face the first contact regions 38 along the other first trench source structure 25 in the second direction Y.
  • the first contact regions 38 are arranged in a matrix shape with gaps in between in the first direction X and the second direction Y as a whole when viewed in a plan view.
  • the first contact regions 38 along one first trench source structure 25 may be arranged offset in the first direction X so as to face the second direction Y in a region between the first contact regions 38 along another first trench source structure 25.
  • the first contact regions 38 may be arranged in a staggered manner with gaps in the first direction X and the second direction Y as a whole in a plan view.
  • the semiconductor device 1 includes a plurality of gate connection electrode films 39 that cover the ends of the plurality of trench gate structures 20 on the first main surface 3 (active surface 8) in the active region 12. Specifically, the plurality of gate connection electrode films 39 are disposed on the main surface insulating film 16. The plurality of gate connection electrode films 39 cover the inner portions of the plurality of trench gate structures 20 and the ends of the corresponding trench gate structures 20 at intervals from the plurality of first trench source structures 25 and the plurality of second trench source structures 30.
  • the multiple gate connection electrode films 39 are arranged alternately with the multiple first trench source structures 25 in the second direction Y in a planar view.
  • the multiple gate connection electrode films 39 are each formed in a strip shape extending in the first direction X.
  • the multiple gate connection electrode films 39 do not face the multiple second trench source structures 30 in the second direction Y in a planar view. Below, one gate connection electrode film 39 will be described.
  • the gate connection electrode film 39 is connected to the corresponding gate buried electrode 23 in the portion covering the corresponding trench gate structure 20.
  • the gate connection electrode film 39 is formed integrally with the corresponding gate buried electrode 23.
  • the gate connection electrode film 39 is made up of a portion of the gate buried electrode 23 that is pulled out in the form of a film onto the active surface 8 (main surface insulating film 16).
  • the gate connection electrode film 39 may be formed separately from the gate buried electrode 23.
  • the gate connection electrode film 39 has an electrode surface 39a extending along the active surface 8.
  • the gate connection electrode film 39 is formed in a tapered shape (quadratic pyramid shape) from the active surface 8 towards the electrode surface 39a in a cross-sectional view.
  • the electrode surface 39a is preferably formed to be wider than the trench gate structure 20 in the second direction Y.
  • the electrode surface 39a preferably has a portion facing the trench gate structure 20 in the normal direction Z, and a portion facing the area outside the trench gate structure 20 (i.e., the main surface insulating film 16) in the normal direction Z.
  • the gate connection electrode film 39 includes conductive polysilicon.
  • the gate connection electrode film 39 has an electrode thickness TE.
  • the electrode thickness TE is preferably 0.5 times or more the first width W1 of the trench gate structure 20 (the second width W2 of the first trench source structure 25).
  • the electrode thickness TE is preferably equal to or less than the peripheral depth DO of the peripheral surface 9.
  • the electrode thickness TE is preferably equal to or less than the second depth D2 of the first trench source structure 25. It is particularly preferable that the electrode thickness TE is less than the second depth D2 (peripheral depth DO).
  • the electrode thickness TE is preferably equal to or less than the first depth D1 of the trench gate structure 20. It is particularly preferable that the electrode thickness TE is less than the first depth D1.
  • the electrode thickness TE may be 0.05 ⁇ m or more and 2.5 ⁇ m or less. It is preferable that the electrode thickness TE is 0.5 ⁇ m or more and 1.5 ⁇ m or less. Of course, the electrode thickness TE may be greater than the first depth D1. Also, the electrode thickness TE may be greater than the outer periphery depth DO (second depth D2).
  • FIG. 13 is an enlarged plan view showing the layout of the termination region 15 (first termination region 15A).
  • FIG. 14 is an enlarged plan view showing the layout of the gate resistor 40.
  • FIG. 15 is an enlarged plan view showing the inner part of the gate resistor 40.
  • FIG. 16 is an enlarged plan view showing the peripheral part of the gate resistor 40.
  • FIG. 17 is a cross-sectional view taken along line XVII-XVII shown in FIG. 15.
  • FIG. 18 is a cross-sectional view taken along line XVIII-XVIII shown in FIG. 15.
  • FIG. 19 is a cross-sectional view taken along line XIX-XIX shown in FIG. 16.
  • FIG. 20 is a cross-sectional view taken along line XX-XX shown in FIG. 16.
  • FIG. 21 is a cross-sectional view taken along line XXI-XXI shown in FIG. 16.
  • FIG. 22 is a cross-sectional view taken along line XXII-XXII shown in FIG. 16.
  • FIG. 23 is an enlarged plan view showing a main portion of gate resistor 40.
  • the semiconductor device 1 includes a gate resistor 40 formed on the first main surface 3 (active surface 8) in the first termination region 15A.
  • the gate resistor 40 is incorporated in the chip 2 (first termination region 15A) as a resistor electrically connected to the gate (trench gate structure 20) of the MISFET.
  • the gate resistor 40 is disposed in a region on the first side surface 5A side (first connection surface 10A side) of the active region 12, and faces the active region 12 in the second direction Y.
  • the gate resistor 40 is disposed at a distance from the peripheral region 14 in the first direction X so as not to face the peripheral region 14 in the second direction Y.
  • the gate resistor 40 is disposed between the center of the first side surface 5A (first connection surface 10A) and the active region 12.
  • the gate resistor 40 includes at least one (in this embodiment, multiple) trench resistor structures 41 formed on the first main surface 3 (active surface 8) in the first termination region 15A.
  • a gate potential VG is applied as a first potential to the multiple trench resistor structures 41, but they do not contribute to channel control.
  • the multiple trench resistance structures 41 are each formed in a band shape extending in the first direction X, and are arranged at intervals in the second direction Y.
  • the multiple trench resistance structures 41 penetrate the body region 17 to reach the first semiconductor region 6.
  • the multiple trench resistance structures 41 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.
  • the multiple trench resistance structures 41 include multiple first trench resistance structures 42 and multiple second trench resistance structures 43.
  • the multiple first trench resistance structures 42 are formed on the active surface 8 at intervals from the periphery of the active surface 8 in the first termination region 15A.
  • the multiple first trench resistance structures 42 are each formed in a band shape extending in the first direction X, and are arranged at intervals in the second direction Y.
  • the multiple first trench resistance structures 42 face the first trench source structure 25 in the second direction Y.
  • the multiple first trench resistance structures 42 are arranged at intervals from the second trench source structure 30 in the first direction X so as not to face the second trench source structure 30 in the second direction Y.
  • the multiple first trench resistance structures 42 penetrate the body region 17 to reach the first semiconductor region 6.
  • the multiple first trench resistance structures 42 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.
  • the first trench resistor structure 42 has a first resistor length L1 in the first direction X.
  • the first resistor length L1 is arbitrary and is appropriately determined according to the resistance value to be achieved.
  • the first trench resistor structure 42 has a fourth width W4 in the second direction Y and a fourth depth D4 in the normal direction Z. It is preferable that the fourth width W4 is approximately equal to the first width W1 of the trench gate structure 20.
  • the fourth width W4 may be 0.1 ⁇ m or more and 3 ⁇ m or less. It is preferable that the fourth width W4 is 0.5 ⁇ m or more and 2 ⁇ m or less.
  • the fourth depth D4 is less than the second depth D2 of the first trench source structure 25.
  • the fourth depth D4 is less than the outer circumferential depth DO of the outer circumferential surface 9. It is preferable that the fourth depth D4 is approximately equal to the first depth D1 of the trench gate structure 20.
  • the fourth depth D4 may be greater than or equal to 0.1 ⁇ m and less than or equal to 3 ⁇ m. It is preferable that the fourth depth D4 is greater than or equal to 0.5 ⁇ m and less than or equal to 1.5 ⁇ m.
  • the innermost first trench resistance structure 42 on the active region 12 side is disposed at the aforementioned first interval I1 from the outermost first trench source structure 25 so as to be adjacent to the outermost first trench source structure 25 in the second direction Y.
  • the innermost first trench resistance structure 42 is disposed at an interval in the first direction X from the outermost second trench source structure 30 so as not to be adjacent to the outermost second trench source structure 30 in the second direction Y.
  • the first trench resistance structure 42 includes a first trench 44, a first insulating film 45, and a first buried electrode 46.
  • the first buried electrode 46 may be referred to as a "first buried resistor.”
  • the first trench 44 is formed in the active surface 8 and defines the wall surface of the first trench resistance structure 42.
  • the first insulating film 45 covers the wall surface of the first trench 44 and is connected to the main surface insulating film 16 at the active surface 8.
  • the first insulating film 45 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the first insulating film 45 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the first insulating film 45 includes a silicon oxide film made of an oxide of the chip 2.
  • the first buried electrode 46 is buried in the first trench 44 with the first insulating film 45 in between.
  • the first buried electrode 46 may include conductive polysilicon.
  • the multiple second trench resistance structures 43 are formed on the active surface 8 at intervals from the periphery of the active surface 8 in the first termination region 15A.
  • the multiple second trench resistance structures 43 are each disposed in a region between two adjacent first trench resistance structures 42.
  • the multiple second trench resistance structures 43 are arranged alternately with the multiple first trench resistance structures 42 in the second direction Y.
  • the multiple second trench resistance structures 43 are each formed in a band shape extending in the first direction X in a plan view.
  • the multiple second trench resistance structures 43 face the trench gate structure 20 and the first trench source structure 25 in the second direction Y.
  • the multiple second trench resistance structures 43 are arranged at intervals from the second trench source structure 30 in the first direction X so as not to face the second trench source structure 30 in the second direction Y.
  • the multiple second trench resistance structures 43 penetrate the body region 17 to reach the first semiconductor region 6.
  • the multiple second trench resistance structures 43 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.
  • the second trench resistance structure 43 has a second resistance length L2 in the first direction X.
  • the second resistance length L2 is arbitrary and is appropriately determined according to the resistance value to be achieved.
  • the second resistance length L2 is less than the first resistance length L1 of the first trench resistance structure 42.
  • both ends of the second trench resistance structure 43 are set back inward from both ends of the first trench resistance structure 42.
  • the second resistance length L2 may be approximately equal to the first resistance length L1.
  • the second resistance length L2 may be greater than the first resistance length L1.
  • the second trench resistor structure 43 has a fifth width W5 in the second direction Y and a fifth depth D5 in the normal direction Z.
  • the fifth width W5 is preferably approximately equal to the fourth width W4 of the first trench resistor structure 42.
  • the fifth width W5 is preferably approximately equal to the second width W2 of the first trench source structure 25 (the first width W1 of the trench gate structure 20).
  • the fifth width W5 may be 0.1 ⁇ m or more and 3 ⁇ m or less.
  • the fifth width W5 is preferably 0.5 ⁇ m or more and 2 ⁇ m or less.
  • the fifth depth D5 is equal to or greater than the fourth depth D4 of the first trench resistor structure 42 (the first depth D1 of the trench gate structure 20). In this embodiment, the fifth depth D5 is greater than the fourth depth D4 (the first depth D1). The fifth depth D5 is preferably equal to or greater than 1.5 times and equal to or less than 3 times the fourth depth D4 (the first depth D1). The fifth depth D5 is preferably approximately equal to the second depth D2 of the first trench source structure 25. The fifth depth D5 is approximately equal to the outer circumferential depth DO of the outer circumferential surface 9. The fifth depth D5 may be equal to or greater than 0.5 ⁇ m and equal to or less than 5 ⁇ m. It is particularly preferable that the fifth depth D5 is equal to or less than 2.5 ⁇ m.
  • the second trench resistance structure 43 is disposed in the second direction Y at a fourth interval I4 from the first trench resistance structure 42.
  • the fourth interval I4 is preferably 0.5 to 2 times the fourth width W4 (fifth width W5). It is particularly preferable that the fourth interval I4 is less than the fourth width W4 (fifth width W5). It is preferable that the fourth interval I4 is approximately equal to the first interval I1 between the trench gate structure 20 and the first trench source structure 25.
  • the fourth interval I4 may be 0.1 ⁇ m to 2.5 ⁇ m. It is preferable that the fourth interval I4 is 0.5 ⁇ m to 1.5 ⁇ m.
  • the second trench resistance structure 43 includes a second trench 47, a second insulating film 48, and a second buried electrode 49.
  • the second buried electrode 49 may be referred to as a "second buried resistor.”
  • the second trench 47 is formed in the active surface 8 and defines the wall surface of the second trench resistance structure 43.
  • the second insulating film 48 covers the wall surface of the second trench 47 and is connected to the main surface insulating film 16 at the active surface 8.
  • the second insulating film 48 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the second insulating film 48 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the second insulating film 48 includes a silicon oxide film made of an oxide of the chip 2.
  • the second buried electrode 49 is buried in the second trench 47 with the second insulating film 48 in between.
  • the second buried electrode 49 may include conductive polysilicon.
  • the gate resistor 40 includes a resistive film 50 covering at least one (in this embodiment, multiple) trench resistor structures 41 on the first main surface 3 (active surface 8).
  • the resistive film 50 includes at least one of a conductive polysilicon film and an alloy crystal film.
  • the alloy crystal film includes alloy crystals composed of a metal element and a nonmetal element.
  • the alloy crystal film may include at least one of a CrSi film, a CrSiN film, a CrSiO film, a TaN film, and a TiN film.
  • the resistive film 50 includes conductive polysilicon.
  • the resistive film 50 is disposed on the main surface insulating film 16, and has a portion covering the active surface 8 and a portion covering the multiple trench resistance structures 41. In this form, the resistive film 50 covers all of the multiple trench resistance structures 41 in the short direction (second direction Y) of the multiple trench resistance structures 41.
  • the resistive film 50 is connected to the first buried electrode 46 and the second buried electrode 49 in the portion covering the multiple trench resistance structures 41.
  • the resistive film 50 is formed integrally with the first buried electrode 46 and the second buried electrode 49.
  • the resistive film 50 is made up of a portion of the first buried electrode 46 and a portion of the second buried electrode 49 that are pulled out in a film shape onto the active surface 8 (main surface insulating film 16).
  • the resistive film 50 may be formed separately from the first buried electrode 46 and the second buried electrode 49.
  • the resistive film 50 faces the trench gate structure 20 and the first trench source structure 25 in the second direction Y.
  • the resistive film 50 is spaced apart from the second trench source structure 30 in the first direction X so as not to face the second trench source structure 30 in the second direction Y.
  • the resistive film 50 is formed in a band shape extending in the first direction X in a plan view.
  • the planar shape of the resistive film 50 is arbitrary and is adjusted appropriately according to the resistance value to be achieved.
  • the resistive film 50 preferably has a third resistance length L3 in the first direction X that is shorter than the first resistance length L1 of the first trench resistance structure 42 and the second resistance length L2 of the second trench resistance structure 43.
  • the resistive film 50 preferably covers the inner portions of the multiple trench resistance structures 41 with a gap inward from both ends of the multiple trench resistance structures 41 in the longitudinal direction (first direction X) of the multiple trench resistance structures 41.
  • the resistive film 50 preferably exposes both ends of the multiple first trench resistance structures 42 and both ends of the multiple second trench resistance structures 43.
  • the resistive film 50 may cover the entire area of the multiple trench resistance structures 41. That is, the third resistance length L3 may be greater than the first resistance length L1.
  • the resistive film 50 may also expose both ends of the multiple first trench resistance structures 42 and cover both ends of the multiple second trench resistance structures 43. That is, the third resistance length L3 may be smaller than the first resistance length L1 and greater than the second resistance length L2.
  • the resistive film 50 has a resistive thickness TR in the normal direction Z.
  • the resistive thickness TR is adjusted as appropriate according to the resistance value to be achieved.
  • the resistance value of the resistive film 50 is adjusted by increasing or decreasing the resistive thickness TR and increasing or decreasing the third resistive length L3. It is preferable that the resistive thickness TR be 0.5 or more times the aforementioned fourth width W4 (fifth width W5).
  • the resistor thickness TR satisfies this condition, when a conductive polysilicon film is formed by CVD to fill the first trench 44 and the second trench 47 and cover the first main surface 3 (active surface 8), the first buried electrode 46, the second buried electrode 49, and the resistor film 50 can be formed using a portion of the conductive polysilicon film. It is preferable that the resistor thickness TR is equal to or less than the aforementioned outer periphery depth DO. It is preferable that the resistor thickness TR is equal to or less than the aforementioned fifth depth D5 (the aforementioned second depth D2).
  • the resistor thickness TR is less than the fifth depth D5. It is preferred that the resistor thickness TR is less than the aforementioned fourth depth D4 (first depth D1). It is particularly preferred that the resistor thickness TR is less than the fourth depth D4. It is preferred that the resistor thickness TR is approximately equal to the aforementioned electrode thickness TE.
  • the resistor thickness TR may be 0.05 ⁇ m or more and 2.5 ⁇ m or less. It is preferred that the resistor thickness TR is 0.5 ⁇ m or more and 1.5 ⁇ m or less.
  • the resistor thickness TR may be greater than the fourth depth D4. Also, the resistor thickness TR may be greater than or equal to the outer circumferential depth DO (fifth depth D5). Also, when the resistor film 50 is made of an alloy crystal film, the resistor thickness TR may be less than the fourth depth D4. In this case, the resistor thickness TR may be greater than or equal to 0.1 nm and less than or equal to 100 nm.
  • the semiconductor device 1 includes a dummy structure 55 formed on the first main surface 3 (active surface 8) in the first termination region 15A.
  • the dummy structure 55 is incorporated in the active surface 8 (first termination region 15A) for one purpose, which is to reduce localized electric field concentration in the vicinity of the gate resistor 40 and improve the breakdown voltage (e.g., breakdown voltage).
  • the presence or absence of the dummy structure 55 is optional, and a configuration without the dummy structure 55 may be adopted.
  • the dummy structure 55 includes a first dummy structure 56 and a second dummy structure 57.
  • the first dummy structure 56 is arranged in a region on the third side surface 5C side (third connection surface 10C side) of the gate resistor 40.
  • the first dummy structure 56 faces the gate resistor 40 in the first direction X, and faces the active region 12 and the first peripheral region 14A in the second direction Y.
  • the second dummy structure 57 is arranged in a region on the fourth side surface 5D side (fourth connection surface 10D side) of the gate resistor 40.
  • the second dummy structure 57 faces the first dummy structure 56 across the gate resistor 40 in the first direction X, and faces the active region 12 and the second peripheral region 14B in the second direction Y. Since the layout of the second dummy structure 57 is substantially similar to the layout of the first dummy structure 56, the configuration of the first dummy structure 56 will be described below.
  • the layout of the second dummy structure 57 can be obtained by replacing "third connection surface 10C" with "fourth connection surface 10D" in the following description.
  • the first dummy structure 56 includes at least one (in this embodiment, multiple) dummy trench structures 60 formed in the first main surface 3 (active surface 8) in the first termination region 15A.
  • a source potential VS is applied to the multiple dummy trench structures 60 as a second potential.
  • the multiple dummy trench structures 60 are each formed in a band shape extending in the first direction X, and are arranged at intervals in the second direction Y.
  • the multiple dummy trench structures 60 face the multiple trench resistor structures 41 in a one-to-one correspondence in the first direction X.
  • the multiple dummy trench structures 60 face the first trench source structure 25 and the second trench source structure 30 in the second direction Y.
  • the multiple dummy trench structures 60 penetrate the body region 17 to reach the first semiconductor region 6.
  • the multiple dummy trench structures 60 penetrate the third connection surface 10C and are exposed from the third connection surface 10C.
  • the multiple trench gate structures 20 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.
  • the multiple dummy trench structures 60 include multiple first dummy trench structures 61 and multiple second dummy trench structures 62.
  • the multiple first dummy trench structures 61 are arranged in the region between the periphery of the active surface 8 and the multiple first trench resistance structures 42.
  • the multiple first dummy trench structures 61 are each formed in a band shape extending in the first direction X, and are arranged at intervals in the second direction Y.
  • the multiple first dummy trench structures 61 face the multiple first trench resistance structures 42 in a one-to-one correspondence in the first direction X.
  • the first trench resistance structure 42 to which the gate potential VG is applied and the first dummy trench structure 61 to which the source potential VS is applied face each other in the first direction X.
  • the multiple first dummy trench structures 61 face the first trench source structure 25 and the second trench source structure 30 in the second direction Y.
  • the multiple first dummy trench structures 61 penetrate the third connection surface 10C and are exposed from the third connection surface 10C.
  • the multiple first dummy trench structures 61 penetrate the body region 17 to reach the first semiconductor region 6.
  • the multiple first dummy trench structures 61 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.
  • the first dummy trench structure 61 has a sixth width W6 in the second direction Y and a sixth depth D6 in the normal direction Z.
  • the sixth width W6 is preferably approximately equal to the fourth width W4 of the first trench resistor structure 42.
  • the sixth width W6 is preferably approximately equal to the first width W1 of the trench gate structure 20.
  • the sixth width W6 may be 0.1 ⁇ m or more and 3 ⁇ m or less.
  • the sixth width W6 is preferably 0.5 ⁇ m or more and 2 ⁇ m or less.
  • the sixth depth D6 is less than the fifth depth D5 of the second trench resistance structure 43 (the second depth D2 of the first trench source structure 25).
  • the sixth depth D6 is less than the outer circumferential depth DO of the outer circumferential surface 9. It is preferable that the sixth depth D6 is approximately equal to the fourth depth D4 of the first trench resistance structure 42 (the first depth D1 of the trench gate structure 20).
  • the sixth depth D6 may be 0.1 ⁇ m or more and 3 ⁇ m or less. It is preferable that the sixth depth D6 is 0.5 ⁇ m or more and 1.5 ⁇ m or less.
  • the first dummy trench structure 61 is disposed in the first direction X at a fifth interval I5 from the first trench resistance structure 42.
  • the fifth interval I5 is preferably 0.5 to 2 times the fourth width W4 (sixth width W6).
  • the fifth interval I5 is preferably 0.5 to 2 times the fourth interval I4 between the first trench resistance structure 42 and the second trench resistance structure 43. It is particularly preferable that the fifth interval I5 is 1.5 times or less than the fourth interval I4.
  • the fifth interval I5 may be approximately equal to the fourth interval I4.
  • the fifth interval I5 may be 0.1 ⁇ m to 2.5 ⁇ m. It is preferable that the fifth interval I5 is 0.5 ⁇ m to 1.5 ⁇ m.
  • the innermost first dummy trench structure 61 on the active region 12 side is arranged adjacent to the outermost first trench source structure 25 in the second direction Y, with the aforementioned first distance I1 from the outermost first trench source structure 25.
  • the first dummy trench structure 61 includes a first dummy trench 63, a first dummy insulating film 64, and a first dummy buried electrode 65.
  • the first dummy trench 63 is formed in the active surface 8 and defines the wall surface of the first dummy trench structure 61.
  • the sidewall and bottom wall of the first dummy trench 63 are connected to the third connection surface 10C.
  • the first dummy insulating film 64 covers the wall surface of the first dummy trench 63 and is connected to the main surface insulating film 16 at the active surface 8.
  • the first dummy insulating film 64 is connected to the main surface insulating film 16 at the communicating portion of the third connection surface 10C.
  • the first dummy insulating film 64 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the first dummy insulating film 64 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the first dummy insulating film 64 includes a silicon oxide film made of an oxide of the chip 2.
  • the first dummy buried electrode 65 is buried in the first dummy trench 63 with the first dummy insulating film 64 in between.
  • the first dummy buried electrode 65 may include conductive polysilicon.
  • the multiple second dummy trench structures 62 are arranged in the region between the periphery of the active surface 8 and the multiple second trench resistance structures 43.
  • the multiple second dummy trench structures 62 are arranged in the region between two first dummy trench structures 61 adjacent in the second direction Y.
  • the multiple second dummy trench structures 62 are arranged alternately with the multiple first dummy trench structures 61 in the second direction Y, and face the multiple second trench resistance structures 43 in a one-to-one correspondence in the first direction X.
  • the second trench resistance structure 43 to which the gate potential VG is applied and the second dummy trench structure 62 to which the source potential VS is applied face each other in the first direction X.
  • the multiple second dummy trench structures 62 are each formed in a band shape extending in the first direction X in a plan view.
  • the second dummy trench structures 62 face the first trench source structure 25 and the second trench source structure 30 in the second direction Y.
  • the second dummy trench structures 62 have portions that are extended toward the ends of the second trench resistance structures 43 relative to the ends of the first trench resistance structures 42.
  • the multiple second dummy trench structures 62 are pulled out toward the ends of the multiple second trench resistance structures 43 with respect to the region between the first trench resistance structure 42 and the first dummy trench structure 61. As a result, the ends of the multiple second dummy trench structures 62 face the first trench resistance structure 42 in the second direction Y. In other words, the multiple second dummy trench structures 62 have a portion facing the first trench resistance structure 42 in the second direction Y, and a portion facing the first dummy trench structure 61 in the second direction Y.
  • the multiple second dummy trench structures 62 penetrate the third connection surface 10C and are exposed from the third connection surface 10C.
  • the multiple second dummy trench structures 62 penetrate the body region 17 to reach the first semiconductor region 6.
  • the multiple second dummy trench structures 62 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.
  • the second dummy trench structure 62 has a seventh width W7 in the second direction Y and a seventh depth D7 in the normal direction Z.
  • the seventh width W7 is preferably approximately equal to the fifth width W5 of the second trench resistor structure 43.
  • the seventh width W7 is preferably approximately equal to the second width W2 of the first trench source structure 25 (the first width W1 of the trench gate structure 20).
  • the seventh width W7 may be 0.1 ⁇ m or more and 3 ⁇ m or less.
  • the seventh width W7 is preferably 0.5 ⁇ m or more and 2 ⁇ m or less.
  • the seventh depth D7 is equal to or greater than the sixth depth D6 of the first dummy trench structure 61 (the fourth depth D4 of the first trench resistor structure 42). In this embodiment, the seventh depth D7 is greater than the sixth depth D6 (the fourth depth D4). It is preferable that the seventh depth D7 is greater than or equal to 1.5 times and less than or equal to 3 times the sixth depth D6 (the fourth depth D4).
  • the seventh depth D7 is preferably approximately equal to the fifth depth D5 of the second trench resistor structure 43 (the second depth D2 of the first trench source structure 25). In this embodiment, the seventh depth D7 is approximately equal to the outer circumferential depth DO of the outer circumferential surface 9.
  • the seventh depth D7 may be 0.5 ⁇ m or more and 5 ⁇ m or less. It is particularly preferable that the seventh depth D7 is 2.5 ⁇ m or less.
  • the second dummy trench structure 62 is disposed at a sixth interval I6 from the first dummy trench structure 61 in the second direction Y.
  • the sixth interval I6 is preferably 0.5 to 2 times the sixth width W6 (seventh width W7). It is particularly preferable that the sixth interval I6 is less than the sixth width W6 (seventh width W7).
  • the sixth interval I6 is preferably approximately equal to the fourth interval I4 between the first trench resistor structure 42 and the second trench resistor structure 43.
  • the sixth interval I6 is preferably approximately equal to the first interval I1 between the trench gate structure 20 and the first trench source structure 25.
  • the sixth interval I6 may be 0.1 ⁇ m or more and 2.5 ⁇ m or less.
  • the sixth interval I6 is preferably 0.5 ⁇ m or more and 1.5 ⁇ m or less.
  • the second dummy trench structure 62 is disposed in the first direction X at a seventh interval I7 from the second trench resistor structure 43.
  • the seventh interval I7 is preferably 0.5 to 2 times the sixth width W6 (seventh width W7).
  • the seventh interval I7 is preferably 0.5 to 2 times the sixth width W6 (seventh width W7).
  • the seventh interval I7 is 1.5 times or less the sixth interval I6 (fourth interval I4). It is preferable that the seventh interval I7 is approximately equal to the aforementioned fifth interval I5. The seventh interval I7 may be approximately equal to the sixth interval I6 (fourth interval I4). The seventh interval I7 may be 0.1 ⁇ m or more and 2.5 ⁇ m or less. It is preferable that the seventh interval I7 is 0.5 ⁇ m or more and 1.5 ⁇ m or less.
  • the second dummy trench structure 62 includes a second dummy trench 66, a second dummy insulating film 67, and a second dummy buried electrode 68.
  • the second dummy trench 66 is formed in the active surface 8 and defines the wall surface of the second dummy trench structure 62.
  • the side wall of the second dummy trench 66 is connected to the third connection surface 10C.
  • the bottom wall of the second dummy trench 66 is connected to the outer peripheral surface 9.
  • the second dummy insulating film 67 covers the wall surface of the second dummy trench 66 and is connected to the main surface insulating film 16 at the active surface 8.
  • the second dummy insulating film 67 is connected to the main surface insulating film 16 at the communicating portion of the third connection surface 10C and the communicating portion of the outer peripheral surface 9.
  • the second dummy insulating film 67 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the second dummy insulating film 67 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the second dummy insulating film 67 includes a silicon oxide film made of an oxide of the chip 2.
  • the second dummy buried electrode 68 is buried in the second dummy trench 66 with the second dummy insulating film 67 in between.
  • the second dummy buried electrode 68 may include conductive polysilicon.
  • the semiconductor device 1 includes a plurality of main mesa portions 70, a plurality of first mesa portions 71, and a plurality of second mesa portions 72.
  • Each main mesa portion 70 is partitioned into a region between the first trench resistance structure 42 and the second trench resistance structure 43, and a region between the first dummy trench structure 61 and the second dummy trench structure 62.
  • Each main mesa portion 70 extends in a strip shape in the first direction X.
  • the width of each main mesa portion 70 in the second direction Y is determined by the aforementioned fourth interval I4 and sixth interval I6.
  • Each first mesa portion 71 is partitioned into an area between the first trench resistor structure 42 and the first dummy trench structure 61, and is connected to the main mesa portion 70.
  • Each first mesa portion 71 is an area in which a voltage drop occurs between the gate potential VG and the source potential VS in the first direction X.
  • the width of each first mesa portion 71 in the first direction X is determined by the fifth interval I5 described above.
  • each first mesa portion 71 faces the second dummy trench structure 62 in the second direction Y, but is shifted toward the second dummy trench structure 62 with respect to the end of the second trench resistance structure 43 so as not to face the second trench resistance structure 43 in the second direction Y.
  • Each first mesa portion 71 is formed at a distance from the periphery of the resistance film 50 in the first direction X, and does not face the resistance film 50 in the normal direction Z.
  • each first mesa portion 71 may face the resistive film 50 in the normal direction Z.
  • Each first mesa portion 71 defines one main mesa portion 70 and a T-shaped mesa in plan view. From another perspective, each first mesa portion 71 defines two main mesa portions 70 and an H-shaped mesa in plan view. In this embodiment, the multiple first mesa portions 71 are formed on the same straight line along the second direction Y. Of course, the multiple first mesa portions 71 may be formed offset from each other in the first direction X so as not to be positioned on the same straight line along the second direction Y.
  • Each second mesa portion 72 is partitioned into an area between the second trench resistor structure 43 and the second dummy trench structure 62, and is connected to the main mesa portion 70.
  • Each second mesa portion 72 is an area in which a voltage drop occurs between the gate potential VG and the source potential VS in the first direction X.
  • the width of each second mesa portion 72 in the first direction X is determined by the seventh interval I7 described above.
  • Each second mesa portion 72 is formed at a distance from the first mesa portion 71 in the first direction X so as not to face the first mesa portion 71 in the second direction Y.
  • each second mesa portion 72 faces the first trench resistance structure 42 in the second direction Y, and is shifted toward the first trench resistance structure 42 with respect to the end of the first dummy trench structure 61 so as not to face the first dummy trench structure 61 in the second direction Y.
  • Each second mesa portion 72 is formed at a distance from the periphery of the resistive film 50 in the first direction X in a plan view, and does not face the resistive film 50 in the normal direction Z. Therefore, electrical interference of the resistive film 50 with each second mesa portion 72 is suppressed, and electrical interference of each second mesa portion 72 with the resistive film 50 is suppressed. Of course, if a resistive film 50 wider than the multiple trench resistance structures 41 is formed, each second mesa portion 72 may face the resistive film 50 in the normal direction Z.
  • Each second mesa portion 72 defines one main mesa portion 70 and a T-shaped mesa in plan view. From another perspective, each second mesa portion 72 defines two main mesa portions 70 and an H-shaped mesa in plan view. In this embodiment, the multiple second mesa portions 72 are formed on the same straight line along the second direction Y.
  • the multiple second mesa portions 72 may be formed offset from each other in the first direction X so as not to be positioned on the same straight line along the second direction Y. Even in this case, the multiple second mesa portions 72 are formed at intervals from the first mesa portion 71 in the first direction X so as not to face the first mesa portion 71 in the second direction Y.
  • the semiconductor device 1 includes a plurality of fourth well regions 75 of p-type formed in a region along the plurality of first trench resistance structures 42 in the first termination region 15A.
  • the fourth well region 75 has a higher p-type impurity concentration than the body region 17.
  • the p-type impurity concentration of the fourth well region 75 may be lower than the body region 17. It is preferable that the p-type impurity concentration of the fourth well region 75 is approximately equal to the p-type impurity concentration of the first well region 35.
  • the multiple fourth well regions 75 cover the wall surfaces of the corresponding first trench resistance structures 42 at intervals from the second trench resistance structure 43, the first dummy trench structure 61, and the second dummy trench structure 62, and are electrically connected to the body region 17 in the surface portion of the active surface 8.
  • Each fourth well region 75 includes a portion that covers the wall surface of each first trench resistance structure 42 in each first mesa portion 71, and faces each first dummy trench structure 61 in the first direction X.
  • each fourth well region 75 has a portion that faces the second trench resistance structure 43 in the second direction Y, and a portion that faces the second dummy trench structure 62 in the second direction Y.
  • the multiple fourth well regions 75 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 across a portion of the first semiconductor region 6.
  • the bottoms of the multiple fourth well regions 75 are located on the active surface 8 side relative to the depth position of the bottoms of the multiple second well regions 36.
  • the bottoms of the multiple fourth well regions 75 are formed at approximately the same depth as the bottoms of the multiple first well regions 35.
  • the multiple fourth well regions 75 form pn junctions with the first semiconductor region 6.
  • the semiconductor device 1 includes a plurality of p-type fifth well regions 76 formed in a region along the plurality of second trench resistance structures 43 in the first termination region 15A.
  • the fifth well region 76 has a higher p-type impurity concentration than the body region 17.
  • the p-type impurity concentration of the fifth well region 76 may be lower than the body region 17. It is preferable that the p-type impurity concentration of the fifth well region 76 is approximately equal to the p-type impurity concentration of the plurality of fourth well regions 75 (second well region 36).
  • the plurality of fifth well regions 76 cover the wall surfaces of the corresponding second trench resistance structures 43 at intervals from the first trench resistance structure 42, the first dummy trench structure 61, and the second dummy trench structure 62, and are electrically connected to the body region 17 at the surface portion of the active surface 8.
  • Each fifth well region 76 includes a portion that covers the wall surface of each second trench resistance structure 43 in each second mesa portion 72, and faces the second dummy trench structure 62 in the first direction X. In this embodiment, each fifth well region 76 faces the first trench resistance structure 42 in the second direction Y, but does not face the first dummy trench structure 61 in the second direction Y.
  • the multiple fifth well regions 76 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 across a portion of the first semiconductor region 6.
  • the bottoms of the multiple fifth well regions 76 are located on the bottom side of the first semiconductor region 6 relative to the depth position of the bottoms of the multiple fourth well regions 75 (first well regions 35).
  • the bottoms of the multiple fifth well regions 76 are formed at a depth approximately equal to the bottoms of the multiple second well regions 36.
  • the multiple fifth well regions 76 form pn junctions with the first semiconductor region 6.
  • the semiconductor device 1 includes a plurality of sixth well regions 77 of p-type formed in a region along the plurality of first dummy trench structures 61 in the first termination region 15A.
  • the sixth well region 77 has a higher p-type impurity concentration than the body region 17.
  • the p-type impurity concentration of the sixth well region 77 may be lower than the body region 17. It is preferable that the p-type impurity concentration of the sixth well region 77 is approximately equal to the p-type impurity concentration of the fourth well region 75 (first well region 35).
  • the sixth well regions 77 cover the walls of the corresponding first dummy trench structures 61 at intervals from the first trench resistance structure 42, the second trench resistance structure 43, and the second dummy trench structure 62, and are electrically connected to the body region 17 at the surface portion of the active surface 8.
  • Each sixth well region 77 includes a portion that covers the wall of each first dummy trench structure 61 in each first mesa portion 71, and faces the first trench resistance structure 42 in the first direction X.
  • Each sixth well region 77 may be formed in each first mesa portion 71 at a distance from each fourth well region 75, or may be integrated with each fourth well region 75. Each sixth well region 77 faces the second dummy trench structure 62 in the second direction Y, but does not face the second trench resistor structure 43 in the second direction Y.
  • the multiple sixth well regions 77 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 across a portion of the first semiconductor region 6.
  • the bottoms of the multiple sixth well regions 77 are located on the active surface 8 side relative to the depth position of the bottoms of the multiple fifth well regions 76 (second well regions 36).
  • the bottoms of the multiple sixth well regions 77 are formed at a depth approximately equal to the bottoms of the multiple fourth well regions 75 (first well regions 35).
  • the multiple sixth well regions 77 form pn junctions with the first semiconductor region 6.
  • the semiconductor device 1 includes a plurality of p-type seventh well regions 78 formed in a region along the plurality of second dummy trench structures 62 in the first termination region 15A.
  • the seventh well regions 78 have a higher p-type impurity concentration than the body region 17.
  • the p-type impurity concentration of the seventh well regions 78 may be lower than the body region 17. It is preferable that the p-type impurity concentration of the seventh well regions 78 is approximately equal to the p-type impurity concentration of the fifth well region 76 (second well region 36).
  • the seventh well regions 78 cover the walls of the corresponding second dummy trench structures 62 at intervals from the first trench resistance structure 42, the second trench resistance structure 43, and the first dummy trench structure 61, and are electrically connected to the body region 17 at the surface portion of the active surface 8.
  • Each seventh well region 78 includes a portion that covers the wall of each second dummy trench structure 62 in each second mesa portion 72, and faces the second trench resistance structure 43 in the first direction X.
  • Each seventh well region 78 may be formed in each second mesa portion 72 at a distance from each fifth well region 76, or may be integrated with each fifth well region 76.
  • Each seventh well region 78 has a portion facing the first dummy trench structure 61 in the second direction Y, and a portion facing the first trench resistor structure 42 in the second direction Y.
  • the multiple seventh well regions 78 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 across a portion of the first semiconductor region 6.
  • the bottoms of the multiple seventh well regions 78 are located on the bottom side of the first semiconductor region 6 relative to the depth position of the bottoms of the multiple sixth well regions 77 (fourth well regions 75).
  • the bottoms of the multiple seventh well regions 78 are formed at a depth approximately equal to the bottoms of the multiple fifth well regions 76 (second well regions 36).
  • the multiple seventh well regions 78 form pn junctions with the first semiconductor region 6.
  • the semiconductor device 1 includes a plurality of second contact regions 79 of p-type formed in a region along the plurality of second trench resistance structures 43 in the first termination region 15A.
  • the second contact regions 79 have a higher p-type impurity concentration than the body region 17.
  • the p-type impurity concentration of the second contact regions 79 is higher than the fifth well region 76. It is preferable that the p-type impurity concentration of the second contact regions 79 is approximately equal to the p-type impurity concentration of the first contact region 38.
  • the second contact regions 79 cover the wall surfaces of the corresponding second trench resistance structures 43 in the corresponding fifth well regions 76.
  • the second contact regions 79 are formed in a one-to-many correspondence with each second trench resistance structure 43.
  • the second contact regions 79 are formed at intervals along the corresponding second trench resistance structures 43.
  • the second contact regions 79 are extended from the corresponding fifth well regions 76 along the wall surfaces of the corresponding second trench resistance structures 43 to the surface layer of the body region 17 and exposed from the active surface 8.
  • the multiple second contact regions 79 are each formed in a band shape extending in the first direction X in a plan view.
  • the length of the multiple second contact regions 79 in the first direction X is preferably equal to or greater than the fifth width W5 of the second trench resistance structure 43.
  • the length of the multiple second contact regions 79 is preferably greater than the distance between two adjacent second contact regions 79 in the first direction X.
  • the length of the multiple second contact regions 79 is preferably less than the distance between the first mesa portion 71 and the second mesa portion 72.
  • the length of the multiple second contact regions 79 is preferably approximately equal to the length of the multiple first contact regions 38.
  • the multiple second contact regions 79 include an outermost second contact region 79 that covers an area along the end of each second trench resistance structure 43.
  • the outermost second contact region 79 is preferably formed at a distance from the second mesa portion 72. In other words, the outermost second contact region 79 preferably faces the first trench resistance structure 42 in the second direction Y, but does not face the first dummy trench structure 61 in the second direction Y.
  • the distance between the second mesa portion 72 and the outermost second contact region 79 may be less than the length of the second contact region 79.
  • the distance between the second mesa portion 72 and the outermost second contact region 79 may be less than the fifth width W5 of the second trench resistor structure 43. It is particularly preferable that the distance between the second mesa portion 72 and the outermost second contact region 79 is less than the width (seventh interval I7) of the second mesa portion 72.
  • the second contact regions 79 along one second trench resistance structure 43 face the second contact regions 79 along the other second trench resistance structures 43 in the second direction Y. That is, in this embodiment, the second contact regions 79 are arranged in a matrix with gaps in the first direction X and the second direction Y as a whole in a plan view. The second contact regions 79 may face the first contact regions 38 in the second direction Y. In this case, the second contact regions 79 may be arranged in a matrix with the first contact regions 38.
  • the second contact regions 79 along one second trench resistance structure 43 may be arranged offset in the first direction X so as to face the regions between the second contact regions 79 along the other second trench resistance structures 43 in the second direction Y.
  • the second contact regions 79 may be arranged in a staggered manner with gaps in the first direction X and the second direction Y as a whole in a plan view.
  • the second contact regions 79 may face the regions between the first contact regions 38 in the second direction Y.
  • the second contact regions 79 may be arranged in a staggered manner together with the first contact regions 38.
  • the semiconductor device 1 includes a plurality of p-type third contact regions 80 formed in a region along the plurality of second dummy trench structures 62 in the first termination region 15A.
  • the third contact regions 80 have a higher p-type impurity concentration than the body region 17.
  • the p-type impurity concentration of the third contact regions 80 is higher than the seventh well region 78. It is preferable that the p-type impurity concentration of the third contact regions 80 is approximately equal to the p-type impurity concentration of the second contact region 79 (first contact region 38).
  • the multiple third contact regions 80 cover the wall surfaces of the corresponding second dummy trench structures 62 in the corresponding seventh well regions 78.
  • the multiple third contact regions 80 are formed in a one-to-many correspondence with each second dummy trench structure 62.
  • the multiple third contact regions 80 are formed at intervals along the corresponding second dummy trench structures 62.
  • the multiple third contact regions 80 are extended from the corresponding seventh well regions 78 along the wall surfaces of the corresponding second dummy trench structures 62 to the surface layer of the body region 17 and exposed from the active surface 8.
  • the multiple third contact regions 80 are each formed in a band shape extending in the first direction X in a plan view.
  • the length of the multiple third contact regions 80 in the first direction X is preferably equal to or greater than the seventh width W7 described above.
  • the length of the multiple third contact regions 80 is preferably greater than the distance between two adjacent third contact regions 80 in the first direction X.
  • the length of the multiple third contact regions 80 is preferably less than the distance between the first mesa portion 71 and the second mesa portion 72.
  • the length of the multiple third contact regions 80 is preferably approximately equal to the length of the multiple second contact regions 79 (first contact regions 38).
  • the multiple third contact regions 80 face the first dummy trench structure 61 in the second direction Y in the region on the third connection surface 10C side relative to the first mesa portion 71.
  • the multiple third contact regions 80 are formed at intervals along each second dummy trench structure 62 so that the first mesa portion 71 is located between two adjacent third contact regions 80. It is preferable that the multiple third contact regions 80 are formed at intervals in the first direction X from the first mesa portion 71 so as not to face the first mesa portion 71.
  • the distance between the first mesa portion 71 and the third contact region 80 is less than the length of the third contact region 80. It is preferable that the distance between the first mesa portion 71 and the third contact region 80 is less than the seventh width W7 described above. It is particularly preferable that the distance between the first mesa portion 71 and the third contact region 80 is less than the width of the first mesa portion 71 (the fifth interval I5).
  • the multiple third contact regions 80 include at least one (in this example, one) outermost third contact region 80 formed in the range between the first mesa portion 71 and the second mesa portion 72.
  • the outermost third contact region 80 faces the first trench resistor structure 42 in the second direction Y.
  • the outermost third contact region 80 is preferably formed at a distance in the first direction X from the first mesa portion 71 and the second mesa portion 72. In other words, the outermost third contact region 80 preferably faces the first trench resistor structure 42 in the second direction Y, but does not face the first dummy trench structure 61 in the second direction Y.
  • the distance between the second mesa portion 72 and the third contact region 80 is preferably less than the length of the third contact region 80.
  • the distance between the second mesa portion 72 and the third contact region 80 is preferably less than the aforementioned seventh width W7.
  • the distance between the second mesa portion 72 and the outermost third contact region 80 is less than the width (seventh interval I7) of the second mesa portion 72. It is preferable that the distance between the outermost second contact region 79 and the outermost third contact region 80 adjacent to each other across the second mesa portion 72 is approximately equal to the distance between two adjacent third contact regions 80 across the first mesa portion 71.
  • the multiple third contact regions 80 along one second dummy trench structure 62 face the multiple third contact regions 80 along the other second dummy trench structures 62 in the second direction Y. That is, in this embodiment, the multiple third contact regions 80 are arranged in a matrix with gaps in the first direction X and the second direction Y as a whole in a plan view. In this case, the multiple third contact regions 80 may be arranged in a matrix with the multiple second contact regions 79. The multiple third contact regions 80 may also be arranged in a matrix with the multiple first contact regions 38.
  • the third contact regions 80 along one second dummy trench structure 62 may be arranged offset in the first direction X so as to face the second direction Y in a region between the third contact regions 80 along the other second dummy trench structure 62.
  • the third contact regions 80 may be arranged in a staggered manner with intervals in the first direction X and the second direction Y as a whole in a plan view.
  • the third contact regions 80 may be arranged in a staggered manner together with the second contact regions 79.
  • the third contact regions 80 may also be arranged in a staggered manner together with the first contact regions 38.
  • the semiconductor device 1 includes a termination dummy structure 85 formed on the first main surface 3 (active surface 8) in the first termination region 15A.
  • the termination dummy structure 85 is incorporated in the active surface 8 (first termination region 15A) for one purpose of alleviating local electric field concentration in the vicinity of the gate resistor 40 and improving the breakdown voltage (e.g., breakdown voltage).
  • the presence or absence of the termination dummy structure 85 is optional, and a configuration not including the termination dummy structure 85 may be adopted.
  • the termination dummy structure 85 is disposed in a region on the first side surface 5A side (first connection surface 10A side) of the gate resistor 40.
  • the termination dummy structure 85 is formed at the end edge of the active surface 8.
  • the termination dummy structure 85 faces the gate resistor 40 and the dummy structure 55 in the second direction Y.
  • the termination dummy structure 85 faces the active region 12 across the gate resistor 40 in the second direction Y, faces the first peripheral region 14A across the first dummy structure 56 in the second direction Y, and faces the second peripheral region 14B across the second dummy structure 57 in the second direction Y.
  • Figure 24 is an enlarged plan view showing the layout of the termination dummy structure 85.
  • Figure 25 is a further enlarged plan view showing the layout of the termination dummy structure 85.
  • Figure 26 is a cross-sectional view taken along line XXVI-XXVI shown in Figure 25.
  • the termination dummy structure 85 includes at least one (in this embodiment, multiple) trench termination structures 86 formed in the first termination region 15A.
  • a source potential VS is applied to the multiple trench termination structures 86 as a second potential.
  • the multiple trench termination structures 86 are each formed in a band shape extending in the first direction X and are arranged at intervals in the second direction Y.
  • the multiple trench termination structures 86 face the first trench resistor structure 42 and the first dummy trench structure 61 in the second direction Y.
  • the multiple trench termination structures 86 are exposed from at least one of the third connection surface 10C and the fourth connection surface 10D.
  • the trench termination structure 86 penetrates both the third connection surface 10C and the fourth connection surface 10D and is exposed from both the third connection surface 10C and the fourth connection surface 10D.
  • the multiple trench termination structures 86 penetrate the body region 17 to reach the first semiconductor region 6.
  • the multiple trench termination structures 86 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.
  • the trench termination structure 86 has an eighth width W8 in the second direction Y and an eighth depth D8 in the normal direction Z.
  • the eighth width W8 is preferably approximately equal to the fifth width W5 (second width W2) described above.
  • the eighth width W8 may be 0.1 ⁇ m or more and 3 ⁇ m or less.
  • the eighth width W8 is preferably 0.5 ⁇ m or more and 2 ⁇ m or less.
  • the eighth depth D8 is equal to or greater than the fourth depth D4 (first depth D1) described above. In this embodiment, the eighth depth D8 is greater than the fourth depth D4 (first depth D1). It is preferable that the eighth depth D8 is 1.5 to 3 times the fourth depth D4 (first depth D1). In this embodiment, the eighth depth D8 is approximately equal to the fifth depth D5 (second depth D2) described above. The eighth depth D8 is approximately equal to the outer circumferential depth DO of the outer circumferential surface 9.
  • the eighth depth D8 may be 0.5 ⁇ m to 5 ⁇ m. It is particularly preferable that the eighth depth D8 is 2.5 ⁇ m or less.
  • the multiple trench termination structures 86 are arranged at an eighth interval I8 from each other in the second direction Y.
  • the eighth interval I8 is preferably 0.5 to 2 times the eighth width W8. It is particularly preferable that the eighth interval I8 is less than the eighth width W8. It is preferable that the eighth width W8 is approximately equal to the aforementioned fourth interval I4 (first interval I1).
  • the eighth width W8 may be 0.1 ⁇ m to 2.5 ⁇ m. It is preferable that the eighth width W8 is 0.5 ⁇ m to 1.5 ⁇ m.
  • the innermost trench termination structure 86 on the gate resistor 40 side is disposed adjacent to the outermost first trench resistance structure 42 in the second direction Y, with the aforementioned fourth interval I4 between them. Also, in this embodiment, the innermost trench termination structure 86 is disposed adjacent to the outermost first dummy trench structure 61 in the second direction Y, with the aforementioned sixth interval I6 between them.
  • the trench termination structure 86 includes a termination trench 87, a termination insulating film 88, and a termination buried electrode 89.
  • the termination trench 87 is formed in the active surface 8 and defines the wall surface of the trench termination structure 86.
  • the side wall of the termination trench 87 is in communication with the third connection surface 10C.
  • the bottom wall of the termination trench 87 is in communication with the outer peripheral surface 9.
  • the termination insulating film 88 covers the wall surface of the termination trench 87 and is connected to the main surface insulating film 16 at the active surface 8.
  • the termination insulating film 88 is connected to the main surface insulating film 16 at the communicating portion of the third connection surface 10C and the communicating portion of the outer peripheral surface 9.
  • the termination insulating film 88 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the termination insulating film 88 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the termination insulating film 88 includes a silicon oxide film made of an oxide of the chip 2.
  • the termination buried electrode 89 is embedded in the termination trench 87 with the termination insulating film 88 in between.
  • the termination buried electrode 89 may include conductive polysilicon.
  • the semiconductor device 1 includes a plurality of p-type eighth well regions 90 formed in the first termination region 15A in a region along the plurality of trench termination structures 86.
  • the eighth well regions 90 have a higher p-type impurity concentration than the body region 17.
  • the p-type impurity concentration of the eighth well regions 90 may be lower than the body region 17. It is preferable that the p-type impurity concentration of the eighth well regions 90 is approximately equal to the p-type impurity concentration of the second well region 36 (first well region 35).
  • the multiple eighth well regions 90 cover the wall surfaces of the corresponding trench termination structures 86 at intervals from the adjacent trench termination structures 86, and are electrically connected to the body region 17 at the surface portion of the active surface 8.
  • the multiple eighth well regions 90 extend in a band shape along the corresponding trench termination structures 86 in a plan view, and are exposed from the third connection surface 10C and the fourth connection surface 10D.
  • the multiple eighth well regions 90 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 across a portion of the first semiconductor region 6.
  • the bottoms of the multiple eighth well regions 90 are located on the bottom side of the first semiconductor region 6 relative to the depth position of the bottoms of the multiple first well regions 35.
  • the bottoms of the multiple eighth well regions 90 are formed at a depth approximately equal to the bottoms of the multiple second well regions 36.
  • the multiple eighth well regions 90 form pn junctions with the first semiconductor region 6.
  • the semiconductor device 1 includes a dummy structure 55 and a termination dummy structure 85 formed on the first main surface 3 (active surface 8) in the second termination region 15B.
  • the semiconductor device 1 does not include a gate resistor 40 in the second termination region 15B.
  • the dummy structure 55 on the second termination region 15B side is disposed in a region on the fourth side surface 5D side (fourth connection surface 10D side) of the active region 12, and faces the active region 12 and the peripheral region 14 in the second direction Y.
  • the dummy structure 55 on the second termination region 15B side includes multiple dummy trench structures 60 (multiple first dummy trench structures 61 and multiple second dummy trench structures 62), similar to the first dummy structure 56 on the first termination region 15A side.
  • the multiple dummy trench structures 60 on the second termination region 15B side penetrate both the third connection surface 10C and the fourth connection surface 10D, and are exposed from both the third connection surface 10C and the fourth connection surface 10D. Otherwise, the configuration of the dummy structure 55 on the second termination region 15B side is similar to the configuration of the dummy structure 55 (first dummy structure 56) on the first termination region 15A side.
  • the termination dummy structure 85 on the second termination region 15B side has a configuration similar to the configuration of the termination dummy structure 85 on the first termination region 15A side.
  • the description of the termination dummy structure 85 on the first termination region 15A side applies.
  • the semiconductor device 1 also includes a plurality of sixth well regions 77, a plurality of seventh well regions 78, a plurality of second contact regions 79, and a plurality of eighth well regions 90 in the second termination region 15B.
  • the explanations of the sixth well region 77, the seventh well region 78, the second contact region 79, and the eighth well region 90 on the second termination region 15B side are the same as those of the sixth well region 77, the seventh well region 78, the second contact region 79, and the eighth well region 90 on the first termination region 15A side.
  • the semiconductor device 1 includes a p-type outer well region 91 formed in the surface layer of the peripheral surface 9.
  • the outer well region 91 has a lower p-type impurity concentration than the first contact region 38.
  • the p-type impurity concentration of the outer well region 91 is higher than that of the body region 17.
  • the p-type impurity concentration of the outer well region 91 may be lower than that of the body region 17. It is preferable that the outer well region 91 has a p-type impurity concentration approximately equal to that of the first well region 35 (second well region 36).
  • the outer well region 91 is formed at a distance from the periphery of the outer peripheral surface 9 (first to fourth side surfaces 5A to 5D) toward the active surface 8 in a plan view, and extends in a band shape along the active surface 8.
  • the outer well region 91 is formed in a ring shape (specifically, a square ring shape) that surrounds the active surface 8 in a plan view.
  • the outer well region 91 extends from the surface layer of the outer peripheral surface 9 toward the surface layers of the first to fourth connection surfaces 10A to 10D, and covers the first to fourth connection surfaces 10A to 10D.
  • the outer well region 91 is electrically connected to the body region 17 at the surface portion of the active surface 8.
  • the outer well region 91 is connected to the second well region 36 at the third connection surface 10C (fourth connection surface 10D) and the communication portion of the first trench source structure 25.
  • the outer well region 91 is connected to the third well region 37 at the communication portion of the third connection surface 10C (fourth connection surface 10D) and the second trench source structure 30.
  • the outer well region 91 is connected to the sixth well region 77 at the third connection surface 10C (fourth connection surface 10D) and the communication portion of the first dummy trench structure 61.
  • the outer well region 91 is connected to the seventh well region 78 at the communication portion of the third connection surface 10C (fourth connection surface 10D) and the second dummy trench structure 62.
  • the outer well region 91 is connected to the eighth well region 90 at the communication portion of the third connection surface 10C (fourth connection surface 10D) and the trench termination structure 86.
  • the outer well region 91 is formed at a distance from the bottom of the first semiconductor region 6 toward the outer circumferential surface 9, and faces the second semiconductor region 7 across a portion of the first semiconductor region 6.
  • the outer well region 91 is located closer to the bottom of the first semiconductor region 6 than the bottom wall of the first trench source structure 25 (second trench resistor structure 43).
  • the bottom of the outer well region 91 is located closer to the bottom of the first semiconductor region 6 than the bottom of the first contact region 38. It is preferable that the bottom of the outer well region 91 is formed at a depth position approximately equal to the bottom of the second well region 36.
  • the outer well region 91 forms a pn junction with the first semiconductor region 6.
  • the semiconductor device 1 includes a p-type outer contact region 92 formed in a surface layer of the outer well region 91.
  • the outer contact region 92 has a higher p-type impurity concentration than the body region 17.
  • the p-type impurity concentration of the outer contact region 92 is higher than that of the outer well region 91. It is preferable that the p-type impurity concentration of the outer contact region 92 is approximately equal to the p-type impurity concentration of the first contact region 38 (second contact region 79).
  • the outer contact region 92 is formed in the surface layer of the outer well region 91 at a distance from the periphery of the active surface 8 (first to fourth connection surfaces 10A to 10D) and the periphery of the outer peripheral surface 9 (first to fourth side surfaces 5A to 5D) in a plan view, and is formed in a band shape extending along the active surface 8.
  • the outer contact region 92 is formed in a ring shape (specifically, a square ring shape) surrounding the active surface 8 in a plan view.
  • the outer contact region 92 is formed at a distance from the bottom of the outer well region 91 toward the outer peripheral surface 9, and faces the first semiconductor region 6 across a portion of the outer well region 91.
  • the outer contact region 92 is located closer to the bottom of the first semiconductor region 6 than the bottom wall of the first trench source structure 25 (second trench resistor structure 43). It is preferable that the bottom of the outer contact region 92 is formed at a depth position approximately equal to the bottom of the first contact region 38 (second contact region 79).
  • the semiconductor device 1 includes at least one (preferably 2 to 20) p-type field region 93 formed in the surface layer of the outer peripheral surface 9 in a region between the periphery of the outer peripheral surface 9 and the outer well region 91.
  • the semiconductor device 1 includes four field regions 93.
  • the multiple field regions 93 are formed in an electrically floating state and reduce the electric field within the chip 2 at the outer peripheral surface 9.
  • the number, width, depth, p-type impurity concentration, etc. of the field regions 93 are arbitrary and can take various values depending on the electric field to be relaxed.
  • the field regions 93 may have a lower p-type impurity concentration than the outer contact region 92.
  • the field regions 93 may have a higher p-type impurity concentration than the outer well region 91.
  • the field regions 93 may have a lower p-type impurity concentration than the outer well region 91.
  • the multiple field regions 93 are arranged at intervals from the outer well region 91 side to the peripheral edge side of the outer peripheral surface 9.
  • the multiple field regions 93 are formed in a band shape extending along the active surface 8 in a plan view.
  • the multiple field regions 93 are formed in a ring shape (specifically, a square ring shape) surrounding the active surface 8 in a plan view.
  • the multiple field regions 93 are formed at intervals from the bottom of the first semiconductor region 6 toward the outer circumferential surface 9, and face the second semiconductor region 7 across a portion of the first semiconductor region 6.
  • the multiple field regions 93 are located closer to the bottom of the first semiconductor region 6 than the bottom wall of the first trench source structure 25.
  • the bottoms of the multiple field regions 93 are located closer to the bottom of the first semiconductor region 6 than the bottom of the first contact region 38.
  • the bottoms of the multiple field regions 93 may be formed at a depth position approximately equal to the bottom of the second well region 36.
  • the semiconductor device 1 includes a sidewall wiring 95 formed on the outer peripheral surface 9 so as to cover at least one of the first to fourth connection surfaces 10A to 10D. Specifically, the sidewall wiring 95 is disposed on the main surface insulating film 16. The sidewall wiring 95 also functions as a sidewall structure that reduces the step formed between the active surface 8 and the outer peripheral surface 9.
  • the sidewall wiring 95 is preferably formed in a band shape extending along at least one of the third connection surface 10C and the fourth connection surface 10D.
  • the sidewall wiring 95 is formed in a ring shape (specifically, a square ring shape) extending along the first to fourth connection surfaces 10A to 10D so as to surround the active surface 8 in a plan view.
  • the portions of the sidewall wiring 95 that cover the four corners of the active surface 8 are formed in a curved shape toward the outer circumferential surface 9.
  • the sidewall wiring 95 includes a portion that extends in a film-like manner along the outer peripheral surface 9, and a portion that extends in a film-like manner along the first to fourth connection surfaces 10A to 10D.
  • the portion of the sidewall wiring 95 located on the outer peripheral surface 9 may cover the outer peripheral surface 9 in a region on the outer peripheral surface 9 side relative to the active surface 8.
  • the portion of the sidewall wiring 95 located on the outer peripheral surface 9 may have a thickness less than the thickness of the active plateau 11 (outer peripheral depth DO).
  • the sidewall wiring 95 faces the outer well region 91 on the outer peripheral surface 9, with the main surface insulating film 16 in between.
  • the sidewall wiring 95 may also face the outer contact region 92, with the main surface insulating film 16 in between.
  • the sidewall wiring 95 is formed at a distance from the field region 93 toward the active surface 8 in a plan view.
  • the sidewall wiring 95 faces the second well region 36, the third well region 37, the sixth well region 77, the seventh well region 78, the eighth well region 90, and the outer well region 91 at the first to fourth connection surfaces 10A to 10D, with the main surface insulating film 16 in between.
  • the sidewall wiring 95 also faces the body region 17, with the main surface insulating film 16 in between.
  • the sidewall wiring 95 covers the exposed portion of the first trench source structure 25, the exposed portion of the second trench source structure 30, the exposed portion of the first dummy trench structure 61, the exposed portion of the second dummy trench structure 62, and the exposed portion of the trench termination structure 86 at the first to fourth connection surfaces 10A to 10D.
  • the sidewall wiring 95 is electrically connected to the first trench source structure 25, the second trench source structure 30, the first dummy trench structure 61, the second dummy trench structure 62, and the trench termination structure 86.
  • the sidewall wiring 95 applies the source potential VS to the connection target from the outer peripheral surface 9 side.
  • the sidewall wiring 95 has an overlapping portion 96 that extends from at least one of the first to fourth connection surfaces 10A to 10D onto the edge of the active surface 8.
  • the overlapping portion 96 covers the active surface 8 in a film-like manner in a plan view, and is formed in a band shape extending along the edge of the active surface 8.
  • the overlapping portion 96 is formed in a ring shape (specifically, a square ring shape) that surrounds the inner part of the active surface 8 in a plan view.
  • the overlap portion 96 is electrically connected to the first trench source structure 25, the second trench source structure 30, the first dummy trench structure 61, the second dummy trench structure 62 and the trench termination structure 86 on the active surface 8.
  • the sidewall wiring 95 includes conductive polysilicon and is formed integrally with the first source buried electrode 28, the second source buried electrode 33, the first dummy buried electrode 65, the second dummy buried electrode 68, and the termination buried electrode 89.
  • the sidewall wiring 95 may be formed separately from the first source buried electrode 28, the second source buried electrode 33, the first dummy buried electrode 65, the second dummy buried electrode 68, and the termination buried electrode 89.
  • the semiconductor device 1 includes an interlayer insulating film 99 that covers the main surface insulating film 16.
  • the interlayer insulating film 99 covers the active surface 8, the outer peripheral surface 9, and the first to fourth connection surfaces 10A to 10D with the main surface insulating film 16 in between.
  • the interlayer insulating film 99 covers the trench gate structure 20, the first trench source structure 25, the second trench source structure 30, the first trench resistor structure 42, the second trench resistor structure 43, the first dummy trench structure 61, the second dummy trench structure 62, and the trench termination structure 86 on the active surface 8.
  • the interlayer insulating film 99 covers the resistive film 50 in the first termination region 15A, and covers the multiple trench resistance structures 41 with the resistive film 50 in between.
  • the interlayer insulating film 99 covers the outer well region 91, the outer contact region 92, and the multiple field regions 93 with the main surface insulating film 16 in between at the outer peripheral surface 9.
  • the interlayer insulating film 99 covers the sidewall wiring 95 at the first to fourth connection surfaces 10A to 10D.
  • the interlayer insulating film 99 is continuous with the first to fourth side surfaces 5A to 5D.
  • the wall portion of the interlayer insulating film 99 may be formed at a distance inward from the periphery of the outer peripheral surface 9, exposing the first semiconductor region 6 from the periphery of the outer peripheral surface 9.
  • the interlayer insulating film 99 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the interlayer insulating film 99 includes a silicon oxide film.
  • the semiconductor device 1 includes a gate electrode 100 disposed on an interlayer insulating film 99.
  • the gate electrode 100 has a resistance value lower than the resistance value of the gate resistor 40.
  • the gate electrode 100 has a resistance value lower than the resistance value of the trench resistor structure 41.
  • the gate electrode 100 also has a resistance value lower than the resistance value of the resistive film 50.
  • the gate electrode 100 is preferably thicker than the resistive film 50.
  • the gate electrode 100 is preferably thicker than the interlayer insulating film 99.
  • the gate electrode 100 may have a thickness of 0.5 ⁇ m or more and 10 ⁇ m or less.
  • the thickness of the gate electrode 100 is preferably 1 ⁇ m or more and 5 ⁇ m or less.
  • the gate electrode 100 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film.
  • the gate electrode 100 may include at least one of a pure Cu film (Cu film with a purity of 99% or more), a pure Al film (Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film.
  • the gate electrode 100 has a layered structure including a Ti film and an Al alloy film (an AlSiCu alloy film in this embodiment) layered in this order from the chip 2 side.
  • the gate electrode 100 may be referred to as a "gate metal".
  • the gate electrode 100 includes a gate pad 101, a gate wiring 102, and a gate subpad 103.
  • a gate potential VG is applied to the gate pad 101 from the outside.
  • the gate pad 101 is disposed in a region along the center of the first connection surface 10A in a plan view.
  • the gate pad 101 is disposed on the inner portion of the active surface 8 at a distance from the periphery of the active surface 8, and is not disposed on the outer peripheral surface 9.
  • the gate pad 101 is disposed in a region that overlaps the active region 12 and the first termination region 15A in a plan view.
  • the gate pad 101 covers the multiple trench gate structures 20 and the multiple first trench source structures 25 in the active region 12 with the interlayer insulating film 99 in between.
  • the gate pad 101 is disposed in a region that overlaps the gate resistor 40 in a planar view.
  • the gate pad 101 is formed at a distance from the dummy structure 55 and the termination dummy structure 85 in a planar view.
  • the gate pad 101 may be disposed in a region that overlaps with either or both of the dummy structure 55 and the termination dummy structure 85 in a planar view.
  • the gate pad 101 is electrically connected to the gate resistor 40 through the interlayer insulating film 99 in the first termination region 15A. Specifically, the gate pad 101 is connected to the resistive film 50 through the interlayer insulating film 99. In this embodiment, the gate pad 101 is connected to the center of the resistive film 50 through the interlayer insulating film 99.
  • the gate pad 101 faces one or more (in this embodiment, multiple) trench resistance structures 41 across the resistive film 50. In this embodiment, the gate pad 101 faces multiple first trench resistance structures 42 and multiple second trench resistance structures 43 across the resistive film 50.
  • the gate pad 101 includes a pad body 104 and an extraction portion 105.
  • the pad body 104 is a portion to which a gate potential VG is applied from the outside.
  • the pad body 104 is disposed on a portion of the interlayer insulating film 99 that covers the active region 12, and faces the gate resistor 40 in the second direction Y in a plan view.
  • the pad body 104 covers the multiple trench gate structures 20 and the multiple first trench source structures 25 with the interlayer insulating film 99 in between.
  • the pad body 104 is formed to be wider than the gate resistor 40 (trench gate structure 20) in the first direction X.
  • the pad main body 104 is formed in a rectangular shape in a plan view. It is preferable that the pad main body 104 has a plan area that is 25% or less of the plan area of the first main surface 3. It is preferable that the plan area of the pad main body 104 is 10% or less of the plan area of the first main surface 3.
  • the draw-out portion 105 is a portion that electrically connects the pad body portion 104 to the gate resistor 40.
  • the draw-out portion 105 is drawn out in a strip shape from the pad body portion 104 onto a portion of the interlayer insulating film 99 that covers the gate resistor 40.
  • the draw-out portion 105 is formed narrower than the pad body portion 104 in the first direction X.
  • the draw-out portion 105 is formed narrower than the gate resistor 40 (trench gate structure 20) in the first direction X.
  • the lead-out portion 105 is connected to the gate resistor 40 via a first resistor opening 106 formed in the interlayer insulating film 99. Specifically, the lead-out portion 105 is connected to the resistive film 50 within the first resistor opening 106. In other words, the lead-out portion 105 is electrically connected to the multiple trench resistor structures 41 via the resistive film 50.
  • the pad main body 104 is electrically connected to the multiple trench resistance structures 41 and the resistive film 50 via the lead-out portion 105.
  • the lead-out portion 105 faces one or multiple (multiple in this embodiment) trench resistance structures 41 across the resistive film 50.
  • the lead-out portion 105 faces multiple first trench resistance structures 42 and multiple second trench resistance structures 43 across the resistive film 50.
  • the gate wiring 102 is selectively routed from the first termination region 15A toward the active region 12 so as to transmit the gate potential VG applied to the gate pad 101 to the multiple trench gate structures 20.
  • the gate wiring 102 is disposed on the inner portion of the active surface 8 at a distance from the periphery of the active surface 8, and is not disposed on the outer periphery 9.
  • the gate wiring 102 is disposed on the interlayer insulating film 99 at a distance from the gate pad 101 in the first termination region 15A.
  • the gate wiring 102 penetrates the interlayer insulating film 99 at a position different from the gate pad 101 and is electrically connected to the gate resistor 40.
  • the gate wiring 102 penetrates the interlayer insulating film 99 and is connected to the resistive film 50.
  • the gate wiring 102 is electrically connected to the gate pad 101 via the multiple trench resistor structures 41 and the resistive film 50.
  • the gate wiring 102 faces one or more (multiple in this embodiment) trench resistance structures 41 across the resistive film 50.
  • the gate wiring 102 faces a plurality of first trench resistance structures 42 and a plurality of second trench resistance structures 43 across the resistive film 50.
  • the gate wiring 102 extends in a line shape so as to intersect (specifically, perpendicular to) the multiple trench gate structures 20 in the active region 12, and is electrically connected to the multiple trench gate structures 20 by penetrating the interlayer insulating film 99.
  • the gate wiring 102 includes a first gate wiring 102A, a second gate wiring 102B, and a third gate wiring 102C.
  • the first gate wiring 102A is disposed in a region on the third connection surface 10C side of the gate pad 101, and extends in a line along the first connection surface 10A and the third connection surface 10C.
  • the first gate wiring 102A is electrically connected to the gate pad 101 via a gate resistor 40 in the first termination region 15A, and is electrically connected to a plurality of trench gate structures 20 in the active region 12.
  • the first gate wiring 102A extends in a line in the first direction X so as to cover the gate resistor 40 and the dummy structure 55 (first dummy structure 56) in the first termination region 15A.
  • the first gate wiring 102A is disposed on a portion of the interlayer insulating film 99 that covers the gate resistor 40, spaced apart from the gate pad 101.
  • the first gate wiring 102A is connected to the gate resistor 40 via a second resistor opening 107 formed in the interlayer insulating film 99 at a distance from the first resistor opening 106.
  • the first gate wiring 102A is connected to a region on one end side (the third connection surface 10C side) of the gate resistor 40 at a distance from the connection position of the gate pad 101.
  • the first gate wiring 102A is connected to the resistive film 50 within the second resistive opening 107. That is, the first gate wiring 102A is electrically connected to the multiple trench resistance structures 41 via the resistive film 50.
  • the first gate wiring 102A faces one or multiple (multiple in this embodiment) trench resistance structures 41 across the resistive film 50. In this embodiment, the first gate wiring 102A faces multiple first trench resistance structures 42 and multiple second trench resistance structures 43 across the resistive film 50.
  • the first gate wiring 102A extends in a line in the second direction Y so as to intersect (specifically, perpendicularly) with the multiple trench gate structures 20 in the active region 12.
  • the first gate wiring 102A is electrically connected to the multiple gate connection electrode films 39 via the multiple gate openings 108 formed in the interlayer insulating film 99.
  • the first gate wiring 102A is electrically connected to the multiple trench gate structures 20 via the multiple gate connection electrode films 39.
  • the portion of the first gate wiring 102A that extends in a line in the second direction Y in the active region 12 is an example of a "peripheral gate wiring" in this disclosure.
  • connection height position of the first gate wiring 102A to the gate connection electrode film 39 may be approximately equal to the connection height position of the first gate wiring 102A to the resistive film 50.
  • the connection height position of the first gate wiring 102A to the gate connection electrode film 39 may be located closer to the active surface 8 than the connection height position of the second gate wiring 102B to the resistive film 50.
  • the connection height position of the first gate wiring 102A to the gate connection electrode film 39 may be located higher than the connection height position of the second gate wiring 102B to the resistive film 50.
  • the second gate wiring 102B is disposed in a region on the fourth connection surface 10D side of the gate pad 101, and extends in a line along the first connection surface 10A and the fourth connection surface 10D.
  • the second gate wiring 102B is electrically connected to the gate pad 101 via the gate resistor 40 in the first termination region 15A, and is electrically connected to a plurality of trench gate structures 20 in the active region 12.
  • the second gate wiring 102B is electrically connected to a plurality of trench gate structures 20 electrically connected to the first gate wiring 102A.
  • the second gate wiring 102B extends in a line in the first direction X so as to cover the gate resistor 40 and the dummy structure 55 (second dummy structure 57) in the first termination region 15A.
  • the second gate wiring 102B is disposed on a portion of the interlayer insulating film 99 that covers the gate resistor 40, spaced apart from the gate pad 101.
  • the second gate wiring 102B is connected to the gate resistor 40 via a third resistor opening 109 formed in the interlayer insulating film 99 at a distance from the first resistor opening 106 and the second resistor opening 107.
  • the second gate wiring 102B is connected to a region on the other end side (the fourth connection surface 10D side) of the gate resistor 40 at a distance from the connection position of the gate pad 101.
  • the second gate wiring 102B is connected to the resistive film 50 within the third resistance opening 109. That is, the second gate wiring 102B is electrically connected to the multiple trench resistance structures 41 via the resistive film 50.
  • the second gate wiring 102B faces one or multiple (multiple in this embodiment) trench resistance structures 41 across the resistive film 50. In this embodiment, the second gate wiring 102B faces multiple first trench resistance structures 42 and multiple second trench resistance structures 43 across the resistive film 50.
  • the second gate wiring 102B extends in a line in the second direction Y so as to intersect (specifically, perpendicular to) the multiple trench gate structures 20 in the active region 12.
  • the second gate wiring 102B is electrically connected to the multiple gate connection electrode films 39 via the multiple gate openings 108 formed in the interlayer insulating film 99.
  • the second gate wiring 102B is electrically connected to the multiple trench gate structures 20 via the multiple gate connection electrode films 39.
  • connection height position of the second gate wiring 102B to the gate connection electrode film 39 may be approximately equal to the connection height position of the second gate wiring 102B to the resistive film 50.
  • connection height position of the second gate wiring 102B to the gate connection electrode film 39 may be located closer to the active surface 8 than the connection height position of the second gate wiring 102B to the resistive film 50.
  • connection height position of the second gate wiring 102B to the gate connection electrode film 39 may be located higher than the connection height position of the second gate wiring 102B to the resistive film 50.
  • the third gate wiring 102C is disposed in a region on the second connection surface 10B side of the gate pad 101, and extends in a line shape along the second direction Y in the region between the gate pad 101 and the second connection surface 10B.
  • the third gate wiring 102C is connected to the first gate wiring 102A and the second gate wiring 102B in the first termination region 15A, and is electrically connected to a plurality of trench gate structures 20 in the active region 12.
  • the third gate wiring 102C is electrically connected to the gate resistor 40 via the first gate wiring 102A, and is electrically connected to the gate resistor 40 via the second gate wiring 102B.
  • the portion of the first gate wiring 102A connected to the gate resistor 40 and the portion of the second gate wiring 102B connected to the gate resistor 40 may be considered as part of the third gate wiring 102C.
  • the third gate wiring 102C is electrically connected to a plurality of trench gate structures 20 electrically connected to the first gate wiring 102A and the second gate wiring 102B in the active region 12.
  • the third gate wiring 102C includes a line portion 110, a first branch portion 111, and a second branch portion 112.
  • the line portion 110 extends in a line shape along the second direction Y in the region between the gate pad 101 and the second connection surface 10B.
  • the line portion 110 has a first end portion on the gate pad 101 side and a second end portion on the second connection surface 10B side.
  • the first end portion is formed at a distance from the gate pad 101 to the second connection surface 10B side.
  • the second end portion is formed at a distance from the second connection surface 10B to the gate pad 101 side.
  • the line portion 110 is an example of a "central gate wiring" in this disclosure.
  • the line portion 110 is electrically connected to the multiple trench gate structures 20 via multiple gate openings 108 formed in the interlayer insulating film 99.
  • Multiple gate connection electrode films 39 may be formed to cover the inner portions of the multiple trench gate structures 20. In this case, the line portion 110 is electrically connected to the multiple trench gate structures 20 via the multiple gate connection electrode films 39.
  • connection height position of the line portion 110 to the gate connection electrode film 39 may be approximately equal to the connection height position of the first gate wiring 102A (second gate wiring 102B) to the resistive film 50.
  • connection height position of the line portion 110 to the gate connection electrode film 39 may be located closer to the active surface 8 than the connection height position of the second gate wiring 102B to the resistive film 50.
  • connection height position of the line portion 110 to the gate connection electrode film 39 may be located higher than the connection height position of the second gate wiring 102B to the resistive film 50.
  • the first branch portion 111 connects the line portion 110 and the first gate wiring 102A.
  • the first branch portion 111 is pulled out from the first end of the line portion 110 to one side (the third connection surface 10C side) and extends in a strip shape along the gate pad 101.
  • the first branch portion 111 is connected to a portion of the first gate wiring 102A that covers the dummy structure 55 (first dummy structure 56).
  • the first branch portion 111 may be connected to a portion of the first gate wiring 102A that covers the gate resistor 40. In a portion extending in the second direction Y, the first branch portion 111 is electrically connected to a plurality of trench gate structures 20 via a plurality of gate openings 108 formed in the interlayer insulating film 99. The first branch portion 111 may be electrically connected to a plurality of trench gate structures 20 via a plurality of gate connection electrode films 39.
  • the second branch portion 112 connects the line portion 110 and the second gate wiring 102B.
  • the second branch portion 112 is pulled out from the first end of the line portion 110 to the other side (the fourth connection surface 10D side) and extends in a band shape along the periphery of the gate pad 101.
  • the second branch portion 112 faces the first branch portion 111 across the gate pad 101 in the first direction X.
  • the second branch portion 112 is connected to a portion of the second gate wiring 102B that covers the dummy structure 55 (second dummy structure 57).
  • the second branch portion 112 may be connected to a portion of the second gate wiring 102B that covers the gate resistor 40. In a portion extending in the second direction Y, the second branch portion 112 is electrically connected to a plurality of trench gate structures 20 via a plurality of gate openings 108 formed in the interlayer insulating film 99. The second branch portion 112 may be electrically connected to a plurality of trench gate structures 20 via a plurality of gate connection electrode films 39.
  • the gate subpad 103 is disposed on the interlayer insulating film 99 so as to be electrically connected to the gate pad 101 via the gate resistor 40.
  • the gate subpad 103 is disposed at a distance from the gate pad 101 toward the third connection surface 10C, and faces the gate pad 101 in the first direction X.
  • the gate subpad 103 is disposed on a portion of the interlayer insulating film 99 that covers the active region 12, spaced apart from the first termination region 15A in a plan view.
  • the gate subpad 103 faces the dummy structure 55 (first dummy structure 56) in the second direction Y in a plan view.
  • the gate subpad 103 is formed narrower than the gate pad 101 and wider than the gate wiring 102.
  • the gate subpad 103 faces the multiple trench gate structures 20 and the multiple first trench source structures 25 across the interlayer insulating film 99.
  • the gate subpad 103 is electrically connected to the gate wiring 102.
  • the gate subpad 103 is connected to the third gate wiring 102C (first branch portion 111).
  • the gate subpad 103 only needs to be connected to at least one of the first to third gate wirings 102A to 102C, and the location of the gate subpad 103 is arbitrary.
  • FIG. 27 is an electrical circuit diagram showing the connection form of the gate electrode 100 and the gate resistor 40.
  • the trench gate structure 20 is shown by a circuit symbol indicating a MISFET.
  • the gate wiring 102 is electrically connected to the gate pad 101 via the gate resistor 40.
  • the gate resistor 40 includes a resistive parallel circuit 113 composed of a first resistor portion R1 and a second resistor portion R2.
  • the first resistor portion R1 is formed by a portion of the gate resistor 40 located between the connection portion of the gate pad 101 and the connection portion of the first gate wiring 102A.
  • the second resistor portion R2 is formed by a portion of the gate resistor 40 located between the connection portion of the gate pad 101 and the connection portion of the second gate wiring 102B.
  • the first gate wiring 102A is electrically connected to the gate pad 101 via the first resistance portion R1
  • the second gate wiring 102B is electrically connected to the gate pad 101 via the second resistance portion R2.
  • the resistance value of the first resistance portion R1 is adjusted by increasing or decreasing the distance between the connection portion of the gate pad 101 and the connection portion of the first gate wiring 102A.
  • the resistance value of the second resistor R2 is adjusted by increasing or decreasing the distance between the connection part of the gate pad 101 and the connection part of the second gate wiring 102B.
  • the resistance value of the second resistor R2 may be equal to or greater than the resistance value of the first resistor R1, may be less than the resistance value of the first resistor R1, or may be approximately equal to the resistance value of the first resistor R1.
  • the second gate wiring 102B is electrically connected to the trench gate structure 20 that is electrically connected to the first gate wiring 102A. Therefore, the second resistance portion R2 is connected in parallel to the first resistance portion R1, thereby forming a resistive parallel circuit 113.
  • the third gate wiring 102C is electrically connected to the trench gate structure 20 that is electrically connected to the first gate wiring 102A and the second gate wiring 102B.
  • one gate wiring 102 including the first to third gate wirings 102A to 102C is electrically connected to the resistive parallel circuit 113 and the trench gate structure 20.
  • the resistance value of the gate resistor 40 i.e., the resistance value between the gate pad 101 and the gate wiring 102 is indirectly measured by measuring the resistance value between the gate pad 101 and the gate subpad 103.
  • the gate resistor 40 suppresses surge currents by slowing down the switching speed during switching operations. In other words, the gate resistor 40 suppresses noise caused by surge currents. Because the gate resistor 40 is formed on the first main surface 3 (active surface 8), it is not externally connected to the semiconductor device 1. Therefore, by incorporating the gate resistor 40 into the first main surface 3, the number of components mounted on the circuit board is reduced.
  • the gate resistor 40 includes a trench resistor structure 41 embedded in the thickness direction of the chip 2, the area occupied by the gate resistor 40 relative to the first main surface 3 is limited. Therefore, the reduction in the area of the active region 12 caused by the introduction of the gate resistor 40 is suppressed. In particular, since the gate resistor 40 is disposed in the termination region 15, the reduction in the area of the active region 12 is appropriately suppressed.
  • the gate resistor 40 has a configuration similar to that of the active region 12. Therefore, the electrical influence of the gate resistor 40 on the active region 12 is suppressed, and the electrical influence of the active region 12 on the gate resistor 40 is suppressed. This suppresses fluctuations in the electrical characteristics on the active region 12 side, and suppresses fluctuations in the electrical characteristics on the gate resistor 40 side.
  • the gate resistor 40 does not necessarily have to have a resistive parallel circuit 113 including the first resistive portion R1 and the second resistive portion R2. Therefore, the gate resistor 40 may be composed of only the first resistive portion R1 or the second resistive portion R2. Such a configuration is achieved by changing the connection configuration of the gate wiring 102 to the gate resistor 40.
  • the gate wiring 102 (second gate wiring 102B) can be electrically disconnected from the gate resistor 40.
  • the gate wiring 102 (first gate wiring 102A) can be electrically disconnected from the gate resistor 40.
  • the gate wiring 102 does not need to include all of the first to third gate wirings 102A to 102C at the same time, but only needs to include at least one of the first to third gate wirings 102A to 102C.
  • the semiconductor device 1 includes a source electrode 120 disposed on an interlayer insulating film 99 at a distance from the gate electrode 100.
  • the source electrode 120 has a resistance value lower than that of the gate resistor 40.
  • the source electrode 120 is preferably thicker than the resistive film 50.
  • the source electrode 120 is preferably thicker than the interlayer insulating film 99.
  • the source electrode 120 may have a thickness of 0.5 ⁇ m or more and 10 ⁇ m or less.
  • the thickness of the source electrode 120 is preferably 1 ⁇ m or more and 5 ⁇ m or less.
  • the thickness of the source electrode 120 is preferably approximately equal to the thickness of the gate electrode 100.
  • the source electrode 120 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film.
  • the source electrode 120 may include at least one of a pure Cu film (Cu film with a purity of 99% or more), a pure Al film (Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film.
  • the source electrode 120 has a layered structure including a Ti film and an Al alloy film (AlSiCu alloy film in this embodiment) layered in this order from the chip 2 side.
  • the source electrode 120 may be referred to as a "source metal".
  • the source electrode 120 includes a first source pad 121, a second source pad 122, a first source sub-pad 123, a second source sub-pad 124, and a source wiring 125.
  • a source potential VS for the main source is applied to the first source pad 121 from the outside.
  • the first source pad 121 is disposed in the region between the first gate wiring 102A and the third gate wiring 102C on the portion of the interlayer insulating film 99 that covers the active region 12.
  • the first source pad 121 covers the active region 12 at a distance from the peripheral region 14 and the termination region 15 in a plan view.
  • the first source pad 121 may be disposed in a region that overlaps with either or both of the peripheral region 14 and the termination region 15 in a plan view.
  • the first source pad 121 faces the multiple trench gate structures 20 across the interlayer insulating film 99.
  • the first source pad 121 is electrically connected to the multiple first trench source structures 25, the source region 18, and the multiple first contact regions 38 via multiple source openings 126 formed in the interlayer insulating film 99.
  • the first source pad 121 preferably has a planar area larger than the planar area of the gate pad 101.
  • the second source pad 122 is supplied with a source potential VS for the main source from the outside.
  • the second source pad 122 is disposed in the region between the second gate wiring 102B and the third gate wiring 102C on the portion of the interlayer insulating film 99 that covers the active region 12.
  • the second source pad 122 covers the active region 12 at a distance from the peripheral region 14 and the termination region 15 in a plan view.
  • the second source pad 122 may be disposed in a region that overlaps with either or both of the peripheral region 14 and the termination region 15 in a plan view.
  • the second source pad 122 faces the multiple trench gate structures 20 with the interlayer insulating film 99 interposed therebetween.
  • the second source pad 122 is electrically connected to the first trench source structures 25, the source region 18, and the first contact regions 38 through a plurality of source openings 126 formed in the interlayer insulating film 99.
  • the second source pad 122 preferably has a planar area larger than the planar area of the gate pad 101.
  • the first source subpad 123 is supplied with a source potential VS for source sensing from the outside.
  • the first source subpad 123 is disposed in the region between the gate pad 101 and the first gate wiring 102A (third connection surface 10C) on the portion of the interlayer insulating film 99 that covers the active region 12.
  • the first source subpad 123 has a planar area less than the planar area of the first source pad 121 and is formed integrally with the first source pad 121. It is preferable that the planar area of the first source subpad 123 is greater than the planar area of the gate subpad 103. It is particularly preferable that the planar area of the first source subpad 123 is greater than the planar area of the gate pad 101.
  • the first source subpad 123 covers the active region 12 at a distance from the peripheral region 14 and the termination region 15 in a plan view.
  • the first source subpad 123 may be disposed in a region that overlaps with either or both of the peripheral region 14 and the termination region 15 in a plan view.
  • the first source subpad 123 faces the multiple trench gate structures 20 across the interlayer insulating film 99.
  • the first source subpad 123 is electrically connected to the multiple first trench source structures 25, the source region 18, and the multiple first contact regions 38 via multiple source openings 126 formed in the interlayer insulating film 99.
  • the second source subpad 124 is supplied with a source potential VS for source sensing from the outside.
  • the second source subpad 124 is disposed in the region between the gate pad 101 and the second gate wiring 102B (fourth connection surface 10D) on the portion of the interlayer insulating film 99 that covers the active region 12.
  • the second source subpad 124 has a plan area less than the plan area of the second source pad 122 and is formed integrally with the second source pad 122. It is preferable that the plan area of the second source subpad 124 is greater than the plan area of the gate subpad 103. It is particularly preferable that the plan area of the second source subpad 124 is greater than the plan area of the gate pad 101.
  • the second source subpad 124 covers the active region 12 at a distance from the peripheral region 14 and the termination region 15 in a plan view.
  • the second source subpad 124 may be disposed in a region overlapping either or both of the peripheral region 14 and the termination region 15 in a plan view.
  • the second source subpad 124 faces the multiple trench gate structures 20 with the interlayer insulating film 99 in between.
  • the second source subpad 124 is electrically connected to the multiple first trench source structures 25, the source region 18, and the multiple first contact regions 38 via the multiple source openings 126 formed in the interlayer insulating film 99.
  • the total planar area of the first source pad 121, the second source pad 122, the first source sub-pad 123, and the second source sub-pad 124 is preferably 50% or more and 90% or less of the planar area of the first main surface 3. It is particularly preferable that the total planar area is 75% or more of the planar area of the first main surface 3.
  • the source wiring 125 transmits the source potential VS applied to the first source pad 121 and the second source pad 122 to other regions.
  • the source wiring 125 is drawn out from the first source pad 121 and the second source pad 122 so as to be located closer to the outer periphery region 13 than the gate wiring 102.
  • the source wiring 125 is drawn out from the active surface 8 side to the outer peripheral surface 9 side, passing through the first to fourth connection surfaces 10A to 10D.
  • the source wiring 125 is formed in a strip shape extending along the first to fourth connection surfaces 10A to 10D. In other words, the source wiring 125 faces the sidewall wiring 95 with the interlayer insulating film 99 in between.
  • the source wiring 125 is formed in a ring shape (specifically, a square ring shape) extending along the first to fourth connection surfaces 10A to 10D, and surrounds the gate wiring 102.
  • the source wiring 125 is electrically connected to the sidewall wiring 95 and the outer contact region 92 via an outer opening 127 formed in the interlayer insulating film 99.
  • the outer opening 127 is formed in a strip or ring shape extending along the sidewall wiring 95 and the outer contact region 92.
  • the source potential VS applied to the source wiring 125 is transmitted to the first trench source structure 25, the second trench source structure 30, the first dummy trench structure 61, the second dummy trench structure 62, and the trench termination structure 86 via the sidewall wiring 95.
  • the straight portion of the source wiring 125 that extends along the first side surface 5A is an example of a "first source wiring” in this disclosure.
  • the outer contact region 92 to which the straight portion of the source wiring 125 that extends along the first side surface 5A is electrically connected via the outer opening 127 is an example of a "first outer contact region" in this disclosure.
  • the straight portion of the source wiring 125 extending along the third side surface 5C and the straight portion extending along the fourth side surface 5D are an example of a "second source wiring" in this disclosure.
  • the outer contact region 92 to which the straight portion of the source wiring 125 extending along the third side surface 5C and the straight portion extending along the fourth side surface 5D are electrically connected via the outer opening 127 is an example of a "second outer contact region" in this disclosure.
  • the semiconductor device 1 includes an upper insulating film 130 that selectively covers the gate electrode 100, the source electrode 120, and the interlayer insulating film 99 on the first main surface 3.
  • the upper insulating film 130 includes a gate pad opening 131 that exposes the inner portion of the gate pad 101, and a gate subpad opening 132 that exposes the inner portion of the gate subpad 103.
  • the upper insulating film 130 covers the periphery of the gate pad 101, the periphery of the gate subpad 103, and the entire gate wiring 102.
  • the gate pad opening 131 is formed in a rectangular shape in a plan view.
  • the gate subpad opening 132 is formed in a rectangular shape in a plan view.
  • the gate subpad opening 132 has a plan area smaller than the plan area of the gate pad opening 131.
  • the upper insulating film 130 includes a first source pad opening 133 exposing the inner portion of the first source pad 121, a second source pad opening 134 exposing the inner portion of the second source pad 122, a first source subpad opening 135 exposing the inner portion of the first source subpad 123, and a second source subpad opening 136 exposing the inner portion of the second source subpad 124.
  • the upper insulating film 130 covers the periphery of the first source pad 121, the periphery of the second source pad 122, the periphery of the first source subpad 123, the periphery of the second source subpad 124, and the entire area of the source wiring 125.
  • the first source pad opening 133 is formed in a rectangular shape in a plan view.
  • the first source pad opening 133 has a plan area larger than the plan area of the gate subpad opening 132. It is preferable that the plan area of the first source pad opening 133 is larger than the plan area of the gate pad opening 131.
  • the second source pad opening 134 is formed in a rectangular shape in a plan view.
  • the second source pad opening 134 has a plan area larger than the plan area of the gate subpad opening 132. It is preferable that the plan area of the second source pad opening 134 is larger than the plan area of the gate pad opening 131. It is preferable that the plan area of the second source pad opening 134 is approximately equal to the plan area of the first source pad opening 133.
  • the first source subpad opening 135 is formed in a rectangular shape in a plan view.
  • the first source subpad opening 135 has a plan area smaller than the plan area of the first source pad opening 133.
  • the plan area of the first source subpad opening 135 is preferably larger than the plan area of the gate subpad opening 132.
  • the plan area of the first source subpad opening 135 is larger than the plan area of the gate pad opening 131.
  • the plan area of the first source subpad opening 135 may be smaller than the plan area of the gate pad opening 131.
  • the second source subpad opening 136 is formed in a rectangular shape in a plan view.
  • the second source subpad opening 136 has a plan area smaller than the plan area of the second source pad opening 134. It is preferable that the plan area of the second source subpad opening 136 is larger than the plan area of the gate subpad opening 132.
  • the plane area of the second source subpad opening 136 is larger than the plane area of the gate pad opening 131.
  • the plane area of the second source subpad opening 136 may be less than the plane area of the gate pad opening 131. It is preferable that the plane area of the second source subpad opening 136 is approximately equal to the plane area of the first source subpad opening 135.
  • the upper insulating film 130 is formed at a distance inward from the periphery of the chip 2 (first to fourth side surfaces 5A to 5D), and defines a dicing street 137 between the upper insulating film 130 and the periphery of the chip 2.
  • the dicing street 137 is formed in a band shape extending along the periphery of the chip 2 in a plan view.
  • the dicing street 137 is formed in a ring shape (specifically, a square ring) surrounding the active surface 8 in a plan view.
  • the dicing street 137 exposes the interlayer insulating film 99.
  • the dicing street 137 may also expose the outer peripheral surface 9.
  • the dicing street 137 may have a width of 1 ⁇ m or more and 200 ⁇ m or less.
  • the width of the dicing street 137 is the width in a direction perpendicular to the extension direction of the dicing street 137.
  • the width of the dicing street 137 is preferably 5 ⁇ m or more and 50 ⁇ m or less.
  • the upper insulating film 130 preferably has a thickness that exceeds the thickness of the gate electrode 100 and the thickness of the source electrode 120.
  • the thickness of the upper insulating film 130 is preferably less than the thickness of the chip 2.
  • the thickness of the upper insulating film 130 may be 3 ⁇ m or more and 35 ⁇ m or less.
  • the thickness of the upper insulating film 130 is preferably 25 ⁇ m or less.
  • the upper insulating film 130 has a layered structure including an inorganic insulating film 140 and an organic insulating film 141, which are layered in this order from the chip 2 side.
  • the upper insulating film 130 only needs to include at least one of the inorganic insulating film 140 and the organic insulating film 141, and does not necessarily need to include both the inorganic insulating film 140 and the organic insulating film 141 at the same time.
  • the inorganic insulating film 140 selectively covers the gate electrode 100, the source electrode 120 and the interlayer insulating film 99, and defines a portion of the gate pad opening 131, a portion of the gate subpad opening 132, a portion of the first source pad opening 133, a portion of the second source pad opening 134, a portion of the first source subpad opening 135, a portion of the second source subpad opening 136 and a portion of the dicing street 137.
  • the inorganic insulating film 140 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is preferable that the inorganic insulating film 140 includes an insulating material different from that of the interlayer insulating film 99. It is preferable that the inorganic insulating film 140 includes a silicon nitride film. It is preferable that the inorganic insulating film 140 has a thickness less than that of the interlayer insulating film 99. The thickness of the inorganic insulating film 140 may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the organic insulating film 141 selectively covers the inorganic insulating film 140 and defines a portion of the gate pad opening 131, a portion of the gate subpad opening 132, a portion of the first source pad opening 133, a portion of the second source pad opening 134, a portion of the first source subpad opening 135, a portion of the second source subpad opening 136, and a portion of the dicing street 137.
  • the organic insulating film 141 may expose the inorganic insulating film 140 on the wall surface of the gate pad opening 131.
  • the organic insulating film 141 may expose the inorganic insulating film 140 on the wall surface of the gate subpad opening 132.
  • the organic insulating film 141 may expose the inorganic insulating film 140 on the wall surface of the first source pad opening 133.
  • the organic insulating film 141 may expose the inorganic insulating film 140 on the wall surface of the second source pad opening 134.
  • the organic insulating film 141 may expose the inorganic insulating film 140 on the wall surface of the first source subpad opening 135.
  • the organic insulating film 141 may expose the inorganic insulating film 140 on the wall surface of the second source subpad opening 136.
  • the organic insulating film 141 may expose the inorganic insulating film 140 on the wall surface of the dicing street 137.
  • the organic insulating film 141 may cover the entire inorganic insulating film 140 so that the inorganic insulating film 140 is not exposed.
  • the organic insulating film 141 is preferably made of a resin film other than a thermosetting resin.
  • the organic insulating film 141 may be made of a translucent resin or a transparent resin.
  • the organic insulating film 141 may be made of a negative type or positive type photosensitive resin film.
  • the organic insulating film 141 is preferably made of a polyimide film, a polyamide film, or a polybenzoxazole film. In this embodiment, the organic insulating film 141 includes a polybenzoxazole film.
  • the organic insulating film 141 preferably has a thickness that exceeds the thickness of the inorganic insulating film 140.
  • the thickness of the organic insulating film 141 preferably exceeds the thickness of the interlayer insulating film 99. It is particularly preferable that the thickness of the organic insulating film 141 exceeds the thickness of the gate electrode 100 and the thickness of the source electrode 120.
  • the thickness of the organic insulating film 141 may be 3 ⁇ m or more and 30 ⁇ m or less.
  • the thickness of the organic insulating film 141 is preferably 20 ⁇ m or less.
  • the semiconductor device 1 includes a drain electrode 150 covering the second main surface 4.
  • the drain electrode 150 forms an ohmic contact with the second semiconductor region 7 exposed from the second main surface 4.
  • the drain electrode 150 may cover the entire second main surface 4 so as to be continuous with the periphery of the chip 2 (first to fourth side surfaces 5A to 5D).
  • the breakdown voltage that can be applied between the source electrode 120 and the drain electrode 150 (between the first main surface 3 and the second main surface 4) may be 500V or more and 3000V or less.
  • the resistive film 50 includes a portion 50a formed on the main surface insulating film 16, in other words, a portion 50a covering the main surface insulating film 16.
  • the gate connection electrode film 39 includes a portion 39b formed on the main surface insulating film 16, in other words, a portion 39b covering the main surface insulating film 16. The resistive film 50 and the gate connection electrode film 39 are electrically connected to the gate electrode 100.
  • gate connection conductive films 50a and 39b are examples of the "gate connection conductive film" of this disclosure.
  • p-type regions formed in the surface layer of the first semiconductor region 6, such as the p-type body region 17, the first well region 35, the second well region 36, the third well region 37, the fourth well region 75, the fifth well region 76, the sixth well region 77, and the outer well region 91 will be collectively referred to as the "p-type region.”
  • the "p-type region” is an example of the "first region” of this disclosure.
  • p-type contact regions that are formed on the surface layer of the "p-type region” and electrically connected to the source electrode 120, such as the first contact region 38 and the outer contact region 92, will be collectively referred to as p-type contact regions 38, 92.
  • the p-type contact regions 38, 92 are an example of a "contact region" in this disclosure.
  • the region where the source electrode 120 is bonded to the p-type contact region 38, 92 via the source opening 126 or the outer opening 127 will be collectively referred to as the "source/contact junction region.”
  • the "source/contact junction region” is the region of the p-type contact region 38, 92 where the source electrode 120 is bonded.
  • the distance through which the charging current ic flows within the "p-type region” should be shortened. In other words, the maximum distance between each position on the underside of the gate connection conductive film 50a, 39b and the "source/contact junction region" closest to it should be reduced.
  • the layout of the gate connection conductive films 50a, 39b, the "source/contact junction region”, etc. is designed so that the maximum distance between each position on the underside of the gate connection conductive films 50a, 39b and the "source/contact junction region" closest to it is 90 ⁇ m or less.
  • the layout of the gate connection conductive films 50a, 39b, the "source/contact junction region”, etc. so that the maximum distance between each position on the underside of the gate connection conductive films 50a, 39b and the "source/contact junction region” closest to it is 80 ⁇ m or less. Furthermore, it is even more preferable to design the layout of the gate connection conductive films 50a, 39b, the "source/contact junction region”, etc. so that the maximum distance between each position on the underside of the gate connection conductive films 50a, 39b and the "source/contact junction region” closest to it is 70 ⁇ m or less.
  • the layout in which the distance between the position on the underside of the gate connection conductive films 50a, 39b and the "source/contact junction region" closest to it is greatest in the semiconductor device 1 is present in the region E1 shown in FIG. 13.
  • FIG. 29 is a cross-sectional view taken along line XXIX-XXIX in FIG. 13.
  • the gate resistor 40 includes a resistive film 50. Therefore, the gate resistor 40 includes a gate connection conductive film 50a formed on the main surface insulating film 16.
  • the position where the minimum distance from each of all the "source/contact junction regions" in the semiconductor device 1 to that position is the largest is defined as the first position P1.
  • the position on the underside of the resistive film 50 (gate connection conductive film 50a) closest to the active region 12 side (pad body portion 104 side) is the first position P1.
  • the source wiring 125 includes a straight portion (hereinafter referred to as the "first source wiring 125") that extends along the trench resistor structure 41 (first side surface 5A) in the region opposite the active region 12 with respect to the gate resistor 40.
  • the region of the outer contact region 92 to which the "first source wiring 125" is connected and to which the "first source wiring 125" is bonded is referred to as the source/contact junction region 92A to which the "first source wiring 125" is bonded.
  • the source/contact junction region 92A to which the "first source wiring 125" is bonded is the region of the outer contact region 92 to which the "first source wiring 125" is bonded.
  • the source/contact junction region 92A to which the "first source wiring 125" is bonded includes the source/contact junction region 92A having the shortest distance to the first position P1 among all the “source/contact junction regions” in the semiconductor device 1.
  • the distance M1 between the source/contact junction region 92A closest to the first position P1 among the source/contact junction regions 92A to which the "first source wiring 125" is bonded and the first position P1 is about 68 ⁇ m, which is less than 70 ⁇ m.
  • the maximum distance between each position on the lower surface of the gate connection conductive films 50a, 39b and the "source/contact junction region" closest to it is less than 70 ⁇ m.
  • FIG. 11 is a cross-sectional view taken along line XI-XI shown in FIG. 6.
  • the first gate wiring 102A has a straight portion (hereinafter referred to as the "first peripheral gate wiring 102A") that extends along the first peripheral region 14A in the active region 12.
  • the "first peripheral gate wiring 102A” is an example of the “peripheral gate wiring” of the present disclosure.
  • a gate connection electrode film 39 is formed on the end of the trench gate structure 20 on the "first peripheral gate wiring 102A" side (first peripheral region 14A side), covering the gate buried electrode 23 and the main surface insulating film 16 and joining to the "first peripheral gate wiring 102A".
  • the gate connection electrode film 39 includes a gate connection conductive film 39b (see FIG. 9) formed on the main surface insulating film 16.
  • the source wiring 125 includes a straight portion (hereinafter referred to as the "second source wiring 125") that extends along the "first peripheral gate wiring 102A" (third side surface 5C) in the region opposite the active region 12 with respect to the "first peripheral gate wiring 102A.”
  • the "second source wiring 125" is an example of the “second source wiring” in this disclosure.
  • the second position P2 is the central position of the length in the first direction X of the gate connection electrode film 39 joined to the "first peripheral gate wiring 102A".
  • the region of the outer contact region 92 to which the "second source wiring 125" is connected, to which the "second source wiring 125" is bonded is referred to as the source/contact junction region 92B to which the "second source wiring 125" is bonded.
  • the source/contact junction region 92B to which the "second source wiring 125" is bonded is the region of the outer contact region 92 to which the "second source wiring 125" is bonded.
  • the source/contact junction region 92B to which the "second source wiring 125" is bonded includes the source/contact junction region 92B having the shortest distance to the second position P2 among all the “source/contact junction regions” in the semiconductor device 1.
  • the distance M2 between the source/contact junction region 92B closest to the second position P2 among the source/contact junction regions 92B to which the "second source wiring 125" is bonded and the second position P2 is approximately 29 ⁇ m.
  • the second peripheral gate wiring 102B has a straight line portion (hereinafter referred to as the "second peripheral gate wiring 102B") that extends along the second peripheral region 14B in the active region 12.
  • the "second peripheral gate wiring 102B" is an example of the "peripheral gate wiring" of the present disclosure.
  • a gate connection electrode film 39 is formed on the end of the trench gate structure 20 on the "second peripheral gate wiring 102B" side (second peripheral region 14B side), covering the gate buried electrode 23 and the main surface insulating film 16 and being joined to the "second peripheral gate wiring 102B".
  • the gate connection electrode film 39 joined to the "second peripheral gate wiring 102B" includes a gate connection conductive film 39b formed on the main surface insulating film 16, similar to the gate connection electrode film 39 joined to the "first peripheral gate wiring 102A".
  • the source wiring 125 includes a straight portion (hereinafter referred to as the "third source wiring 125") that extends along the "second peripheral gate wiring 102B" (fourth side surface 5D) in the region opposite the active region 12 relative to the "second peripheral gate wiring 102B.”
  • the "third source wiring 125" is an example of the "second source wiring” in this disclosure.
  • the fourth position is the center position of the length in the first direction X of the gate connection electrode film 39 joined to the "second peripheral gate wiring 102B".
  • the region of the outer contact region 92 to which the "third source wiring 125" is bonded is referred to as the "source/contact junction region” to which the "third source wiring 125" is bonded.
  • the "source/contact junction region” to which the "third source wiring 125" is bonded is the region of the outer contact region 92 to which the "third source wiring 125" is bonded.
  • the "source/contact junction region" to which the "third source wiring 125" is bonded includes the “source/contact junction region” that has the shortest distance to the fourth position among all the “source/contact junction regions” in the semiconductor device 1.
  • the distance between the fourth position and the "source/contact junction region" closest to the fourth position among the “source/contact junction regions” to which the "third source wiring 125" is bonded is approximately 29 ⁇ m.
  • FIG. 30 is an enlarged plan view showing a portion of region E3 in FIG. 13.
  • FIG. 31 is a cross-sectional view taken along line XXXI-XXXI in FIG. 30.
  • the third gate wiring 102C includes a line portion 110 that extends along the central region between the peripheral regions 14A and 14B on both sides of the active region 12.
  • the line portion 110 is an example of the "central gate wiring" of the present disclosure.
  • a gate connection electrode film 39 is formed in the portion of the trench gate structure 20 facing the line portion 110, covering the gate buried electrode 23 and the main surface insulating film 16 and being joined to the line portion 110.
  • the gate connection electrode film 39 includes a gate connection conductive film 39b formed on the main surface insulating film 16.
  • the source electrode 120 includes a first source pad 121 and a second source pad 122 arranged on both sides of the line portion 110 at a distance from the line portion 110 in the active region 12.
  • the first source pad 121 and the second source pad 122 are an example of a "source pad portion" in this disclosure.
  • the first source pad 121 and the second source pad 122 are electrically connected to the first trench source structure 25, the source region 18, and the first contact region 38 via the source opening 126.
  • the third position P3 is the center position of the length in the first direction X of the gate connection electrode film 39 joined to the line portion 110.
  • the region of the first contact region 38 to which the first source pad 121 is bonded is referred to as the source/contact junction region 38A to which the first source pad 121 is bonded.
  • the source/contact junction region 38A to which the first source pad 121 is bonded is the region of the first contact region 38 to which the first source pad 121 is bonded.
  • the region of the first contact region 38 to which the second source pad 122 is bonded is referred to as the source/contact junction region 38A to which the second source pad 122 is bonded.
  • the source/contact junction region 38A to which the second source pad 122 is bonded is the region of the first contact region 38 to which the second source pad 122 is bonded.
  • the source/contact junction region 38A to which at least one of the first source pad 121 and the second source pad 122 (in this embodiment, both the first source pad 121 and the second source pad 122) is bonded includes the source/contact junction region 38A that has the shortest distance to the third position P3 among all the "source/contact junction regions" in the semiconductor device 1.
  • FIG. 31 illustrates the source/contact junction region 38A to which the first source pad 121 is bonded, which has the shortest distance to the third position P3.
  • the source/contact junction region 38A to which the second source pad 122 is bonded, which has the shortest distance to the third position P3, is not illustrated.
  • the distance M3 between the source/contact junction region 38A closest to the third position P3 among the source/contact junction regions 38A to which the first source pad 121 is bonded and the third position P3 is approximately 32 ⁇ m. Also, the distance between the source/contact junction region 38A closest to the third position P3 among the source/contact junction regions 38A to which the second source pad 122 is bonded and the third position P3 is approximately 32 ⁇ m.
  • the layout of the gate connection conductive films 50a, 38b and the source/contact junction regions 38A, 92A, 92B is designed so that the maximum distance between each position on the underside of the gate connection conductive films 50a, 38b and the nearest source/contact junction regions 38A, 92A, 92B is 90 ⁇ m or less. This makes it possible to suppress damage to the main surface insulating film 16 caused by the voltage V DS /dt generated during switching of the MISFET, and therefore to suppress an increase in leakage current.
  • the semiconductor device 1 includes a chip 2, a gate resistor 40, a gate pad 101, and a gate wiring 102.
  • the chip 2 has a first main surface 3.
  • the gate resistor 40 includes a trench resistor structure 41 formed on the first main surface 3.
  • the gate pad 101 has a lower resistance value than the trench resistor structure 41, and is disposed on the first main surface 3 so as to be electrically connected to the trench resistor structure 41.
  • the gate wiring 102 has a lower resistance value than the trench resistor structure 41, and is disposed on the first main surface 3 so as to be electrically connected to the gate pad 101 via the trench resistor structure 41.
  • the trench resistance structure 41 is incorporated in the chip 2 in the region between the gate pad 101 and the gate wiring 102, so that the area occupied by the gate resistance 40 on the first main surface 3 can be limited.
  • the resistance value of the gate resistance 40 is adjusted by adjusting the depth and length of the trench resistance structure 41. Therefore, an increase in the area occupied by the gate resistance 40 on the first main surface 3 can be suppressed. Therefore, in a configuration including the gate resistance 40, a semiconductor device 1 can be provided that has a novel layout that contributes to miniaturization.
  • the gate pad 101 has a portion located directly above the trench resistance structure 41.
  • the gate resistor 40 is disposed in a region directly below the gate pad 101, so that an increase in the area occupied by the gate resistor 40 with respect to the first main surface 3 can be suppressed.
  • the gate wiring 102 has a portion located directly above the trench resistance structure 41. With this structure, it is preferable that the gate resistor 40 is disposed in a region directly below the gate wiring 102, so that an increase in the area occupied by the gate resistor 40 with respect to the first main surface 3 can be suppressed.
  • the trench resistance structure 41 does not contribute to channel control. With this structure, malfunctions caused by the trench resistance structure 41 can be appropriately suppressed. It is preferable that the gate resistance 40 includes a resistive film 50 that covers the trench resistance structure 41. With this structure, the resistance value of the gate resistance 40 can be adjusted by utilizing both the trench resistance structure 41 and the resistive film 50.
  • the gate pad 101 is electrically connected to the trench resistance structure 41 via the resistive film 50.
  • the gate pad 101 can be appropriately electrically connected to the trench resistance structure 41 by the resistive film 50. It is preferable that the gate pad 101 has a portion that faces the trench resistance structure 41 with the resistive film 50 in between.
  • the gate wiring 102 is preferably electrically connected to the trench resistance structure 41 via the resistive film 50.
  • the resistive film 50 can properly electrically connect the gate wiring 102 to the trench resistance structure 41.
  • the gate wiring 102 has a portion that faces the trench resistance structure 41 across the resistive film 50.
  • the resistive film 50 may have a portion covering the first main surface 3 and a portion covering the trench resistance structure 41.
  • the resistance value of the resistive film 50 can be adjusted by utilizing the region on the first main surface 3 and the region on the trench resistance structure 41.
  • the influence caused by the alignment error of the gate pad 101 with respect to the resistive film 50 and the influence caused by the alignment error of the gate wiring 102 can be reduced.
  • the gate pad 101 may have a portion facing the first main surface 3 across the resistive film 50.
  • the gate wiring 102 may have a portion facing the first main surface 3 across the resistive film 50.
  • the semiconductor device 1 may include an interlayer insulating film 99 that covers the resistive film 50.
  • the gate pad 101 penetrates the interlayer insulating film 99 and is connected to the resistive film 50.
  • the gate wiring 102 penetrates the interlayer insulating film 99 and is connected to the resistive film 50.
  • a plurality of trench resistance structures 41 are preferably formed on the first main surface 3. With this structure, the resistance value of the gate resistor 40 can be adjusted using the plurality of trench resistance structures 41.
  • the plurality of trench resistance structures 41 preferably include a first trench resistance structure 42 and a second trench resistance structure 43 that is deeper than the first trench resistance structure 42.
  • the resistance value of the gate resistor 40 can be adjusted by utilizing the first trench resistor structure 42 and the second trench 47 structure, which have different depths.
  • the second trench resistor structure 43 can increase the resistance of the gate resistor 40 in the thickness direction of the chip 2. Therefore, for example, when a resistive film 50 is provided, the film thickness of the resistive film 50 can also be reduced.
  • the semiconductor device 1 preferably includes an active region 12, a peripheral region 13, and a termination region 15.
  • the active region 12 is provided in an inner portion of the first main surface 3.
  • the peripheral region 13 is provided in a peripheral portion of the first main surface 3.
  • the termination region 15 is provided between the active region 12 and the peripheral region 13.
  • the trench resistor structure 41 is preferably formed in the termination region 15. With this layout, it is possible to appropriately suppress the reduction in the area of the active region 12 that accompanies the introduction of the gate resistor 40.
  • the gate pad 101 is electrically connected to the trench resistance structure 41 in the termination region 15. It is also preferable that the gate wiring 102 is electrically connected to the gate pad 101 via the trench resistance structure 41 in the termination region 15.
  • the semiconductor device 1 preferably includes a trench gate structure 20 formed on the first main surface 3 in the active region 12.
  • the gate wiring 102 is preferably electrically connected to the trench gate structure 20 in the active region 12.
  • a gate resistor 40 trench resistor structure 41
  • the semiconductor device 1 may include a first trench source structure 25 formed on the first main surface 3 adjacent to the trench gate structure 20 in the active region 12 and to which a source potential VS is applied.
  • the first trench source structure 25 may be formed deeper than the trench gate structure 20.
  • the multiple trench resistance structures 41 preferably include a first trench resistance structure 42 formed relatively shallow in correspondence with the trench gate structure 20, and a second trench resistance structure 43 formed relatively deep in correspondence with the first trench source structure 25.
  • the first trench resistor structure 42 has a depth approximately equal to that of the trench gate structure 20.
  • the second trench resistor structure 43 has a depth approximately equal to that of the first trench source structure 25.
  • the semiconductor device 1 preferably further includes a dummy trench structure 60 formed on the first main surface 3 so as to be adjacent to the trench resistance structure 41 in the termination region 15.
  • the dummy trench structure 60 preferably does not contribute to channel control. With this structure, malfunctions caused by the trench resistance structure 41 can be appropriately suppressed.
  • a source potential VS is applied to the dummy trench structure 60.
  • the electric field in the region near the trench resistance structure 41 can be alleviated by the dummy trench structure 60.
  • a plurality of dummy trench structures 60 are formed on the first main surface 3. With this structure, the electric field in the region near the trench resistance structure 41 in the termination region 15 can be alleviated by the plurality of dummy trench structures 60.
  • the multiple dummy trench structures 60 preferably include a first dummy trench structure 61 and a second dummy trench structure 62 that is deeper than the first dummy trench structure 61. With this structure, the electric field near the trench resistor structure 41 can be alleviated by the first dummy trench structure 61 and the second dummy trench structure 62.
  • This structure is particularly effective when a first trench source structure 25 that is deeper than the trench gate structure 20 is formed in the active region 12. This structure is also particularly effective when a second trench resistor structure 43 that is deeper than the first trench resistor structure 42 is formed in the termination region 15.
  • the semiconductor device 1 may include an active surface 8 formed on the inner side of the first main surface 3, an outer peripheral surface 9 formed on the periphery of the first main surface 3 so as to be recessed from the active surface 8 in the thickness direction of the chip 2, and an active plateau 11 defined on the first main surface 3 by first to fourth connection surfaces 10A to 10D connecting the active surface 8 and the outer peripheral surface 9.
  • the active region 12 is provided on the active surface 8
  • the outer peripheral region 13 is provided on the outer peripheral surface 9, and the termination region 15 is provided on the active surface 8.
  • the semiconductor device 1 preferably includes an n-type first semiconductor region 6 formed in a surface layer of the first main surface 3.
  • the trench resistor structure 41 is formed in the first main surface 3 so as to be located within the first semiconductor region 6.
  • the semiconductor device 1 preferably includes a p-type fourth well region 75 (fifth well region 76) formed in a region along the trench resistor structure 41 in the first semiconductor region 6 so as to form a pn junction with the first semiconductor region 6.
  • the breakdown voltage e.g., breakdown voltage
  • the depletion layer that spreads from the fourth well region 75 (fifth well region 76).
  • the semiconductor device 1 may include a gate subpad 103 arranged on the first main surface 3 so as to have a lower resistance value than the trench resistor structure 41 and to be electrically connected to the gate pad 101 via the trench resistor structure 41.
  • the resistance between the gate pad 101 and the gate wiring 102 can be indirectly measured by measuring the resistance between the gate pad 101 and the gate subpad 103. It is preferable that the gate subpad 103 is formed narrower than the gate pad 101 and wider than the gate wiring 102. The gate subpad 103 may be connected to the gate wiring 102.
  • the semiconductor device 1 may include a p-type outer well region 91 formed in the surface layer of the first main surface 3 in the peripheral region 13. With this structure, the outer well region 91 can reduce the electric field in the peripheral region 13.
  • the semiconductor device 1 may include at least one p-type field region 93 formed in the surface layer of the first main surface 3 in the peripheral region 13. With this structure, the field region 93 can reduce the electric field in the peripheral region 13.
  • the semiconductor device 1 includes a chip 2, a first trench resistance structure 42 (first groove structure), a first dummy trench structure 61 (second groove structure), a second trench resistance structure 43 (third groove structure), a second dummy trench structure 62 (fourth groove structure), a first mesa portion 71 and a second mesa portion 72.
  • the chip 2 has a first main surface 3.
  • the first trench resistance structure 42 is formed on the first main surface 3.
  • the first dummy trench structure 61 is formed on the first main surface 3 so as to be adjacent to the first trench resistance structure 42 in the first direction X.
  • the second trench resistance structure 43 is formed on the first main surface 3 so as to be adjacent to the first trench resistance structure 42 in a second direction Y perpendicular to the first direction X.
  • the second dummy trench structure 62 is formed on the first main surface 3 so as to be adjacent to the second trench resistance structure 43 in the first direction X.
  • the first mesa portion 71 is defined in the region between the first trench resistance structure 42 and the first dummy trench structure 61.
  • the second mesa portion 72 is defined in the region between the second trench resistance structure 43 and the second dummy trench structure 62, shifted in the first direction X with respect to the first mesa portion 71.
  • This structure makes it possible to prevent the electric field generated in the second mesa portion 72 from interfering with the electric field generated in the first mesa portion 71. This makes it possible to prevent electric field concentration in the first mesa portion 71 and electric field concentration in the second mesa portion 72. This makes it possible to provide a semiconductor device 1 having a novel layout that can improve the withstand voltage (e.g., breakdown voltage).
  • the withstand voltage e.g., breakdown voltage
  • Such a structure is particularly effective in the case where an electric field caused by a potential difference between the first dummy trench structure 61 and the first trench resistance structure 42 occurs in the first mesa portion 71, and an electric field caused by a potential difference between the second dummy trench structure 62 and the second trench resistance structure 43 occurs in the second mesa portion 72. Therefore, a potential different from that applied to the first dummy trench structure 61 and that applied to the first trench resistance structure 42 may be applied to the second dummy trench structure 62 and that applied to the second trench resistance structure 43.
  • a first potential may be applied to the first trench resistance structure 42 and the second trench resistance structure 43, and a second potential different from the first potential may be applied to the first dummy trench structure 61 and the second dummy trench structure 62.
  • the first potential may be a gate potential VG
  • the second potential may be a source potential VS.
  • the second dummy trench structure 62 is preferably formed on the first main surface 3 so as to be adjacent to the first dummy trench structure 61 in the second direction Y.
  • the second trench resistance structure 43 may be formed deeper than the first trench resistance structure 42.
  • the second dummy trench structure 62 is preferably formed deeper than the first dummy trench structure 61.
  • This structure can alleviate the bias in the electric field caused by the difference in depth between the first trench resistance structure 42 and the second trench resistance structure 43.
  • the first dummy trench structure 61 is formed to a depth approximately equal to that of the first trench resistance structure 42.
  • the second dummy trench structure 62 is formed to a depth approximately equal to that of the second trench resistance structure 43.
  • the semiconductor device 1 includes a main mesa portion 70 defined between the first trench resistor structure 42 and the second trench resistor structure 43.
  • the first mesa portion 71 and the second mesa portion 72 are connected to the main mesa portion 70.
  • the width in the first direction X of the first mesa portion 71 is 0.5 to 2 times the width in the second direction Y of the main mesa portion 70.
  • the width in the first direction X of the second mesa portion 72 is 0.5 to 2 times the width in the second direction Y of the main mesa portion 70.
  • the first trench resistor structure 42 preferably extends in a strip shape in the first direction X.
  • the second trench resistor structure 43 preferably extends in a strip shape in the first direction X.
  • the first dummy trench structure 61 preferably extends in a strip shape in the first direction X.
  • the second dummy trench structure 62 preferably extends in a strip shape in the first direction X.
  • the semiconductor device 1 may include an active surface 8 formed on the inner portion of the first main surface 3, an outer peripheral surface 9 formed on the periphery of the first main surface 3 so as to be recessed from the active surface 8 in the thickness direction of the chip 2, and an active plateau 11 defined on the first main surface 3 by first to fourth connection surfaces 10A to 10D connecting the active surface 8 and the outer peripheral surface 9.
  • the first trench resistor structure 42, the second trench resistor structure 43, the first dummy trench structure 61, and the second dummy trench structure 62 are preferably formed on the active surface 8.
  • the first trench resistor structure 42 and the second trench resistor structure 43 are preferably formed on the active surface 8 at a distance from the first to fourth connection surfaces 10A to 10D.
  • the first dummy trench structure 61 may be formed on the active surface 8 so as to be exposed from the third connection surface 10C (fourth connection surface 10D).
  • the second dummy trench structure 62 may be formed on the active surface 8 so as to be exposed from the third connection surface 10C (fourth connection surface 10D).
  • the semiconductor device 1 may include a sidewall structure disposed on the outer peripheral surface 9 so as to cover at least one of the first to fourth connection surfaces 10A to 10D.
  • the sidewall structure preferably comprises a sidewall wiring 95 electrically connected to the first dummy trench structure 61 and the second dummy trench structure 62.
  • the sidewall wiring 95 can apply a potential different from the potentials applied to the first trench resistance structure 42 and the second trench resistance structure 43 to the first dummy trench structure 61 and the second dummy trench structure 62 from the outer peripheral surface 9 side.
  • the semiconductor device 1 may include an n-type first semiconductor region 6 formed in a surface layer portion of the first main surface 3.
  • the semiconductor device 1 may include a p-type body region 17 formed in a surface layer portion of the first semiconductor region 6.
  • first trench resistance structure 42 and the second trench resistance structure 43 do not contribute to channel control. According to this structure, malfunctions caused by the first trench resistance structure 42 and the second trench resistance structure 43 can be appropriately suppressed. It is preferable that the first dummy trench structure 61 and the second dummy trench structure 62 do not contribute to channel control. According to this structure, it is possible to appropriately suppress malfunctions caused by the first dummy trench structure 61 and the second dummy trench structure 62.
  • the semiconductor device 1 may include a p-type second contact region 79 formed in a region along the second trench resistance structure 43 in the first semiconductor region 6.
  • the second contact region 79 is preferably formed in a region along the second trench resistance structure 43 and spaced apart from the second mesa portion 72.
  • the second contact region 79 is formed offset in the first direction X with respect to the first mesa portion 71. In this case, it is preferable that the second contact region 79 does not face the first mesa portion 71 in the second direction Y. With this structure, the electric field associated with the first mesa portion 71 and the electric field associated with the second mesa portion 72 can be appropriately alleviated.
  • the semiconductor device 1 may include a p-type third contact region 80 formed in a region along the second dummy trench structure 62 in the first semiconductor region 6.
  • the third contact region 80 is preferably formed in a region along the second dummy trench structure 62 with a gap therebetween from the second mesa portion 72. It is particularly preferable that the third contact region 80 is formed shifted in the first direction X with respect to the first mesa portion 71. In this case, it is preferable that the third contact region 80 does not face the first mesa portion 71 in the second direction Y.
  • the chip 2 preferably includes a single crystal of a wide band gap semiconductor.
  • a single crystal of a wide band gap semiconductor is effective in improving electrical characteristics.
  • the single crystal of a wide band gap semiconductor has a relatively high hardness, which suppresses deformation of the chip 2, while allowing the chip 2 to be thinned and the surface area of the chip 2 to be increased.
  • the chip 2 may have a first main surface 3 having an area of 1 mm square or more in a plan view.
  • the chip 2 may have a thickness of 200 ⁇ m or less. It is preferable that the chip 2 has a thickness of 100 ⁇ m or less in a cross-sectional view.
  • each of the above-described embodiments can be implemented in other forms.
  • a form in which the "first conductivity type” is “n-type” and the “second conductivity type” is “p-type” has been shown.
  • each of the above-described embodiments may also adopt a form in which the "first conductivity type” is “p-type” and the “second conductivity type” is "n-type”.
  • a specific configuration in this case can be obtained by replacing "n-type” with "p-type” and at the same time replacing "p-type” with "n-type” in the above description and the accompanying drawings.
  • an n-type second semiconductor region 7 is shown.
  • a p-type second semiconductor region 7 may be adopted.
  • an IGBT Insulated Gate Bipolar Transistor
  • the "source” of the MISFET is replaced with the "emitter” of the IGBT
  • the "drain” of the MISFET is replaced with the "collector” of the IGBT.
  • the p-type second semiconductor region 7 may be an impurity region containing p-type impurities introduced into the surface layer of the second main surface 4 of the chip 2 by ion implantation.
  • a chip (2) having a main surface (3) and made of a first conductivity type semiconductor; a first region (17, 35, 36, 37, 75, 77, 78, 91) of a second conductivity type selectively formed in a surface layer portion on the main surface (3) side of the chip (2); a trench gate structure (20) formed on said main surface (3); a trench source structure (25, 30) formed in said main surface (3); An insulating film (16) selectively formed on the main surface (3); an interlayer insulating film (99) disposed on the main surface (3) so as to cover the insulating film (16); a gate electrode (100) disposed on the interlayer insulating film (99) and applying a gate potential to the trench gate structure (20); a source electrode (120) disposed on the interlayer insulating film (99) and applying a source potential to the trench source structure (25, 30); a gate connection conductive film (50a, 39b) formed on the insulating film (16) and electrically connected to the gate electrode (100); a contact
  • the gate resistor (40) is disposed in the termination region (15);
  • the source electrode (120) includes a first source wiring (125) extending along the trench resistor structure (41) in a region opposite the active region (12) with respect to the gate resistor (40);
  • the semiconductor device according to A5 wherein, among the respective positions on the underside of the gate connection conductive film (50) included in the gate resistor (40), a position at which the minimum value of the distance from each of all of the source/contact junction regions (38A, 92A, 92B) to the position is the largest is defined as a first position (P1), and the source/contact junction region (92A) to which the first source wiring (125) is joined includes the source/contact junction region (92A) at which the distance to the first position (P1) is the smallest among all of the source/contact junction regions (38A, 92A, 92B).
  • the contact region (38, 92) includes a first outer contact region (92) to which the first source wiring (125) is electrically connected,
  • the semiconductor device according to A6, wherein the source/contact junction region (92A) to which the first source wiring (125) is joined is a region of the first outer contact region (92) to which the first source wiring (125) is joined.
  • the trench gate structure (20) includes a gate trench (21) formed in the main surface (3), a gate insulating film (22) formed on a wall surface of the gate trench (21) and connected to the insulating film (16), and a gate buried electrode (23) buried in the gate trench (21) with the gate insulating film (22) sandwiched therebetween, A plurality of gate connection electrode films (39) are formed on the gate buried electrode (23) to selectively cover the gate buried electrode (23) and the insulating film (16), The semiconductor device according to any one of A1 to A7, wherein the gate connection electrode film (39) includes the gate connection conductive film (39b).
  • the gate electrode (100) includes peripheral gate wiring (102A, 102B) extending along at least one of the peripheral regions (14) on both sides in the active region (12), the gate connection electrode film (39) is formed at an end of the trench gate structure (20) on the peripheral gate wiring (102A, 102B) side, the gate connection electrode film (39) covering the gate buried electrode (23) and the insulating film (16) and being joined to the peripheral gate wiring (102A, 102B);
  • the source electrode (120) includes a second source wiring (125) extending along the peripheral gate wiring (102A, 102B) in a region opposite to the active region (12) with respect to the peripheral gate wiring (102A, 102B);
  • the semiconductor device according to A9 wherein, among each position on the underside of the gate connection conductive film (39b) included in the gate connection electrode film (39) joined to the peripheral gate wiring (102A, 102B), a position at which the minimum value of the distance from each of all of the source/contact junction regions (38A, 92A, 92
  • the contact region (38, 92) includes a second outer contact region (92) to which the second source wiring (125) is electrically connected,
  • the semiconductor device according to A10, wherein the source/contact junction region (92B) to which the second source wiring (125) is joined is a region of the second outer contact region (92) to which the second source wiring (125) is joined.
  • the gate electrode (100) is formed in a central region between the peripheral regions (14) on both sides of the active region (12) and includes a central gate wiring (102C) extending along the peripheral regions (14); the gate connection electrode film (39) is formed in a portion of the trench gate structure (20) facing the central gate wiring (102C), the gate connection electrode film (39) covering the gate buried electrode (23) and the insulating film (16) and being joined to the central gate wiring (102C);
  • the source electrode (120) includes two source pad portions (121, 122) disposed on both sides of the central gate wiring (102C) at a distance from the central gate wiring (102C) in the active region (12);
  • the semiconductor device according to A9 wherein, among each position on the underside of the gate connection conductive film (39b) included in the gate connection electrode film (39) joined to the central gate wiring (102C), a position at which the minimum value of the distance from each of all of the source/contact junction regions (38A, 92A, 92B) to the position is the largest is defined
  • the contact region (38, 92) includes a first contact region (38) formed in a region along the trench source structure (25, 30) in the active region (12);
  • the semiconductor device according to A12, wherein the source/contact junction region (38A) to which the source pad portion (121, 122) is joined is a region of the first contact region (38) to which the source pad portion (121, 122) is joined.
  • the semiconductor device further includes a first surface portion (8) formed on the inner side of the main surface (3), a second surface portion (9) formed on the periphery of the main surface (3) so as to be recessed from the first surface portion (8) in the thickness direction of the chip (2), and an active plateau (11) defined on the main surface (3) by a connecting surface portion (10A-10D) connecting the first surface portion (8) and the second surface portion (9),
  • the active region (12) is provided on the first surface portion (8)
  • the outer circumferential region (13) is provided on the second surface portion (9)
  • the semiconductor device according to any one of A5 to A7, wherein the termination region (15) is provided on the first surface portion (8).
  • the semiconductor device further includes a first surface portion (8) formed on the inner side of the main surface (3), a second surface portion (9) formed on the periphery of the main surface (3) so as to be recessed from the first surface portion (8) in the thickness direction of the chip (2), and an active plateau (11) defined on the main surface (3) by a connecting surface portion (10A-10D) connecting the first surface portion (8) and the second surface portion (9),
  • the active region (12) is provided on the first surface portion (8)
  • the outer circumferential region (13) is provided on the second surface portion (9)
  • the semiconductor device according to any one of A9 to A13, wherein the peripheral regions (14) on both sides are provided on the first surface portion (8).
  • A16 The semiconductor device according to any one of A4 to A7, further including a gate subpad (103) arranged on the main surface (3) so as to have a resistance value lower than the trench resistor structure (41) and to be electrically connected to the gate pad (101) via the trench resistor structure (41).

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Abstract

A semiconductor device comprising: a chip having a main surface and made of a semiconductor of a first conduction type; a first region of a second conduction type selectivity formed in a main-surface-side surface-layer portion of the chip; an insulating film selectively formed on the main surface; an interlayer dielectric film disposed over the main surface so as to cover the insulating film; a gate electrode and a source electrode which have been disposed over the interlayer dielectric film; a gate-connection electroconductive film formed on the insulating film and electrically connected to the gate electrode; and a contact region of the second conduction type which has been selectively formed in a surface-layer portion of the first region and to which the source electrode is electrically connected. When an area of the contact region to which the source electrode has been bonded is referred to as a source/contact junction region, then the distance between the position of each of portions of the lower surface of the gate-connection electroconductive film and the source/contact junction region located nearest thereto has a maximum value of 90 μm or less.

Description

半導体装置Semiconductor Device
　本発明は、半導体装置に関する。 The present invention relates to a semiconductor device.
　特許文献１は、半導体層と、半導体層の表面に選択的に形成されたゲート絶縁膜と、ゲート絶縁膜上に形成された内蔵抵抗と、半導体層の表面に内蔵抵抗を覆うように形成された層間膜と、層間膜上に形成され、内蔵抵抗に電気的に接続されたゲートメタルと、層間絶縁膜上に形成され、内蔵抵抗を介してゲートメタルに電気的に接続されたゲートフィンガーとを含む半導体装置を開示している。 Patent document 1 discloses a semiconductor device including a semiconductor layer, a gate insulating film selectively formed on the surface of the semiconductor layer, a built-in resistor formed on the gate insulating film, an interlayer film formed on the surface of the semiconductor layer so as to cover the built-in resistor, a gate metal formed on the interlayer film and electrically connected to the built-in resistor, and a gate finger formed on the interlayer insulating film and electrically connected to the gate metal via the built-in resistor.
国際公開第２０１５／０８０１６２号International Publication No. 2015/080162
　特許文献１に記載の半導体装置では、スイッチング時に発生する比較的大きなソース／ドレイン間電圧ＶＤＳ／ｄｔに起因して、半導体層と内蔵抵抗との間に介在するゲート絶縁膜が損傷し、リーク電流が増加するおそれがある。 In the semiconductor device described in Patent Document 1, a relatively large source-drain voltage V DS /dt generated during switching may damage the gate insulating film between the semiconductor layer and the built-in resistor, resulting in an increase in leakage current.
　本開示の一実施形態の目的は、リーク電流を抑制できる半導体装置を提供することである。 The objective of one embodiment of the present disclosure is to provide a semiconductor device that can suppress leakage current.
　本開示の一実施形態は、主面を有し、第１導電型の半導体からなるチップと、前記チップの前記主面側の表層部に選択的に形成された第２導電型の第１領域と、前記主面に形成されたトレンチゲート構造と、前記主面に形成されたトレンチソース構造と、前記チップの前記主面上に選択的に形成された絶縁膜と、前記絶縁膜上に選択的に配置された層間絶縁膜と、前記層間絶縁膜上に配置され、前記トレンチゲート構造にゲート電位を付与するゲート電極と、前記層間絶縁膜上に配置され、前記トレンチソース構造にソース電位を付与するソース電極と、前記絶縁膜上に形成され、前記ゲート電極に電気的に接続されたゲート接続導電膜と、前記第１領域の表層部に選択的に形成され、前記ソース電極が電気的に接続される第２導電型のコンタクト領域とを含み、前記コンタクト領域のうち前記ソース電極が接合されている領域をソース／コンタクト接合領域とすると、前記ゲート接続導電膜の下面の各位置とそれに最も近い前記ソース／コンタクト接合領域の距離の最大値が９０μｍ以下である、半導体装置を提供する。 An embodiment of the present disclosure provides a semiconductor device including a chip having a main surface and made of a semiconductor of a first conductivity type, a first region of a second conductivity type selectively formed on a surface layer portion of the main surface side of the chip, a trench gate structure formed on the main surface, a trench source structure formed on the main surface, an insulating film selectively formed on the main surface of the chip, an interlayer insulating film selectively arranged on the insulating film, a gate electrode arranged on the interlayer insulating film and applying a gate potential to the trench gate structure, a source electrode arranged on the interlayer insulating film and applying a source potential to the trench source structure, a gate connection conductive film formed on the insulating film and electrically connected to the gate electrode, and a contact region of a second conductivity type selectively formed on a surface layer portion of the first region and electrically connected to the source electrode, where the region of the contact region to which the source electrode is joined is defined as a source/contact junction region, and the maximum distance between each position on the underside of the gate connection conductive film and the source/contact junction region closest to it is 90 μm or less.
　この構成では、リーク電流を抑制できる。 This configuration helps to suppress leakage current.
　上述のまたはさらに他の目的、特徴および効果は、添付図面の参照によって説明される実施形態により明らかにされる。 The above and other objects, features and advantages will become apparent from the embodiments described with reference to the accompanying drawings.
図１は、一実施形態に係る半導体装置を示す平面図である。FIG. 1 is a plan view showing a semiconductor device according to an embodiment. 図２は、図１に示すII-II線に沿う断面図である。FIG. 2 is a cross-sectional view taken along the line II-II shown in FIG. 図３は、ゲート電極およびソース電極のレイアウトを示す平面図である。FIG. 3 is a plan view showing the layout of the gate electrodes and source electrodes. 図４は、第１主面のレイアウトを示す平面図である。FIG. 4 is a plan view showing the layout of the first main surface. 図５は、活性領域のレイアウトを示す拡大平面図である。FIG. 5 is an enlarged plan view showing the layout of the active regions. 図６は、周縁領域のレイアウトを示す拡大平面図である。FIG. 6 is an enlarged plan view showing the layout of the peripheral region. 図７は、図５に示すVII-VII線に沿う断面図である。FIG. 7 is a cross-sectional view taken along line VII-VII shown in FIG. 図８は、図５に示すVIII-VIII線に沿う断面図である。FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG. 図９は、図６に示すIX-IX線に沿う断面図である。FIG. 9 is a cross-sectional view taken along line IX-IX shown in FIG. 図１０は、図６に示すX-X線に沿う断面図である。FIG. 10 is a cross-sectional view taken along line X-X shown in FIG. 図１１は、図６に示すXI-XI線に沿う断面図である。FIG. 11 is a cross-sectional view taken along the line XI-XI shown in FIG. 図１２は、図６に示すXII-XII線に沿う断面図である。FIG. 12 is a cross-sectional view taken along line XII-XII shown in FIG. 図１３は、終端領域のレイアウトを示す拡大平面図である。FIG. 13 is an enlarged plan view showing the layout of the termination region. 図１４は、ゲート抵抗のレイアウトを示す拡大平面図である。FIG. 14 is an enlarged plan view showing the layout of the gate resistors. 図１５は、ゲート抵抗の内方部を示す拡大平面図である。FIG. 15 is an enlarged plan view showing the inner part of the gate resistor. 図１６は、ゲート抵抗の周縁部を示す拡大平面図である。FIG. 16 is an enlarged plan view showing the periphery of the gate resistor. 図１７は、図１５に示すXVII-XVII線に沿う断面図である。17 is a cross-sectional view taken along line XVII-XVII shown in FIG. 図１８は、図１５に示すXVIII-XVIII線に沿う断面図である。18 is a cross-sectional view taken along line XVIII-XVIII shown in FIG. 15. FIG. 図１９は、図１６に示すXIX-XIX線に沿う断面図である。FIG. 19 is a cross-sectional view taken along line XIX-XIX shown in FIG. 図２０は、図１６に示すXX-XX線に沿う断面図である。FIG. 20 is a cross-sectional view taken along the line XX-XX shown in FIG. 図２１は、図１６に示すXXI-XXI線に沿う断面図である。21 is a cross-sectional view taken along line XXI-XXI shown in FIG. 16. FIG. 図２２は、図１６に示すXXII-XXII線に沿う断面図である。22 is a cross-sectional view taken along line XXII-XXII shown in FIG. 16. FIG. 図２３は、ゲート抵抗の一要部を示す拡大平面図である。FIG. 23 is an enlarged plan view showing a main part of the gate resistor. 図２４は、終端ダミー構造のレイアウトを示す拡大平面図である。FIG. 24 is an enlarged plan view showing the layout of the termination dummy structure. 図２５は、終端ダミー構造のレイアウトを示す更なる拡大平面図である。FIG. 25 is a further enlarged plan view showing the layout of the termination dummy structure. 図２６は、図２５に示すXXVI-XXVI線に沿う断面図である。26 is a cross-sectional view taken along line XXVI-XXVI shown in FIG. 25. FIG. 図２７は、ゲート電極およびゲート抵抗の接続形態を示す電気回路図である。FIG. 27 is an electrical circuit diagram showing a connection form of the gate electrode and the gate resistor. 図２８は、外周領域の構造を示す断面図である。FIG. 28 is a cross-sectional view showing the structure of the outer periphery region. 図２９は、図１３のXXIX-XXIX線に沿う断面図である。FIG. 29 is a cross-sectional view taken along line XXIX-XXIX in FIG. 図３０は、図１３の領域Ｅ３の一部を拡大して示す拡大平面図である。FIG. 30 is an enlarged plan view showing a part of the region E3 in FIG. 図３１は、図３０のXXXI-XXXI線に沿う断面図である。31 is a cross-sectional view taken along line XXXI-XXXI in FIG. 30. FIG.
　以下、添付図面を参照して、実施形態が詳細に説明される。添付図面は、模式図であり、厳密に図示されたものではなく、縮尺等は必ずしも一致しない。また、添付図面の間で対応する構造には同一の参照符号が付され、重複する説明は省略または簡略化される。説明が省略または簡略化された構造については、省略または簡略化される前になされた説明が適用される。 Below, the embodiments will be described in detail with reference to the attached drawings. The attached drawings are schematic diagrams, are not strictly illustrated, and are not necessarily to scale. Corresponding structures in the attached drawings are given the same reference symbols, and duplicated explanations have been omitted or simplified. For structures whose explanations have been omitted or simplified, the explanation given before the omission or simplification applies.
　比較対象（comparison target）が存する説明において「ほぼ（substantially）等しい」の文言が使用される場合、この文言は、比較対象の数値（形態）と等しい数値（形態）を含む他、比較対象の数値（形態）を基準とする±１０％の範囲の数値誤差（形態誤差）も含む。実施形態では「第１」、「第２」、「第３」等の文言が使用されるが、これらは説明順序を明確にするために各構造の名称に付された記号であり、各構造の名称を限定する趣旨で付されていない。 When the phrase "substantially equal" is used in a description in which a comparison target exists, this phrase includes a numerical value (shape) equal to the numerical value (shape) of the comparison target, as well as a numerical error (shape error) within a range of ±10% based on the numerical value (shape) of the comparison target. In the embodiments, the words "first," "second," "third," etc. are used, but these are symbols added to the names of each structure to clarify the order of explanation, and are not added with the intention of limiting the names of each structure.
　図１は、一実施形態に係る半導体装置１を示す平面図である。図２は、図１に示すII-II線に沿う断面図である。図３は、ゲート電極１００およびソース電極１２０のレイアウトを示す平面図である。図４は、第１主面３のレイアウトを示す平面図である。図１～図４を参照して、半導体装置１は、ＭＩＳＦＥＴ（Metal Insulator Semiconductor Field Effect Transistor）を含む半導体スイッチング装置である。 FIG. 1 is a plan view showing a semiconductor device 1 according to one embodiment. FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. 1. FIG. 3 is a plan view showing the layout of a gate electrode 100 and a source electrode 120. FIG. 4 is a plan view showing the layout of a first main surface 3. With reference to FIGS. 1 to 4, the semiconductor device 1 is a semiconductor switching device including a MISFET (Metal Insulator Semiconductor Field Effect Transistor).
　半導体装置１は、この形態（this embodiment）では、ワイドバンドギャップ半導体の単結晶を含み、六面体形状（具体的には直方体形状）に形成されたチップ２を含む。つまり、半導体装置１は、「ワイドバンドギャップ半導体装置」である。チップ２は、「半導体チップ」または「ワイドバンドギャップ半導体チップ」と称されてもよい。ワイドバンドギャップ半導体は、Ｓｉ（シリコン）のバンドギャップを超えるバンドギャップを有する半導体である。ＧａＮ（窒化ガリウム）、ＳｉＣ（炭化シリコン）およびＣ（ダイアモンド）が、ワイドバンドギャップ半導体として例示される。 In this embodiment, the semiconductor device 1 includes a chip 2 that includes a single crystal of a wide bandgap semiconductor and is formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). In other words, the semiconductor device 1 is a "wide bandgap semiconductor device." The chip 2 may also be referred to as a "semiconductor chip" or a "wide bandgap semiconductor chip." A wide bandgap semiconductor is a semiconductor that has a bandgap that exceeds the bandgap of Si (silicon). Examples of wide bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond).
　チップ２は、この形態では、ワイドバンドギャップ半導体の一例として六方晶のＳｉＣ単結晶を含む「ＳｉＣチップ」である。つまり、半導体装置１は、「ＳｉＣ半導体装置」である。半導体装置１は、「ＳｉＣ－ＭＩＳＦＥＴ」と称されてもよい。六方晶のＳｉＣ単結晶は、２Ｈ（Hexagonal）－ＳｉＣ単結晶、４Ｈ－ＳｉＣ単結晶、６Ｈ－ＳｉＣ単結晶等を含む複数種のポリタイプを有している。この形態では、チップ２が４Ｈ－ＳｉＣ単結晶を含む例が示されるが、チップ２は他のポリタイプを含んでいてもよい。 In this embodiment, the chip 2 is a "SiC chip" that includes hexagonal SiC single crystal as an example of a wide band gap semiconductor. In other words, the semiconductor device 1 is a "SiC semiconductor device." The semiconductor device 1 may also be referred to as a "SiC-MISFET." The hexagonal SiC single crystal has multiple polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, and the like. In this embodiment, an example is shown in which the chip 2 includes 4H-SiC single crystal, but the chip 2 may include other polytypes.
　チップ２は、一方側の第１主面３、他方側の第２主面４、ならびに、第１主面３および第２主面４を接続する第１～第４側面５Ａ～５Ｄを有している。第１主面３および第２主面４は、それらの法線方向Ｚから見た平面視（以下、単に「平面視」という。）において四角形状に形成されている。法線方向Ｚは、チップ２の厚さ方向でもある。第１主面３および第２主面４は、ＳｉＣ単結晶のｃ面によって形成されていることが好ましい。 The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed in a plan view from their normal direction Z (hereinafter simply referred to as "plan view"). The normal direction Z is also the thickness direction of the chip 2. The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of a SiC single crystal.
　この場合、第１主面３はＳｉＣ単結晶のシリコン面（（０００１）面）によって形成され、第２主面４はＳｉＣ単結晶のカーボン面（（０００ー１）面）によって形成されていることが好ましい。第１主面３および第２主面４は、ｃ面に対して所定のオフ方向に所定の角度で傾斜したオフ角を有していてもよい。オフ方向は、ＳｉＣ単結晶のａ軸方向（［１１－２０］方向）であることが好ましい。オフ角は、０°を超えて１０°以下であってもよい。オフ角は、５°以下であることが好ましい。 In this case, it is preferable that the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal. The first main surface 3 and the second main surface 4 may have an off angle inclined at a predetermined angle in a predetermined off direction with respect to the c-plane. The off direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The off angle may be greater than 0° and less than or equal to 10°. The off angle is preferably less than or equal to 5°.
　第１側面５Ａおよび第２側面５Ｂは、第１主面３に沿う第１方向Ｘに延び、第１方向Ｘに交差（具体的には直交）する第２方向Ｙに対向している。第３側面５Ｃおよび第４側面５Ｄは、第２方向Ｙに延び、第１方向Ｘに対向している。第１方向ＸがＳｉＣ単結晶のｍ軸方向（［１－１００］方向）であり、第２方向ＹがＳｉＣ単結晶のａ軸方向であってもよい。むろん、第１方向ＸがＳｉＣ単結晶のａ軸方向であり、第２方向ＹがＳｉＣ単結晶のｍ軸方向であってもよい。 The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects (specifically, perpendicular to) the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X. The first direction X may be the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y may be the a-axis direction of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal.
　チップ２は、５μｍ以上２００μｍ以下の厚さを有していてもよい。チップ２の厚さは、１５０μｍ以下、１００μｍ以下、８０μｍ以下、５０μｍ以下または４０μｍ以下であってもよい。第１～第４側面５Ａ～５Ｄは、平面視において０．５ｍｍ以上１０ｍｍ以下の長さを有していてもよい。第１～第４側面５Ａ～５Ｄの長さは、１ｍｍ以上であることが好ましい。 The chip 2 may have a thickness of 5 μm or more and 200 μm or less. The thickness of the chip 2 may be 150 μm or less, 100 μm or less, 80 μm or less, 50 μm or less, or 40 μm or less. The first to fourth sides 5A to 5D may have a length of 0.5 mm or more and 10 mm or less in a plan view. It is preferable that the length of the first to fourth sides 5A to 5D is 1 mm or more.
　第１～第４側面５Ａ～５Ｄの長さは、２ｍｍ以上であることが特に好ましい。つまり、チップ２は、１ｍｍ角以上（好ましくは２ｍｍ角以上）の平面積を有し、断面視において１００μｍ以下（好ましくは５０μｍ以下）の厚さを有していることが好ましい。第１～第４側面５Ａ～５Ｄの長さは、この形態では、４ｍｍ以上６ｍｍ以下の範囲に設定されている。 It is particularly preferable that the length of the first to fourth side surfaces 5A to 5D is 2 mm or more. In other words, it is preferable that the chip 2 has a planar area of 1 mm square or more (preferably 2 mm square or more) and a thickness of 100 μm or less (preferably 50 μm or less) in a cross-sectional view. In this embodiment, the length of the first to fourth side surfaces 5A to 5D is set in the range of 4 mm or more and 6 mm or less.
　半導体装置１は、チップ２内において第１主面３側の領域（表層部）に形成されたｎ型の第１半導体領域６を含む。第１半導体領域６は、第１主面３に沿って延びる層状に形成され、第１主面３および第１～第４側面５Ａ～５Ｄから露出している。第１半導体領域６は、この形態では、エピタキシャル層（具体的にはＳｉＣエピタキシャル層）からなる。第１半導体領域６は、１μｍ以上５０μｍ以下の厚さを有していてもよい。第１半導体領域６の厚さは、３μｍ以上３０μｍ以下であることが好ましい。第１半導体領域６の厚さは、５μｍ以上２５μｍ以下であることが特に好ましい。 The semiconductor device 1 includes an n-type first semiconductor region 6 formed in a region (surface layer) on the first main surface 3 side of the chip 2. The first semiconductor region 6 is formed in a layer extending along the first main surface 3, and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor region 6 is made of an epitaxial layer (specifically, a SiC epitaxial layer). The first semiconductor region 6 may have a thickness of 1 μm or more and 50 μm or less. The thickness of the first semiconductor region 6 is preferably 3 μm or more and 30 μm or less. It is particularly preferable that the thickness of the first semiconductor region 6 is 5 μm or more and 25 μm or less.
　半導体装置１は、チップ２内において第２主面４側の領域（表層部）に形成されたｎ型の第２半導体領域７を含む。第２半導体領域７は、第２主面４に沿って延びる層状に形成され、第２主面４および第１～第４側面５Ａ～５Ｄから露出している。第２半導体領域７は、第１半導体領域６よりも高いｎ型不純物濃度を有し、第１半導体領域６に電気的に接続されている。 The semiconductor device 1 includes an n-type second semiconductor region 7 formed in a region (surface layer) on the second main surface 4 side within the chip 2. The second semiconductor region 7 is formed in a layer extending along the second main surface 4, and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. The second semiconductor region 7 has a higher n-type impurity concentration than the first semiconductor region 6, and is electrically connected to the first semiconductor region 6.
　第２半導体領域７は、この形態では、半導体基板（具体的にはＳｉＣ半導体基板）からなる。つまり、チップ２は、半導体基板およびエピタキシャル層を含む積層構造を有している。第２半導体領域７は、１μｍ以上２００μｍ以下の厚さを有していてもよい。第２半導体領域７の厚さは、１５０μｍ以下、１００μｍ以下、５０μｍ以下または４０μｍ以下であってもよい。第２半導体領域７の厚さは、５μｍ以上であってもよい。第２半導体領域７の厚さは、１０μｍ以上であることが好ましい。第２半導体領域７は、この形態では、第１半導体領域６の厚さを超える厚さを有している。 In this embodiment, the second semiconductor region 7 is made of a semiconductor substrate (specifically, a SiC semiconductor substrate). That is, the chip 2 has a layered structure including a semiconductor substrate and an epitaxial layer. The second semiconductor region 7 may have a thickness of 1 μm or more and 200 μm or less. The thickness of the second semiconductor region 7 may be 150 μm or less, 100 μm or less, 50 μm or less, or 40 μm or less. The thickness of the second semiconductor region 7 may be 5 μm or more. The thickness of the second semiconductor region 7 is preferably 10 μm or more. In this embodiment, the second semiconductor region 7 has a thickness that exceeds the thickness of the first semiconductor region 6.
　半導体装置１は、第１主面３に形成された活性面８（active surface）、外周面９（outer surface）および第１～第４接続面１０Ａ～１０Ｄ（connecting surface）を含む。活性面８、外周面９および第１～第４接続面１０Ａ～１０Ｄは、第１主面３において活性台地１１を区画している。活性面８が「第１面部」と称され、外周面９が「第２面部」と称され、第１～第４接続面１０Ａ～１０Ｄが「接続面部」と称されてもよい。活性面８、外周面９および第１～第４接続面１０Ａ～１０Ｄ（つまり活性台地１１）は、チップ２（第１主面３）の構成要素と見なされてもよい。 The semiconductor device 1 includes an active surface 8, an outer surface 9, and first to fourth connecting surfaces 10A-10D formed on the first main surface 3. The active surface 8, the outer surface 9, and the first to fourth connecting surfaces 10A-10D define an active plateau 11 on the first main surface 3. The active surface 8 may be referred to as the "first surface portion," the outer surface 9 as the "second surface portion," and the first to fourth connecting surfaces 10A-10D as the "connecting surface portion." The active surface 8, the outer surface 9, and the first to fourth connecting surfaces 10A-10D (i.e., the active plateau 11) may be considered as components of the chip 2 (first main surface 3).
　活性面８は、第１主面３の周縁（第１～第４側面５Ａ～５Ｄ）から内方に間隔を空けて形成されている。活性面８は、第１方向Ｘおよび第２方向Ｙに延びる平坦面を有している。活性面８は、この形態では、ｃ面（Ｓｉ面）によって形成されている。活性面８は、この形態では、平面視において第１～第４側面５Ａ～５Ｄに平行な４辺を有する四角形状に形成されている。 The active surface 8 is formed at a distance inward from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The active surface 8 has a flat surface extending in the first direction X and the second direction Y. In this embodiment, the active surface 8 is formed by a c-plane (Si-plane). In this embodiment, the active surface 8 is formed in a quadrangle shape having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view.
　外周面９は、活性面８外に位置し、活性面８からチップ２の厚さ方向（第２主面４側）に窪んでいる。具体的には、外周面９は、第１半導体領域６を露出させるように第１半導体領域６の厚さ未満の深さで窪んでいる。外周面９は、平面視において活性面８に沿って帯状に延び、活性面８を取り囲む環状（具体的には四角環状）に形成されている。 The outer peripheral surface 9 is located outside the active surface 8 and is recessed from the active surface 8 in the thickness direction of the chip 2 (towards the second main surface 4). Specifically, the outer peripheral surface 9 is recessed to a depth less than the thickness of the first semiconductor region 6 so as to expose the first semiconductor region 6. The outer peripheral surface 9 extends in a band shape along the active surface 8 in a plan view and is formed in a ring shape (specifically a square ring shape) surrounding the active surface 8.
　外周面９は、第１方向Ｘおよび第２方向Ｙに延びる平坦面を有し、活性面８に対してほぼ平行に形成されている。外周面９は、この形態では、ｃ面（Ｓｉ面）によって形成されている。外周面９は、第１～第４側面５Ａ～５Ｄに連なっている。外周面９は、外周深さＤＯを有している。外周深さＤＯは、０．５μｍ以上５μｍ以下であってもよい。外周深さＤＯは、２．５μｍ以下であることが好ましい。 The outer peripheral surface 9 has a flat surface extending in the first direction X and the second direction Y, and is formed approximately parallel to the active surface 8. In this embodiment, the outer peripheral surface 9 is formed by a c-plane (Si-plane). The outer peripheral surface 9 is continuous with the first to fourth side surfaces 5A to 5D. The outer peripheral surface 9 has a outer peripheral depth DO. The outer peripheral depth DO may be 0.5 μm or more and 5 μm or less. It is preferable that the outer peripheral depth DO is 2.5 μm or less.
　第１～第４接続面１０Ａ～１０Ｄは、法線方向Ｚに延び、活性面８および外周面９を接続している。第１接続面１０Ａは第１側面５Ａ側に位置し、第２接続面１０Ｂは第２側面５Ｂ側に位置し、第３接続面１０Ｃは第３側面５Ｃ側に位置し、第４接続面１０Ｄは第４側面５Ｄ側に位置している。第１接続面１０Ａおよび第２接続面１０Ｂは、第１方向Ｘに延び、第２方向Ｙに対向している。第３接続面１０Ｃおよび第４接続面１０Ｄは、第２方向Ｙに延び、第１方向Ｘに対向している。 The first to fourth connection surfaces 10A to 10D extend in the normal direction Z and connect the active surface 8 and the outer peripheral surface 9. The first connection surface 10A is located on the first side surface 5A side, the second connection surface 10B is located on the second side surface 5B side, the third connection surface 10C is located on the third side surface 5C side, and the fourth connection surface 10D is located on the fourth side surface 5D side. The first connection surface 10A and the second connection surface 10B extend in the first direction X and face the second direction Y. The third connection surface 10C and the fourth connection surface 10D extend in the second direction Y and face the first direction X.
　第１～第４接続面１０Ａ～１０Ｄは、四角柱状の活性台地１１が区画されるように活性面８および外周面９の間をほぼ垂直に延びていてもよい。第１～第４接続面１０Ａ～１０Ｄは、四角錘台状の活性台地１１が区画されるように活性面８から外周面９に向かって斜め下り傾斜していてもよい。このように、半導体装置１は、第１主面３において第１半導体領域６に突状に区画された活性台地１１を含む。活性台地１１は、第１半導体領域６のみに形成され、第２半導体領域７には形成されていない。 The first to fourth connection surfaces 10A to 10D may extend approximately vertically between the active surface 8 and the outer peripheral surface 9 so as to define a square-prism-shaped active plateau 11. The first to fourth connection surfaces 10A to 10D may be inclined downward from the active surface 8 toward the outer peripheral surface 9 so as to define a square-prism-shaped active plateau 11. In this way, the semiconductor device 1 includes an active plateau 11 that is defined in a protruding shape in the first semiconductor region 6 on the first main surface 3. The active plateau 11 is formed only in the first semiconductor region 6, and is not formed in the second semiconductor region 7.
　図４を参照して、半導体装置１は、活性領域１２、外周領域１３、周縁領域１４および終端領域１５を含む。活性領域１２は、活性面８に設けられている。具体的には、活性領域１２は、活性面８の周縁（第１～第４接続面１０Ａ～１０Ｄ）から間隔を空けて活性面８の内方部に設けられている。活性領域１２は、この形態では、平面視において第１～第４側面５Ａ～５Ｄに平行な４辺を有する四角形状に設けられている。外周領域１３は、外周面９に設けられている。外周領域１３は、この形態では、平面視において活性面８（活性台地１１）を取り囲む環状（具体的に四角環状）に設けられている。 Referring to FIG. 4, the semiconductor device 1 includes an active region 12, an outer peripheral region 13, a peripheral region 14, and a termination region 15. The active region 12 is provided on the active surface 8. Specifically, the active region 12 is provided in the inner portion of the active surface 8 at a distance from the peripheral edge (first to fourth connection surfaces 10A to 10D) of the active surface 8. In this embodiment, the active region 12 is provided in a quadrangle shape having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view. The outer peripheral region 13 is provided on the outer peripheral surface 9. In this embodiment, the outer peripheral region 13 is provided in a ring shape (specifically a quadrangular ring shape) surrounding the active surface 8 (active plateau 11) in a plan view.
　周縁領域１４は、活性領域１２および外周領域１３の間の領域において活性面８に設けられている。周縁領域１４は、第１方向Ｘの両サイドから活性領域１２を挟み込むように設けられ、第２方向Ｙに帯状に延びている。周縁領域１４は、第１周縁領域１４Ａおよび第２周縁領域１４Ｂを含む。第１周縁領域１４Ａは活性領域１２に対して第３側面５Ｃ側（第３接続面１０Ｃ側）に設けられ、第２周縁領域１４Ｂは活性領域１２に対して第４側面５Ｄ側（第４接続面１０Ｄ側）に設けられている。 The peripheral region 14 is provided on the active surface 8 in the region between the active region 12 and the outer peripheral region 13. The peripheral region 14 is provided to sandwich the active region 12 from both sides in the first direction X, and extends in a strip shape in the second direction Y. The peripheral region 14 includes a first peripheral region 14A and a second peripheral region 14B. The first peripheral region 14A is provided on the third side surface 5C side (third connection surface 10C side) of the active region 12, and the second peripheral region 14B is provided on the fourth side surface 5D side (fourth connection surface 10D side) of the active region 12.
　終端領域１５は、活性領域１２および外周領域１３の間の領域において活性面８に設けられている。終端領域１５は、第２方向Ｙの両サイドから活性領域１２を挟み込むように設けられ、第１方向Ｘに帯状に延びている。終端領域１５は、第１終端領域１５Ａおよび第２終端領域１５Ｂを含む。第１終端領域１５Ａは活性領域１２に対して第１側面５Ａ側（第１接続面１０Ａ側）に設けられ、第２終端領域１５Ｂは活性領域１２に対して第２側面５Ｂ側（第２接続面１０Ｂ側）に設けられている。 The termination region 15 is provided on the active surface 8 in the region between the active region 12 and the peripheral region 13. The termination region 15 is provided to sandwich the active region 12 from both sides in the second direction Y, and extends in a strip shape in the first direction X. The termination region 15 includes a first termination region 15A and a second termination region 15B. The first termination region 15A is provided on the first side surface 5A side (first connection surface 10A side) of the active region 12, and the second termination region 15B is provided on the second side surface 5B side (second connection surface 10B side) of the active region 12.
　半導体装置１は、第１主面３を被覆する主面絶縁膜１６を含む。主面絶縁膜１６は、活性面８、外周面９および第１～第４接続面１０Ａ～１０Ｄを選択的に被覆している。主面絶縁膜１６は、酸化シリコン膜、窒化シリコン膜および酸窒化シリコン膜のうちの少なくとも１つを含んでいてもよい。 The semiconductor device 1 includes a main surface insulating film 16 that covers the first main surface 3. The main surface insulating film 16 selectively covers the active surface 8, the outer peripheral surface 9, and the first to fourth connection surfaces 10A to 10D. The main surface insulating film 16 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
　主面絶縁膜１６は、この形態では、酸化シリコン膜からなる単層構造を有している。主面絶縁膜１６は、チップ２の酸化物からなる酸化シリコン膜を含むことが特に好ましい。主面絶縁膜１６は、この形態では、第１～第４側面５Ａ～５Ｄに連なっている。むろん、主面絶縁膜１６の壁部は、外周面９の周縁から内方に間隔を空けて形成され、外周面９の周縁部から第１半導体領域６を露出させていてもよい。 In this embodiment, the main surface insulating film 16 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the main surface insulating film 16 includes a silicon oxide film made of an oxide of the chip 2. In this embodiment, the main surface insulating film 16 is continuous with the first to fourth side surfaces 5A to 5D. Of course, the wall portion of the main surface insulating film 16 may be formed at a distance inward from the periphery of the outer peripheral surface 9, exposing the first semiconductor region 6 from the periphery of the outer peripheral surface 9.
　図５は、活性領域１２のレイアウトを示す拡大平面図である。図６は、周縁領域１４のレイアウトを示す拡大平面図である。図７は、図５に示すVII-VII線に沿う断面図である。図８は、図５に示すVIII-VIII線に沿う断面図である。図９は、図６に示すIX-IX線に沿う断面図である。図１０は、図６に示すX-X線に沿う断面図である。図１１は、図６に示すXI-XI線に沿う断面図である。図１２は、図６に示すXII-XII線に沿う断面図である。 FIG. 5 is an enlarged plan view showing the layout of the active region 12. FIG. 6 is an enlarged plan view showing the layout of the peripheral region 14. FIG. 7 is a cross-sectional view taken along line VII-VII shown in FIG. 5. FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG. 5. FIG. 9 is a cross-sectional view taken along line IX-IX shown in FIG. 6. FIG. 10 is a cross-sectional view taken along line X-X shown in FIG. 6. FIG. 11 is a cross-sectional view taken along line XI-XI shown in FIG. 6. FIG. 12 is a cross-sectional view taken along line XII-XII shown in FIG. 6.
　図６では、第１周縁領域１４Ａ側のレイアウトが示されている。第２周縁領域１４Ｂ側のレイアウトは第１周縁領域１４Ａ側のレイアウトとほぼ同様であるため、以下では、第１周縁領域１４Ａ側のレイアウトが主に説明される。第２周縁領域１４Ｂ側のレイアウトは、以下の説明において「第３接続面１０Ｃ」を「第４接続面１０Ｄ」に置き換えることによって得られる。 In FIG. 6, the layout on the first peripheral region 14A side is shown. Since the layout on the second peripheral region 14B side is almost the same as the layout on the first peripheral region 14A side, the layout on the first peripheral region 14A side will be mainly described below. The layout on the second peripheral region 14B side can be obtained by replacing "third connection surface 10C" with "fourth connection surface 10D" in the following description.
　図５～図１２を参照して、半導体装置１は、第１主面３（活性面８）の表層部に形成されたｐ型（第２導電型）のボディ領域１７を含む。ボディ領域１７は、第１半導体領域６の底部から活性面８側に間隔を空けて形成されている。ボディ領域１７は、活性面８に沿って延びる層状に形成されている。ボディ領域１７は、活性面８の全域に形成され、第１～第４接続面１０Ａ～１０Ｄから露出していてもよい。 Referring to Figures 5 to 12, the semiconductor device 1 includes a p-type (second conductivity type) body region 17 formed in a surface layer portion of the first main surface 3 (active surface 8). The body region 17 is formed at a distance from the bottom of the first semiconductor region 6 toward the active surface 8. The body region 17 is formed in a layer extending along the active surface 8. The body region 17 is formed over the entire active surface 8, and may be exposed from the first to fourth connection surfaces 10A to 10D.
　半導体装置１は、活性領域１２において第１主面３（活性面８）の表層部に形成されたｎ型のソース領域１８を含む。具体的には、ソース領域１８は、ボディ領域１７の底部から活性面８側に間隔を空けてボディ領域１７の表層部に形成されている。ソース領域１８は、周縁領域１４および終端領域１５には形成されていない。 The semiconductor device 1 includes an n-type source region 18 formed in a surface layer portion of the first main surface 3 (active surface 8) in the active region 12. Specifically, the source region 18 is formed in the surface layer portion of the body region 17 with a gap from the bottom of the body region 17 toward the active surface 8. The source region 18 is not formed in the peripheral region 14 or the termination region 15.
　むろん、ソース領域１８は、チャネルの制御に影響を与えない範囲において、周縁領域１４および終端領域１５に形成されていてもよい。ソース領域１８は、第１半導体領域６よりも高いｎ型不純物濃度を有している。ソース領域１８は、ボディ領域１７内において第１半導体領域６とＭＩＳＦＥＴのチャネルを形成する。 Of course, the source region 18 may be formed in the peripheral region 14 and the termination region 15 to the extent that it does not affect the control of the channel. The source region 18 has a higher n-type impurity concentration than the first semiconductor region 6. The source region 18 forms a channel of the MISFET together with the first semiconductor region 6 in the body region 17.
　半導体装置１は、活性領域１２において第１主面３（活性面８）に形成された複数のトレンチゲート構造２０を含む。複数のトレンチゲート構造２０には、第１電位としてのゲート電位ＶＧが付与される。複数のトレンチゲート構造２０は、ボディ領域１７内におけるチャネルの反転および非反転を制御する。複数のトレンチゲート構造２０は、平面視において第１方向Ｘに延びる帯状にそれぞれ形成され、第２方向Ｙに間隔を空けて配列されている。 The semiconductor device 1 includes a plurality of trench gate structures 20 formed on the first main surface 3 (active surface 8) in the active region 12. A gate potential VG is applied to the plurality of trench gate structures 20 as a first potential. The plurality of trench gate structures 20 control the inversion and non-inversion of the channel in the body region 17. The plurality of trench gate structures 20 are each formed in a band shape extending in the first direction X in a plan view, and are arranged at intervals in the second direction Y.
　複数のトレンチゲート構造２０は、この形態では、活性面８の周縁から間隔を空けて活性面８の内方部に配置されている。具体的には、複数のトレンチゲート構造２０は、第１～第４接続面１０Ａ～１０Ｄから第１方向Ｘおよび第２方向Ｙに間隔を空けて配置されている。 In this embodiment, the multiple trench gate structures 20 are arranged inward of the active surface 8 at intervals from the periphery of the active surface 8. Specifically, the multiple trench gate structures 20 are arranged at intervals in the first direction X and the second direction Y from the first to fourth connection surfaces 10A to 10D.
　複数のトレンチゲート構造２０は、活性面８の内方部に活性領域１２を区画すると同時に、活性面８の周縁と共に周縁領域１４および終端領域１５を区画している。複数のトレンチゲート構造２０は、第１半導体領域６に至るようにボディ領域１７およびソース領域１８を貫通している。複数のトレンチゲート構造２０は、第１半導体領域６の底部から活性面８側に間隔を空けて形成されている。 The multiple trench gate structures 20 define an active region 12 in the inner part of the active surface 8, and at the same time define a peripheral region 14 and a termination region 15 together with the periphery of the active surface 8. The multiple trench gate structures 20 penetrate the body region 17 and the source region 18 to reach the first semiconductor region 6. The multiple trench gate structures 20 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.
　以下、１つのトレンチゲート構造２０が説明される。トレンチゲート構造２０は、第２方向Ｙに第１幅Ｗ１を有し、法線方向Ｚに第１深さＤ１を有している。第１幅Ｗ１は、０．１μｍ以上３μｍ以下であってもよい。第１幅Ｗ１は、０．５μｍ以上２μｍ以下であることが好ましい。第１深さＤ１は、外周面９の外周深さＤＯ未満である。第１深さＤ１は、０．１μｍ以上３μｍ以下であってもよい。第１深さＤ１は、０．５μｍ以上１．５μｍ以下であることが好ましい。 Below, one trench gate structure 20 is described. The trench gate structure 20 has a first width W1 in the second direction Y and a first depth D1 in the normal direction Z. The first width W1 may be 0.1 μm or more and 3 μm or less. The first width W1 is preferably 0.5 μm or more and 2 μm or less. The first depth D1 is less than the outer circumferential depth DO of the outer circumferential surface 9. The first depth D1 may be 0.1 μm or more and 3 μm or less. The first depth D1 is preferably 0.5 μm or more and 1.5 μm or less.
　トレンチゲート構造２０は、ゲートトレンチ２１、ゲート絶縁膜２２およびゲート埋設電極２３を含む。ゲートトレンチ２１は、活性面８に形成され、トレンチゲート構造２０の壁面を区画している。ゲート絶縁膜２２は、ゲートトレンチ２１の壁面を被覆し、活性面８において主面絶縁膜１６に接続されている。ゲート絶縁膜２２は、酸化シリコン膜、窒化シリコン膜および酸窒化シリコン膜のうちの少なくとも１つを含んでいてもよい。 The trench gate structure 20 includes a gate trench 21, a gate insulating film 22, and a gate buried electrode 23. The gate trench 21 is formed in the active surface 8 and defines the wall surface of the trench gate structure 20. The gate insulating film 22 covers the wall surface of the gate trench 21 and is connected to the main surface insulating film 16 at the active surface 8. The gate insulating film 22 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
　ゲート絶縁膜２２は、この形態では、酸化シリコン膜からなる単層構造を有している。ゲート絶縁膜２２は、チップ２の酸化物からなる酸化シリコン膜を含むことが特に好ましい。ゲート埋設電極２３は、ゲート絶縁膜２２を挟んでゲートトレンチ２１に埋設され、ゲート絶縁膜２２を挟んでチャネルに対向している。ゲート埋設電極２３は、導電性ポリシリコンを含んでいてもよい。 In this embodiment, the gate insulating film 22 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the gate insulating film 22 contains a silicon oxide film made of an oxide of the chip 2. The gate buried electrode 23 is buried in the gate trench 21 with the gate insulating film 22 in between, and faces the channel with the gate insulating film 22 in between. The gate buried electrode 23 may contain conductive polysilicon.
　半導体装置１は、活性領域１２において第１主面３（活性面８）に形成された複数の第１トレンチソース構造２５を含む。複数の第１トレンチソース構造２５には、第１電位とは異なる第２電位としてのソース電位ＶＳが付与される。ソース電位ＶＳは、動作基準となる基準電位（たとえばグランド電位）であってもよい。 The semiconductor device 1 includes a plurality of first trench source structures 25 formed in the first main surface 3 (active surface 8) in the active region 12. A source potential VS is applied to the plurality of first trench source structures 25 as a second potential different from the first potential. The source potential VS may be a reference potential (e.g., ground potential) that serves as an operating reference.
　複数の第１トレンチソース構造２５は、隣り合う２つのトレンチゲート構造２０の間の領域にそれぞれ配置されている。複数の第１トレンチソース構造２５は、平面視において第２方向Ｙに複数のトレンチゲート構造２０と交互に配列され、第１方向Ｘに延びる帯状にそれぞれ形成されている。複数の第１トレンチソース構造２５は、この形態では、活性領域１２から周縁領域１４に引き出されている。複数の第１トレンチソース構造２５は、第３接続面１０Ｃおよび第４接続面１０Ｄのうちの少なくとも一方から露出している。 The multiple first trench source structures 25 are each disposed in a region between two adjacent trench gate structures 20. The multiple first trench source structures 25 are arranged alternately with the multiple trench gate structures 20 in the second direction Y in a plan view, and are each formed in a strip shape extending in the first direction X. In this embodiment, the multiple first trench source structures 25 are drawn out from the active region 12 to the peripheral region 14. The multiple first trench source structures 25 are exposed from at least one of the third connection surface 10C and the fourth connection surface 10D.
　複数の第１トレンチソース構造２５は、この形態では、第３接続面１０Ｃおよび第４接続面１０Ｄの双方を貫通し、第３接続面１０Ｃおよび第４接続面１０Ｄの双方から露出している。複数の第１トレンチソース構造２５は、活性領域１２において第２方向Ｙにトレンチゲート構造２０に対向し、周縁領域１４において第２方向Ｙにトレンチゲート構造２０に対向していない。 In this embodiment, the multiple first trench source structures 25 penetrate both the third connection surface 10C and the fourth connection surface 10D and are exposed from both the third connection surface 10C and the fourth connection surface 10D. The multiple first trench source structures 25 face the trench gate structure 20 in the second direction Y in the active region 12, and do not face the trench gate structure 20 in the second direction Y in the peripheral region 14.
　複数の第１トレンチソース構造２５は、第１半導体領域６に至るように活性領域１２においてボディ領域１７およびソース領域１８を貫通し、周縁領域１４においてボディ領域１７を貫通している。複数の第１トレンチソース構造２５は、第１半導体領域６の底部から活性面８側に間隔を空けて形成されている。 The multiple first trench source structures 25 penetrate the body region 17 and source region 18 in the active region 12 to reach the first semiconductor region 6, and penetrate the body region 17 in the peripheral region 14. The multiple first trench source structures 25 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.
　以下、１つの第１トレンチソース構造２５が説明される。第１トレンチソース構造２５は、第２方向Ｙに第２幅Ｗ２を有し、法線方向Ｚに第２深さＤ２を有している。第２幅Ｗ２は、第１幅Ｗ１とほぼ等しいことが好ましい。第２幅Ｗ２は、０．１μｍ以上３μｍ以下であってもよい。第２幅Ｗ２は、０．５μｍ以上２μｍ以下であることが好ましい。 Below, one first trench source structure 25 is described. The first trench source structure 25 has a second width W2 in the second direction Y and a second depth D2 in the normal direction Z. The second width W2 is preferably approximately equal to the first width W1. The second width W2 may be 0.1 μm or more and 3 μm or less. The second width W2 is preferably 0.5 μm or more and 2 μm or less.
　第２深さＤ２は、第１深さＤ１以上である。第２深さＤ２は、この形態では、第１深さＤ１よりも大きい。第２深さＤ２は、第１深さＤ１の１．５倍以上３倍以下であることが好ましい。第２深さＤ２は、この形態では、外周面９の外周深さＤＯとほぼ等しい。第２深さＤ２は、０．５μｍ以上５μｍ以下であってもよい。第２深さＤ２は、２．５μｍ以下であることが特に好ましい。 The second depth D2 is equal to or greater than the first depth D1. In this embodiment, the second depth D2 is greater than the first depth D1. It is preferable that the second depth D2 is 1.5 to 3 times the first depth D1. In this embodiment, the second depth D2 is approximately equal to the outer circumferential depth DO of the outer circumferential surface 9. The second depth D2 may be 0.5 μm to 5 μm. It is particularly preferable that the second depth D2 is 2.5 μm or less.
　第１トレンチソース構造２５は、第２方向Ｙにトレンチゲート構造２０から第１間隔Ｉ１を空けて配置されている。第１間隔Ｉ１は、第１幅Ｗ１（第２幅Ｗ２）の０．５倍以上２倍以下であることが好ましい。第１間隔Ｉ１は、第１幅Ｗ１（第２幅Ｗ２）未満であることが特に好ましい。第１間隔Ｉ１は、０．１μｍ以上２．５μｍ以下であってもよい。第１間隔Ｉ１は、０．５μｍ以上１．５μｍ以下であることが好ましい。 The first trench source structure 25 is disposed in the second direction Y at a first distance I1 from the trench gate structure 20. It is preferable that the first distance I1 is 0.5 to 2 times the first width W1 (second width W2). It is particularly preferable that the first distance I1 is less than the first width W1 (second width W2). The first distance I1 may be 0.1 μm to 2.5 μm. It is preferable that the first distance I1 is 0.5 μm to 1.5 μm.
　第１トレンチソース構造２５は、第１ソーストレンチ２６、第１ソース絶縁膜２７および第１ソース埋設電極２８を含む。第１ソーストレンチ２６は、活性面８に形成され、第１トレンチソース構造２５の壁面を区画している。第１ソーストレンチ２６の側壁は、第３接続面１０Ｃおよび第４接続面１０Ｄに連通している。第１ソーストレンチ２６の底壁は、外周面９に連通している。 The first trench source structure 25 includes a first source trench 26, a first source insulating film 27, and a first source buried electrode 28. The first source trench 26 is formed in the active surface 8 and defines the wall surface of the first trench source structure 25. The sidewall of the first source trench 26 is in communication with the third connection surface 10C and the fourth connection surface 10D. The bottom wall of the first source trench 26 is in communication with the outer peripheral surface 9.
　第１ソース絶縁膜２７は、第１ソーストレンチ２６の壁面を被覆し、活性面８において主面絶縁膜１６に接続されている。第１ソース絶縁膜２７は、第３接続面１０Ｃの連通部、第４接続面１０Ｄの連通部および外周面９の連通部において主面絶縁膜１６に接続されている。第１ソース絶縁膜２７は、酸化シリコン膜、窒化シリコン膜および酸窒化シリコン膜のうちの少なくとも１つを含んでいてもよい。 The first source insulating film 27 covers the wall surface of the first source trench 26 and is connected to the main surface insulating film 16 at the active surface 8. The first source insulating film 27 is connected to the main surface insulating film 16 at the communicating portion of the third connection surface 10C, the communicating portion of the fourth connection surface 10D, and the communicating portion of the outer peripheral surface 9. The first source insulating film 27 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
　第１ソース絶縁膜２７は、この形態では、酸化シリコン膜からなる単層構造を有している。第１ソース絶縁膜２７は、チップ２の酸化物からなる酸化シリコン膜を含むことが特に好ましい。第１ソース埋設電極２８は、第１ソース絶縁膜２７を挟んで第１ソーストレンチ２６に埋設されている。第１ソース埋設電極２８は、導電性ポリシリコンを含んでいてもよい。 In this embodiment, the first source insulating film 27 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the first source insulating film 27 includes a silicon oxide film made of an oxide of the chip 2. The first source buried electrode 28 is buried in the first source trench 26 with the first source insulating film 27 in between. The first source buried electrode 28 may include conductive polysilicon.
　半導体装置１は、周縁領域１４において第１主面３（活性面８）に形成された複数の第２トレンチソース構造３０を含む。複数の第２トレンチソース構造３０には、ソース電位ＶＳが付与される。複数の第２トレンチソース構造３０は、活性面８の周縁（第３接続面１０Ｃ）および複数のトレンチゲート構造２０の間の領域に配置されている。複数の第２トレンチソース構造３０は、第２方向Ｙに隣り合う２つの第１トレンチソース構造２５の間の領域に配置され、第１方向Ｘに複数のトレンチゲート構造２０に１対１の対応関係で対向している。 The semiconductor device 1 includes a plurality of second trench source structures 30 formed in the first main surface 3 (active surface 8) in the peripheral region 14. A source potential VS is applied to the plurality of second trench source structures 30. The plurality of second trench source structures 30 are arranged in a region between the periphery (third connection surface 10C) of the active surface 8 and the plurality of trench gate structures 20. The plurality of second trench source structures 30 are arranged in a region between two first trench source structures 25 adjacent to each other in the second direction Y, and face the plurality of trench gate structures 20 in a one-to-one correspondence in the first direction X.
　複数の第２トレンチソース構造３０は、平面視において第１方向Ｘに延びる帯状にそれぞれ形成されている。複数の第２トレンチソース構造３０は、この形態では、第３接続面１０Ｃを貫通し、第３接続面１０Ｃから露出している。複数の第２トレンチソース構造３０は、第１半導体領域６に至るようにボディ領域１７を貫通している。複数の第２トレンチソース構造３０は、第１半導体領域６の底部から活性面８側に間隔を空けて形成されている。 The multiple second trench source structures 30 are each formed in a band shape extending in the first direction X in a plan view. In this embodiment, the multiple second trench source structures 30 penetrate the third connection surface 10C and are exposed from the third connection surface 10C. The multiple second trench source structures 30 penetrate the body region 17 to reach the first semiconductor region 6. The multiple second trench source structures 30 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.
　以下、１つの第２トレンチソース構造３０が説明される。第２トレンチソース構造３０は、第２方向Ｙに第３幅Ｗ３を有し、法線方向Ｚに第３深さＤ３を有している。第３幅Ｗ３は、トレンチゲート構造２０の第１幅Ｗ１とほぼ等しいことが好ましい。第３幅Ｗ３は、第１トレンチソース構造２５の第２幅Ｗ２とほぼ等しいことが好ましい。第３幅Ｗ３は、０．１μｍ以上３μｍ以下であってもよい。第３幅Ｗ３は、０．５μｍ以上２μｍ以下であることが好ましい。 Below, one second trench source structure 30 is described. The second trench source structure 30 has a third width W3 in the second direction Y and a third depth D3 in the normal direction Z. The third width W3 is preferably approximately equal to the first width W1 of the trench gate structure 20. The third width W3 is preferably approximately equal to the second width W2 of the first trench source structure 25. The third width W3 may be 0.1 μm or more and 3 μm or less. The third width W3 is preferably 0.5 μm or more and 2 μm or less.
　第３深さＤ３は、トレンチゲート構造２０の第１深さＤ１以上である。第３深さＤ３は、この形態では、第１深さＤ１よりも大きい。第３深さＤ３は、第１深さＤ１の１．５倍以上３倍以下であることが好ましい。第３深さＤ３は、この形態では、第１トレンチソース構造２５の第２深さＤ２とほぼ等しい。第３深さＤ３は、外周面９の外周深さＤＯとほぼ等しい。第３深さＤ３は、０．５μｍ以上５μｍ以下であってもよい。第３深さＤ３は、２．５μｍ以下であることが特に好ましい。 The third depth D3 is equal to or greater than the first depth D1 of the trench gate structure 20. In this embodiment, the third depth D3 is greater than the first depth D1. It is preferable that the third depth D3 is equal to or greater than 1.5 times and equal to or less than 3 times the first depth D1. In this embodiment, the third depth D3 is approximately equal to the second depth D2 of the first trench source structure 25. The third depth D3 is approximately equal to the outer circumferential depth DO of the outer circumferential surface 9. The third depth D3 may be equal to or greater than 0.5 μm and equal to or less than 5 μm. It is particularly preferable that the third depth D3 is equal to or less than 2.5 μm.
　第２トレンチソース構造３０は、第２方向Ｙに第１トレンチソース構造２５から第２間隔Ｉ２を空けて配置されている。第２間隔Ｉ２は、第２幅Ｗ２（第３幅Ｗ３）の０．５倍以上２倍以下であることが好ましい。第２間隔Ｉ２は、第２幅Ｗ２（第３幅Ｗ３）未満であることが特に好ましい。第２間隔Ｉ２は、第１間隔Ｉ１とほぼ等しいことが好ましい。第２間隔Ｉ２は、０．１μｍ以上２．５μｍ以下であってもよい。第２間隔Ｉ２は、０．５μｍ以上１．５μｍ以下であることが好ましい。 The second trench source structure 30 is disposed in the second direction Y at a second distance I2 from the first trench source structure 25. The second distance I2 is preferably 0.5 to 2 times the second width W2 (third width W3). It is particularly preferable that the second distance I2 is less than the second width W2 (third width W3). It is preferable that the second distance I2 is approximately equal to the first distance I1. The second distance I2 may be 0.1 μm to 2.5 μm. It is preferable that the second distance I2 is 0.5 μm to 1.5 μm.
　第２トレンチソース構造３０は、第１方向Ｘにトレンチゲート構造２０から第３間隔Ｉ３を空けて配置されている。第３間隔Ｉ３は、第１幅Ｗ１（第３幅Ｗ３）の０．５倍以上２倍以下であることが好ましい。第３間隔Ｉ３は、第１間隔Ｉ１（第２間隔Ｉ２）の０．５倍以上２倍以下であることが好ましい。第３間隔Ｉ３は、第１間隔Ｉ１（第２間隔Ｉ２）の１．５倍以下であることが特に好ましい。第３間隔Ｉ３は、第１間隔Ｉ１（第２間隔Ｉ２）とほぼ等しくてもよい。第３間隔Ｉ３は、０．１μｍ以上２．５μｍ以下であってもよい。第３間隔Ｉ３は、０．５μｍ以上１．５μｍ以下であることが好ましい。 The second trench source structure 30 is disposed in the first direction X at a third interval I3 from the trench gate structure 20. The third interval I3 is preferably 0.5 to 2 times the first width W1 (third width W3). The third interval I3 is preferably 0.5 to 2 times the first interval I1 (second interval I2). It is particularly preferable that the third interval I3 is 1.5 times or less the first interval I1 (second interval I2). The third interval I3 may be approximately equal to the first interval I1 (second interval I2). The third interval I3 may be 0.1 μm to 2.5 μm. It is preferable that the third interval I3 is 0.5 μm to 1.5 μm.
　第２トレンチソース構造３０は、第２ソーストレンチ３１、第２ソース絶縁膜３２および第２ソース埋設電極３３を含む。第２ソーストレンチ３１は、活性面８に形成され、第２トレンチソース構造３０の壁面を区画している。第２ソーストレンチ３１の側壁は、第３接続面１０Ｃに連通している。第２ソーストレンチ３１の底壁は、外周面９に連通している。 The second trench source structure 30 includes a second source trench 31, a second source insulating film 32, and a second source buried electrode 33. The second source trench 31 is formed in the active surface 8 and defines the wall surface of the second trench source structure 30. The side wall of the second source trench 31 is connected to the third connection surface 10C. The bottom wall of the second source trench 31 is connected to the outer peripheral surface 9.
　第２ソース絶縁膜３２は、第２ソーストレンチ３１の壁面を被覆し、活性面８において主面絶縁膜１６に接続されている。第２ソース絶縁膜３２は、第３接続面１０Ｃの連通部および外周面９の連通部において主面絶縁膜１６に接続されている。第２ソース絶縁膜３２は、酸化シリコン膜、窒化シリコン膜および酸窒化シリコン膜のうちの少なくとも１つを含んでいてもよい。 The second source insulating film 32 covers the wall surface of the second source trench 31 and is connected to the main surface insulating film 16 at the active surface 8. The second source insulating film 32 is connected to the main surface insulating film 16 at the communicating portion of the third connection surface 10C and the communicating portion of the outer peripheral surface 9. The second source insulating film 32 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
　第２ソース絶縁膜３２は、この形態では、酸化シリコン膜からなる単層構造を有している。第２ソース絶縁膜３２は、チップ２の酸化物からなる酸化シリコン膜を含むことが特に好ましい。第２ソース埋設電極３３は、第２ソース絶縁膜３２を挟んで第２ソーストレンチ３１に埋設されている。第２ソース埋設電極３３は、導電性ポリシリコンを含んでいてもよい。 In this embodiment, the second source insulating film 32 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the second source insulating film 32 includes a silicon oxide film made of an oxide of the chip 2. The second source buried electrode 33 is buried in the second source trench 31 with the second source insulating film 32 in between. The second source buried electrode 33 may include conductive polysilicon.
　半導体装置１は、活性領域１２において複数のトレンチゲート構造２０に沿う領域に形成されたｐ型の複数の第１ウェル領域３５を含む。第１ウェル領域３５は、この形態では、ボディ領域１７よりも高いｐ型不純物濃度を有している。むろん、第１ウェル領域３５のｐ型不純物濃度は、ボディ領域１７よりも低くてもよい。 The semiconductor device 1 includes a plurality of p-type first well regions 35 formed in the active region 12 in a region along the plurality of trench gate structures 20. In this embodiment, the first well regions 35 have a higher p-type impurity concentration than the body region 17. Of course, the p-type impurity concentration of the first well regions 35 may be lower than that of the body region 17.
　複数の第１ウェル領域３５は、それと隣り合う第１トレンチソース構造２５から間隔を空けて対応するトレンチゲート構造２０の壁面を被覆し、活性面８の表層部においてボディ領域１７に電気的に接続されている。複数の第１ウェル領域３５は、第１半導体領域６の底部から活性面８側に間隔を空けて形成され、第１半導体領域６の一部を挟んで第２半導体領域７に対向している。複数の第１ウェル領域３５は、第１半導体領域６とｐｎ接合部を形成している。 The multiple first well regions 35 cover the wall surfaces of the corresponding trench gate structures 20 at intervals from the adjacent first trench source structures 25, and are electrically connected to the body region 17 at the surface portion of the active surface 8. The multiple first well regions 35 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 with a part of the first semiconductor region 6 in between. The multiple first well regions 35 form pn junctions with the first semiconductor region 6.
　半導体装置１は、活性領域１２および周縁領域１４において複数の第１トレンチソース構造２５に沿う領域に形成されたｐ型の複数の第２ウェル領域３６を含む。第２ウェル領域３６は、この形態では、ボディ領域１７よりも高いｐ型不純物濃度を有している。むろん、第２ウェル領域３６のｐ型不純物濃度は、ボディ領域１７よりも低くてもよい。第２ウェル領域３６のｐ型不純物濃度は、第１ウェル領域３５のｐ型不純物濃度とほぼ等しいことが好ましい。 The semiconductor device 1 includes a plurality of p-type second well regions 36 formed in the active region 12 and the peripheral region 14 in regions along the plurality of first trench source structures 25. In this embodiment, the second well regions 36 have a higher p-type impurity concentration than the body region 17. Of course, the p-type impurity concentration of the second well regions 36 may be lower than the body region 17. It is preferable that the p-type impurity concentration of the second well regions 36 is approximately equal to the p-type impurity concentration of the first well region 35.
　複数の第２ウェル領域３６は、それと隣り合うトレンチゲート構造２０から間隔を空けて対応する第１トレンチソース構造２５の壁面を被覆し、活性面８の表層部においてボディ領域１７に電気的に接続されている。複数の第２ウェル領域３６は、活性領域１２および周縁領域１４において対応する第１トレンチソース構造２５の壁面を被覆し、第３接続面１０Ｃおよび第４接続面１０Ｄから露出している。 The second well regions 36 cover the walls of the corresponding first trench source structures 25 at intervals from the adjacent trench gate structures 20 and are electrically connected to the body region 17 at the surface portion of the active surface 8. The second well regions 36 cover the walls of the corresponding first trench source structures 25 in the active region 12 and the peripheral region 14 and are exposed from the third connection surface 10C and the fourth connection surface 10D.
　複数の第２ウェル領域３６は、第１半導体領域６の底部から活性面８側に間隔を空けて形成され、第１半導体領域６の一部を挟んで第２半導体領域７に対向している。複数の第２ウェル領域３６の底部は、複数の第１ウェル領域３５の底部の深さ位置に対して第１半導体領域６の底部側に位置している。複数の第２ウェル領域３６は、第１半導体領域６とｐｎ接合部を形成している。 The multiple second well regions 36 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 across a portion of the first semiconductor region 6. The bottoms of the multiple second well regions 36 are located on the bottom side of the first semiconductor region 6 relative to the depth positions of the bottoms of the multiple first well regions 35. The multiple second well regions 36 form pn junctions with the first semiconductor region 6.
　半導体装置１は、周縁領域１４において複数の第２トレンチソース構造３０に沿う領域に形成されたｐ型の複数の第３ウェル領域３７を含む。第３ウェル領域３７は、この形態では、ボディ領域１７よりも高いｐ型不純物濃度を有している。むろん、第３ウェル領域３７のｐ型不純物濃度は、ボディ領域１７よりも低くてもよい。第３ウェル領域３７のｐ型不純物濃度は、第１ウェル領域３５（第２ウェル領域３６）のｐ型不純物濃度とほぼ等しいことが好ましい。 The semiconductor device 1 includes a plurality of p-type third well regions 37 formed in the peripheral region 14 in a region along the plurality of second trench source structures 30. In this embodiment, the third well region 37 has a higher p-type impurity concentration than the body region 17. Of course, the p-type impurity concentration of the third well region 37 may be lower than the body region 17. It is preferable that the p-type impurity concentration of the third well region 37 is approximately equal to the p-type impurity concentration of the first well region 35 (second well region 36).
　複数の第３ウェル領域３７は、それと隣り合うトレンチゲート構造２０およびそれと隣り合う第１トレンチソース構造２５から間隔を空けて対応する第２トレンチソース構造３０の壁面を被覆し、活性面８の表層部においてボディ領域１７に電気的に接続されている。むろん、第３ウェル領域３７は、トレンチゲート構造２０および第２トレンチソース構造３０の間の領域において第１ウェル領域３５と一体化していてもよい。複数の第３ウェル領域３７は、第３接続面１０Ｃから露出している。 The multiple third well regions 37 cover the walls of the corresponding second trench source structures 30 at intervals from the adjacent trench gate structures 20 and the adjacent first trench source structures 25, and are electrically connected to the body region 17 in the surface portion of the active surface 8. Of course, the third well regions 37 may be integrated with the first well region 35 in the region between the trench gate structures 20 and the second trench source structures 30. The multiple third well regions 37 are exposed from the third connection surface 10C.
　複数の第３ウェル領域３７は、第１半導体領域６の底部から活性面８側に間隔を空けて形成され、第１半導体領域６の一部を挟んで第２半導体領域７に対向している。複数の第３ウェル領域３７の底部は、複数の第１ウェル領域３５の底部の深さ位置に対して第１半導体領域６の底部側に位置している。複数の第３ウェル領域３７の底部は、複数の第２ウェル領域３６の底部とほぼ等しい深さに形成されている。複数の第３ウェル領域３７は、第１半導体領域６とｐｎ接合部を形成している。 The multiple third well regions 37 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 across a portion of the first semiconductor region 6. The bottoms of the multiple third well regions 37 are located on the bottom side of the first semiconductor region 6 relative to the depth position of the bottoms of the multiple first well regions 35. The bottoms of the multiple third well regions 37 are formed at approximately the same depth as the bottoms of the multiple second well regions 36. The multiple third well regions 37 form pn junctions with the first semiconductor region 6.
　半導体装置１は、活性領域１２において複数の第１トレンチソース構造２５に沿う領域に形成されたｐ型の複数の第１コンタクト領域３８を含む。第１コンタクト領域３８は、ボディ領域１７よりも高いｐ型不純物濃度を有している。第１コンタクト領域３８のｐ型不純物濃度は、この形態では、第２ウェル領域３６よりも高い。 The semiconductor device 1 includes a plurality of first contact regions 38 of p-type formed in the active region 12 in a region along the plurality of first trench source structures 25. The first contact regions 38 have a higher p-type impurity concentration than the body region 17. In this embodiment, the p-type impurity concentration of the first contact regions 38 is higher than that of the second well region 36.
　複数の第１コンタクト領域３８は、対応する第２ウェル領域３６内において対応する第１トレンチソース構造２５の壁面を被覆している。複数の第１コンタクト領域３８は、各第１トレンチソース構造２５に対して１対多の対応関係で形成されている。複数の第１コンタクト領域３８は、対応する第１トレンチソース構造２５に沿って間隔を空けて形成されている。 The multiple first contact regions 38 cover the wall surfaces of the corresponding first trench source structures 25 in the corresponding second well regions 36. The multiple first contact regions 38 are formed in a one-to-many correspondence with each first trench source structure 25. The multiple first contact regions 38 are formed at intervals along the corresponding first trench source structures 25.
　複数の第１コンタクト領域３８は、対応する第２ウェル領域３６内から対応する第１トレンチソース構造２５の壁面に沿ってボディ領域１７の表層部に引き出され、活性面８から露出している。複数の第１コンタクト領域３８は、活性領域１２に形成され、周縁領域１４には形成されていない。つまり、複数の第１コンタクト領域３８は、第２方向Ｙにトレンチゲート構造２０に対向し、第２方向Ｙに第２トレンチソース構造３０に対向していない。第１コンタクト領域３８は、第３ウェル領域３７内に形成されていない。 The multiple first contact regions 38 are pulled out from within the corresponding second well region 36 along the wall surface of the corresponding first trench source structure 25 to the surface layer of the body region 17 and exposed from the active surface 8. The multiple first contact regions 38 are formed in the active region 12 and are not formed in the peripheral region 14. In other words, the multiple first contact regions 38 face the trench gate structure 20 in the second direction Y, but do not face the second trench source structure 30 in the second direction Y. The first contact regions 38 are not formed in the third well region 37.
　複数の第１コンタクト領域３８は、この形態では、平面視において第１方向Ｘに延びる帯状にそれぞれ形成されている。複数の第１コンタクト領域３８の第１方向Ｘの長さは、第１トレンチソース構造２５の第２幅Ｗ２以上であることが好ましい。複数の第１コンタクト領域３８の長さは、第１方向Ｘに隣り合う２つの第１コンタクト領域３８の間の距離よりも大きいことが好ましい。 In this embodiment, the multiple first contact regions 38 are each formed in a band shape extending in the first direction X in a plan view. The length of the multiple first contact regions 38 in the first direction X is preferably equal to or greater than the second width W2 of the first trench source structure 25. The length of the multiple first contact regions 38 is preferably greater than the distance between two adjacent first contact regions 38 in the first direction X.
　１つの第１トレンチソース構造２５に沿う複数の第１コンタクト領域３８は、他の第１トレンチソース構造２５に沿う複数の第１コンタクト領域３８に第２方向Ｙに対向している。つまり、複数の第１コンタクト領域３８は、この形態では、平面視において全体として第１方向Ｘおよび第２方向Ｙに間隔を空けて行列状に配列されている。 The first contact regions 38 along one first trench source structure 25 face the first contact regions 38 along the other first trench source structure 25 in the second direction Y. In other words, in this embodiment, the first contact regions 38 are arranged in a matrix shape with gaps in between in the first direction X and the second direction Y as a whole when viewed in a plan view.
　１つの第１トレンチソース構造２５に沿う複数の第１コンタクト領域３８は、他の第１トレンチソース構造２５に沿う複数の第１コンタクト領域３８の間の領域に第２方向Ｙに対向するように第１方向Ｘにずれて配列されていてもよい。つまり、複数の第１コンタクト領域３８は、平面視において全体として第１方向Ｘおよび第２方向Ｙに間隔を空けて千鳥状に配列されていてもよい。 The first contact regions 38 along one first trench source structure 25 may be arranged offset in the first direction X so as to face the second direction Y in a region between the first contact regions 38 along another first trench source structure 25. In other words, the first contact regions 38 may be arranged in a staggered manner with gaps in the first direction X and the second direction Y as a whole in a plan view.
　半導体装置１は、活性領域１２において第１主面３（活性面８）の上で複数のトレンチゲート構造２０の端部をそれぞれ被覆する複数のゲート接続電極膜３９を含む。複数のゲート接続電極膜３９は、具体的には、主面絶縁膜１６の上に配置されている。複数のゲート接続電極膜３９は、複数のトレンチゲート構造２０の内方部、複数の第１トレンチソース構造２５および複数の第２トレンチソース構造３０から間隔を空けて対応するトレンチゲート構造２０の端部をそれぞれ被覆している。 The semiconductor device 1 includes a plurality of gate connection electrode films 39 that cover the ends of the plurality of trench gate structures 20 on the first main surface 3 (active surface 8) in the active region 12. Specifically, the plurality of gate connection electrode films 39 are disposed on the main surface insulating film 16. The plurality of gate connection electrode films 39 cover the inner portions of the plurality of trench gate structures 20 and the ends of the corresponding trench gate structures 20 at intervals from the plurality of first trench source structures 25 and the plurality of second trench source structures 30.
　複数のゲート接続電極膜３９は、平面視において第２方向Ｙに複数の第１トレンチソース構造２５と交互に配列されている。複数のゲート接続電極膜３９は、この形態では、第１方向Ｘに延びる帯状にそれぞれ形成されている。複数のゲート接続電極膜３９は、平面視において第２方向Ｙに複数の第２トレンチソース構造３０に対向していない。以下、１つのゲート接続電極膜３９が説明される。 The multiple gate connection electrode films 39 are arranged alternately with the multiple first trench source structures 25 in the second direction Y in a planar view. In this embodiment, the multiple gate connection electrode films 39 are each formed in a strip shape extending in the first direction X. The multiple gate connection electrode films 39 do not face the multiple second trench source structures 30 in the second direction Y in a planar view. Below, one gate connection electrode film 39 will be described.
　ゲート接続電極膜３９は、対応するトレンチゲート構造２０を被覆する部分において対応するゲート埋設電極２３に接続されている。ゲート接続電極膜３９は、この形態では、対応するゲート埋設電極２３と一体的に形成されている。つまり、ゲート接続電極膜３９は、ゲート埋設電極２３の一部が活性面８（主面絶縁膜１６）の上に膜状に引き出された部分からなる。むろん、ゲート接続電極膜３９は、ゲート埋設電極２３とは別体的に形成されていてもよい。 The gate connection electrode film 39 is connected to the corresponding gate buried electrode 23 in the portion covering the corresponding trench gate structure 20. In this embodiment, the gate connection electrode film 39 is formed integrally with the corresponding gate buried electrode 23. In other words, the gate connection electrode film 39 is made up of a portion of the gate buried electrode 23 that is pulled out in the form of a film onto the active surface 8 (main surface insulating film 16). Of course, the gate connection electrode film 39 may be formed separately from the gate buried electrode 23.
　ゲート接続電極膜３９は、活性面８に沿って延びる電極面３９ａを有している。ゲート接続電極膜３９は、この形態では、断面視において活性面８から電極面３９ａに向けて先細り形状（四角錐台状）に形成されている。電極面３９ａは、第２方向Ｙに関してトレンチゲート構造２０よりも幅広に形成されていることが好ましい。つまり、電極面３９ａは、法線方向Ｚにトレンチゲート構造２０に対向する部分、および、法線方向Ｚにトレンチゲート構造２０外の領域（つまり主面絶縁膜１６）に対向する部分を有していることが好ましい。 The gate connection electrode film 39 has an electrode surface 39a extending along the active surface 8. In this embodiment, the gate connection electrode film 39 is formed in a tapered shape (quadratic pyramid shape) from the active surface 8 towards the electrode surface 39a in a cross-sectional view. The electrode surface 39a is preferably formed to be wider than the trench gate structure 20 in the second direction Y. In other words, the electrode surface 39a preferably has a portion facing the trench gate structure 20 in the normal direction Z, and a portion facing the area outside the trench gate structure 20 (i.e., the main surface insulating film 16) in the normal direction Z.
　ゲート接続電極膜３９は、この形態では、導電性ポリシリコンを含む。ゲート接続電極膜３９は、電極厚さＴＥを有している。電極厚さＴＥは、トレンチゲート構造２０の第１幅Ｗ１（第１トレンチソース構造２５の第２幅Ｗ２）の０．５倍以上であることが好ましい。電極厚さＴＥは、外周面９の外周深さＤＯ以下であることが好ましい。電極厚さＴＥは、第１トレンチソース構造２５の第２深さＤ２以下であることが好ましい。電極厚さＴＥは、第２深さＤ２（外周深さＤＯ）未満であること特に好ましい。 In this embodiment, the gate connection electrode film 39 includes conductive polysilicon. The gate connection electrode film 39 has an electrode thickness TE. The electrode thickness TE is preferably 0.5 times or more the first width W1 of the trench gate structure 20 (the second width W2 of the first trench source structure 25). The electrode thickness TE is preferably equal to or less than the peripheral depth DO of the peripheral surface 9. The electrode thickness TE is preferably equal to or less than the second depth D2 of the first trench source structure 25. It is particularly preferable that the electrode thickness TE is less than the second depth D2 (peripheral depth DO).
　電極厚さＴＥは、トレンチゲート構造２０の第１深さＤ１以下であることが好ましい。電極厚さＴＥは、第１深さＤ１未満であることが特に好ましい。電極厚さＴＥは、０．０５μｍ以上２．５μｍ以下であってもよい。電極厚さＴＥは、０．５μｍ以上１．５μｍ以下であることが好ましい。むろん、電極厚さＴＥは、第１深さＤ１よりも大きくてもよい。また、電極厚さＴＥは、外周深さＤＯ（第２深さＤ２）以上であってもよい。 The electrode thickness TE is preferably equal to or less than the first depth D1 of the trench gate structure 20. It is particularly preferable that the electrode thickness TE is less than the first depth D1. The electrode thickness TE may be 0.05 μm or more and 2.5 μm or less. It is preferable that the electrode thickness TE is 0.5 μm or more and 1.5 μm or less. Of course, the electrode thickness TE may be greater than the first depth D1. Also, the electrode thickness TE may be greater than the outer periphery depth DO (second depth D2).
　図１３は、終端領域１５（第１終端領域１５Ａ）のレイアウトを示す拡大平面図である。図１４は、ゲート抵抗４０のレイアウトを示す拡大平面図である。図１５は、ゲート抵抗４０の内方部を示す拡大平面図である。図１６は、ゲート抵抗４０の周縁部を示す拡大平面図である。 FIG. 13 is an enlarged plan view showing the layout of the termination region 15 (first termination region 15A). FIG. 14 is an enlarged plan view showing the layout of the gate resistor 40. FIG. 15 is an enlarged plan view showing the inner part of the gate resistor 40. FIG. 16 is an enlarged plan view showing the peripheral part of the gate resistor 40.
　図１７は、図１５に示すXVII-XVII線に沿う断面図である。図１８は、図１５に示すXVIII-XVIII線に沿う断面図である。図１９は、図１６に示すXIX-XIX線に沿う断面図である。図２０は、図１６に示すXX-XX線に沿う断面図である。図２１は、図１６に示すXXI-XXI線に沿う断面図である。図２２は、図１６に示すXXII-XXII線に沿う断面図である。図２３は、ゲート抵抗４０の一要部を示す拡大平面図である。 FIG. 17 is a cross-sectional view taken along line XVII-XVII shown in FIG. 15. FIG. 18 is a cross-sectional view taken along line XVIII-XVIII shown in FIG. 15. FIG. 19 is a cross-sectional view taken along line XIX-XIX shown in FIG. 16. FIG. 20 is a cross-sectional view taken along line XX-XX shown in FIG. 16. FIG. 21 is a cross-sectional view taken along line XXI-XXI shown in FIG. 16. FIG. 22 is a cross-sectional view taken along line XXII-XXII shown in FIG. 16. FIG. 23 is an enlarged plan view showing a main portion of gate resistor 40.
　図１３～図２３を参照して、半導体装置１は、第１終端領域１５Ａにおいて第１主面３（活性面８）に形成されたゲート抵抗４０を含む。ゲート抵抗４０は、ＭＩＳＦＥＴのゲート（トレンチゲート構造２０）に電気的に接続される抵抗としてチップ２（第１終端領域１５Ａ）に組み込まれている。 Referring to Figures 13 to 23, the semiconductor device 1 includes a gate resistor 40 formed on the first main surface 3 (active surface 8) in the first termination region 15A. The gate resistor 40 is incorporated in the chip 2 (first termination region 15A) as a resistor electrically connected to the gate (trench gate structure 20) of the MISFET.
　ゲート抵抗４０は、活性領域１２に対して第１側面５Ａ側（第１接続面１０Ａ側）の領域に配置され、第２方向Ｙに活性領域１２に対向している。ゲート抵抗４０は、第２方向Ｙに周縁領域１４に対向しないように周縁領域１４から第１方向Ｘに間隔を空けて配置されている。ゲート抵抗４０は、この形態では、第１側面５Ａ（第１接続面１０Ａ）の中央部および活性領域１２の間に配置されている。 The gate resistor 40 is disposed in a region on the first side surface 5A side (first connection surface 10A side) of the active region 12, and faces the active region 12 in the second direction Y. The gate resistor 40 is disposed at a distance from the peripheral region 14 in the first direction X so as not to face the peripheral region 14 in the second direction Y. In this embodiment, the gate resistor 40 is disposed between the center of the first side surface 5A (first connection surface 10A) and the active region 12.
　ゲート抵抗４０は、第１終端領域１５Ａにおいて第１主面３（活性面８）に形成された少なくとも１つ（この形態では複数）のトレンチ抵抗構造４１を含む。複数のトレンチ抵抗構造４１には、第１電位としてのゲート電位ＶＧが付与されるが、チャネルの制御には寄与しない。 The gate resistor 40 includes at least one (in this embodiment, multiple) trench resistor structures 41 formed on the first main surface 3 (active surface 8) in the first termination region 15A. A gate potential VG is applied as a first potential to the multiple trench resistor structures 41, but they do not contribute to channel control.
　複数のトレンチ抵抗構造４１は、第１方向Ｘに延びる帯状にそれぞれ形成され、第２方向Ｙに間隔を空けて配列されている。複数のトレンチ抵抗構造４１は、第１半導体領域６に至るようにボディ領域１７を貫通している。複数のトレンチ抵抗構造４１は、第１半導体領域６の底部から活性面８側に間隔を空けて形成されている。 The multiple trench resistance structures 41 are each formed in a band shape extending in the first direction X, and are arranged at intervals in the second direction Y. The multiple trench resistance structures 41 penetrate the body region 17 to reach the first semiconductor region 6. The multiple trench resistance structures 41 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.
　複数のトレンチ抵抗構造４１は、この形態では、複数の第１トレンチ抵抗構造４２および複数の第２トレンチ抵抗構造４３を含む。複数の第１トレンチ抵抗構造４２は、第１終端領域１５Ａにおいて活性面８の周縁から間隔を空けて活性面８に形成されている。複数の第１トレンチ抵抗構造４２は、第１方向Ｘに延びる帯状にそれぞれ形成され、第２方向Ｙに間隔を空けて配列されている。 In this embodiment, the multiple trench resistance structures 41 include multiple first trench resistance structures 42 and multiple second trench resistance structures 43. The multiple first trench resistance structures 42 are formed on the active surface 8 at intervals from the periphery of the active surface 8 in the first termination region 15A. The multiple first trench resistance structures 42 are each formed in a band shape extending in the first direction X, and are arranged at intervals in the second direction Y.
　複数の第１トレンチ抵抗構造４２は、第２方向Ｙに第１トレンチソース構造２５に対向している。複数の第１トレンチ抵抗構造４２は、第２方向Ｙに第２トレンチソース構造３０に対向しないように第２トレンチソース構造３０から第１方向Ｘに間隔を空けて配置されている。複数の第１トレンチ抵抗構造４２は、第１半導体領域６に至るようにボディ領域１７を貫通している。複数の第１トレンチ抵抗構造４２は、第１半導体領域６の底部から活性面８側に間隔を空けて形成されている。 The multiple first trench resistance structures 42 face the first trench source structure 25 in the second direction Y. The multiple first trench resistance structures 42 are arranged at intervals from the second trench source structure 30 in the first direction X so as not to face the second trench source structure 30 in the second direction Y. The multiple first trench resistance structures 42 penetrate the body region 17 to reach the first semiconductor region 6. The multiple first trench resistance structures 42 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.
　以下、１つの第１トレンチ抵抗構造４２が説明される。第１トレンチ抵抗構造４２は、第１方向Ｘに第１抵抗長Ｌ１を有している。第１抵抗長Ｌ１は、任意であり、達成すべき抵抗値に応じて適宜徴される。第１トレンチ抵抗構造４２は、第２方向Ｙに第４幅Ｗ４を有し、法線方向Ｚに第４深さＤ４を有している。第４幅Ｗ４は、トレンチゲート構造２０の第１幅Ｗ１とほぼ等しいことが好ましい。第４幅Ｗ４は、０．１μｍ以上３μｍ以下であってもよい。第４幅Ｗ４は、０．５μｍ以上２μｍ以下であることが好ましい。 Below, one first trench resistor structure 42 will be described. The first trench resistor structure 42 has a first resistor length L1 in the first direction X. The first resistor length L1 is arbitrary and is appropriately determined according to the resistance value to be achieved. The first trench resistor structure 42 has a fourth width W4 in the second direction Y and a fourth depth D4 in the normal direction Z. It is preferable that the fourth width W4 is approximately equal to the first width W1 of the trench gate structure 20. The fourth width W4 may be 0.1 μm or more and 3 μm or less. It is preferable that the fourth width W4 is 0.5 μm or more and 2 μm or less.
　第４深さＤ４は、第１トレンチソース構造２５の第２深さＤ２未満である。第４深さＤ４は、外周面９の外周深さＤＯ未満である。第４深さＤ４は、トレンチゲート構造２０の第１深さＤ１とほぼ等しいことが好ましい。第４深さＤ４は、０．１μｍ以上３μｍ以下であってもよい。第４深さＤ４は、０．５μｍ以上１．５μｍ以下であることが好ましい。 The fourth depth D4 is less than the second depth D2 of the first trench source structure 25. The fourth depth D4 is less than the outer circumferential depth DO of the outer circumferential surface 9. It is preferable that the fourth depth D4 is approximately equal to the first depth D1 of the trench gate structure 20. The fourth depth D4 may be greater than or equal to 0.1 μm and less than or equal to 3 μm. It is preferable that the fourth depth D4 is greater than or equal to 0.5 μm and less than or equal to 1.5 μm.
　活性領域１２側の最内の第１トレンチ抵抗構造４２は、この形態では、第２方向Ｙに最外の第１トレンチソース構造２５に隣り合うように最外の第１トレンチソース構造２５から前述の第１間隔Ｉ１を空けて配置されている。最内の第１トレンチ抵抗構造４２は、この形態では、第２方向Ｙに最外の第２トレンチソース構造３０に隣り合わないように最外の第２トレンチソース構造３０から第１方向Ｘに間隔を空けて配置されている。 In this embodiment, the innermost first trench resistance structure 42 on the active region 12 side is disposed at the aforementioned first interval I1 from the outermost first trench source structure 25 so as to be adjacent to the outermost first trench source structure 25 in the second direction Y. In this embodiment, the innermost first trench resistance structure 42 is disposed at an interval in the first direction X from the outermost second trench source structure 30 so as not to be adjacent to the outermost second trench source structure 30 in the second direction Y.
　第１トレンチ抵抗構造４２は、第１トレンチ４４、第１絶縁膜４５および第１埋設電極４６を含む。第１埋設電極４６は、「第１埋設抵抗」と称されてもよい。第１トレンチ４４は、活性面８に形成され、第１トレンチ抵抗構造４２の壁面を区画している。第１絶縁膜４５は、第１トレンチ４４の壁面を被覆し、活性面８において主面絶縁膜１６に接続されている。第１絶縁膜４５は、酸化シリコン膜、窒化シリコン膜および酸窒化シリコン膜のうちの少なくとも１つを含んでいてもよい。 The first trench resistance structure 42 includes a first trench 44, a first insulating film 45, and a first buried electrode 46. The first buried electrode 46 may be referred to as a "first buried resistor." The first trench 44 is formed in the active surface 8 and defines the wall surface of the first trench resistance structure 42. The first insulating film 45 covers the wall surface of the first trench 44 and is connected to the main surface insulating film 16 at the active surface 8. The first insulating film 45 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
　第１絶縁膜４５は、この形態では、酸化シリコン膜からなる単層構造を有している。第１絶縁膜４５は、チップ２の酸化物からなる酸化シリコン膜を含むことが特に好ましい。第１埋設電極４６は、第１絶縁膜４５を挟んで第１トレンチ４４に埋設されている。第１埋設電極４６は、導電性ポリシリコンを含んでいてもよい。 In this embodiment, the first insulating film 45 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the first insulating film 45 includes a silicon oxide film made of an oxide of the chip 2. The first buried electrode 46 is buried in the first trench 44 with the first insulating film 45 in between. The first buried electrode 46 may include conductive polysilicon.
　複数の第２トレンチ抵抗構造４３は、第１終端領域１５Ａにおいて活性面８の周縁から間隔を空けて活性面８に形成されている。複数の第２トレンチ抵抗構造４３は、隣り合う２つの第１トレンチ抵抗構造４２の間の領域にそれぞれ配置されている。複数の第２トレンチ抵抗構造４３は、第２方向Ｙに複数の第１トレンチ抵抗構造４２と交互に配列されている。複数の第２トレンチ抵抗構造４３は、平面視において第１方向Ｘに延びる帯状にそれぞれ形成されている。 The multiple second trench resistance structures 43 are formed on the active surface 8 at intervals from the periphery of the active surface 8 in the first termination region 15A. The multiple second trench resistance structures 43 are each disposed in a region between two adjacent first trench resistance structures 42. The multiple second trench resistance structures 43 are arranged alternately with the multiple first trench resistance structures 42 in the second direction Y. The multiple second trench resistance structures 43 are each formed in a band shape extending in the first direction X in a plan view.
　複数の第２トレンチ抵抗構造４３は、第２方向Ｙにトレンチゲート構造２０および第１トレンチソース構造２５に対向している。複数の第２トレンチ抵抗構造４３は、第２方向Ｙに第２トレンチソース構造３０に対向しないように第２トレンチソース構造３０から第１方向Ｘに間隔を空けて配置されている。複数の第２トレンチ抵抗構造４３は、第１半導体領域６に至るようにボディ領域１７を貫通している。複数の第２トレンチ抵抗構造４３は、第１半導体領域６の底部から活性面８側に間隔を空けて形成されている。 The multiple second trench resistance structures 43 face the trench gate structure 20 and the first trench source structure 25 in the second direction Y. The multiple second trench resistance structures 43 are arranged at intervals from the second trench source structure 30 in the first direction X so as not to face the second trench source structure 30 in the second direction Y. The multiple second trench resistance structures 43 penetrate the body region 17 to reach the first semiconductor region 6. The multiple second trench resistance structures 43 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.
　以下、１つの第２トレンチ抵抗構造４３が説明される。第２トレンチ抵抗構造４３は、第１方向Ｘに第２抵抗長Ｌ２を有している。第２抵抗長Ｌ２は、任意であり、達成すべき抵抗値に応じて適宜徴される。第２抵抗長Ｌ２は、この形態では、第１トレンチ抵抗構造４２の第１抵抗長Ｌ１未満である。つまり、第２トレンチ抵抗構造４３の両端部は、第１トレンチ抵抗構造４２の両端部よりも内方にセットバックされている。むろん、第２抵抗長Ｌ２は、第１抵抗長Ｌ１とほぼ等しくてもよい。また、第２抵抗長Ｌ２は、第１抵抗長Ｌ１よりも大きくてもよい。 Below, one second trench resistance structure 43 will be described. The second trench resistance structure 43 has a second resistance length L2 in the first direction X. The second resistance length L2 is arbitrary and is appropriately determined according to the resistance value to be achieved. In this embodiment, the second resistance length L2 is less than the first resistance length L1 of the first trench resistance structure 42. In other words, both ends of the second trench resistance structure 43 are set back inward from both ends of the first trench resistance structure 42. Of course, the second resistance length L2 may be approximately equal to the first resistance length L1. Also, the second resistance length L2 may be greater than the first resistance length L1.
　第２トレンチ抵抗構造４３は、第２方向Ｙに第５幅Ｗ５を有し、法線方向Ｚに第５深さＤ５を有している。第５幅Ｗ５は、第１トレンチ抵抗構造４２の第４幅Ｗ４とほぼ等しいことが好ましい。第５幅Ｗ５は、第１トレンチソース構造２５の第２幅Ｗ２（トレンチゲート構造２０の第１幅Ｗ１）とほぼ等しいことが好ましい。第５幅Ｗ５は、０．１μｍ以上３μｍ以下であってもよい。第５幅Ｗ５は、０．５μｍ以上２μｍ以下であることが好ましい。 The second trench resistor structure 43 has a fifth width W5 in the second direction Y and a fifth depth D5 in the normal direction Z. The fifth width W5 is preferably approximately equal to the fourth width W4 of the first trench resistor structure 42. The fifth width W5 is preferably approximately equal to the second width W2 of the first trench source structure 25 (the first width W1 of the trench gate structure 20). The fifth width W5 may be 0.1 μm or more and 3 μm or less. The fifth width W5 is preferably 0.5 μm or more and 2 μm or less.
　第５深さＤ５は、第１トレンチ抵抗構造４２の第４深さＤ４（トレンチゲート構造２０の第１深さＤ１）以上である。第５深さＤ５は、この形態では、第４深さＤ４（第１深さＤ１）よりも大きい。第５深さＤ５は、第４深さＤ４（第１深さＤ１）の１．５倍以上３倍以下であることが好ましい。第５深さＤ５は、第１トレンチソース構造２５の第２深さＤ２とほぼ等しいことが好ましい。第５深さＤ５は、外周面９の外周深さＤＯとほぼ等しい。第５深さＤ５は、０．５μｍ以上５μｍ以下であってもよい。第５深さＤ５は、２．５μｍ以下であることが特に好ましい。 The fifth depth D5 is equal to or greater than the fourth depth D4 of the first trench resistor structure 42 (the first depth D1 of the trench gate structure 20). In this embodiment, the fifth depth D5 is greater than the fourth depth D4 (the first depth D1). The fifth depth D5 is preferably equal to or greater than 1.5 times and equal to or less than 3 times the fourth depth D4 (the first depth D1). The fifth depth D5 is preferably approximately equal to the second depth D2 of the first trench source structure 25. The fifth depth D5 is approximately equal to the outer circumferential depth DO of the outer circumferential surface 9. The fifth depth D5 may be equal to or greater than 0.5 μm and equal to or less than 5 μm. It is particularly preferable that the fifth depth D5 is equal to or less than 2.5 μm.
　第２トレンチ抵抗構造４３は、第２方向Ｙに第１トレンチ抵抗構造４２から第４間隔Ｉ４を空けて配置されている。第４間隔Ｉ４は、第４幅Ｗ４（第５幅Ｗ５）の０．５倍以上２倍以下であることが好ましい。第４間隔Ｉ４は、第４幅Ｗ４（第５幅Ｗ５）未満であることが特に好ましい。第４間隔Ｉ４は、トレンチゲート構造２０および第１トレンチソース構造２５の間の第１間隔Ｉ１とほぼ等しいことが好ましい。第４間隔Ｉ４は、０．１μｍ以上２．５μｍ以下であってもよい。第４間隔Ｉ４は、０．５μｍ以上１．５μｍ以下であることが好ましい。 The second trench resistance structure 43 is disposed in the second direction Y at a fourth interval I4 from the first trench resistance structure 42. The fourth interval I4 is preferably 0.5 to 2 times the fourth width W4 (fifth width W5). It is particularly preferable that the fourth interval I4 is less than the fourth width W4 (fifth width W5). It is preferable that the fourth interval I4 is approximately equal to the first interval I1 between the trench gate structure 20 and the first trench source structure 25. The fourth interval I4 may be 0.1 μm to 2.5 μm. It is preferable that the fourth interval I4 is 0.5 μm to 1.5 μm.
　第２トレンチ抵抗構造４３は、第２トレンチ４７、第２絶縁膜４８および第２埋設電極４９を含む。第２埋設電極４９は、「第２埋設抵抗」と称されてもよい。第２トレンチ４７は、活性面８に形成され、第２トレンチ抵抗構造４３の壁面を区画している。第２絶縁膜４８は、第２トレンチ４７の壁面を被覆し、活性面８において主面絶縁膜１６に接続されている。第２絶縁膜４８は、酸化シリコン膜、窒化シリコン膜および酸窒化シリコン膜のうちの少なくとも１つを含んでいてもよい。 The second trench resistance structure 43 includes a second trench 47, a second insulating film 48, and a second buried electrode 49. The second buried electrode 49 may be referred to as a "second buried resistor." The second trench 47 is formed in the active surface 8 and defines the wall surface of the second trench resistance structure 43. The second insulating film 48 covers the wall surface of the second trench 47 and is connected to the main surface insulating film 16 at the active surface 8. The second insulating film 48 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
　第２絶縁膜４８は、この形態では、酸化シリコン膜からなる単層構造を有している。第２絶縁膜４８は、チップ２の酸化物からなる酸化シリコン膜を含むことが特に好ましい。第２埋設電極４９は、第２絶縁膜４８を挟んで第２トレンチ４７に埋設されている。第２埋設電極４９は、導電性ポリシリコンを含んでいてもよい。 In this embodiment, the second insulating film 48 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the second insulating film 48 includes a silicon oxide film made of an oxide of the chip 2. The second buried electrode 49 is buried in the second trench 47 with the second insulating film 48 in between. The second buried electrode 49 may include conductive polysilicon.
　ゲート抵抗４０は、第１主面３（活性面８）の上において、少なくとも１つ（この形態では複数）のトレンチ抵抗構造４１を、被覆する抵抗膜５０を含む。抵抗膜５０は、導電性ポリシリコン膜および合金結晶膜のうちの少なくとも１つを含む。合金結晶膜は、金属元素および非金属元素によって構成された合金結晶を含む。合金結晶膜は、ＣｒＳｉ膜、ＣｒＳｉＮ膜、ＣｒＳｉＯ膜、ＴａＮ膜およびＴｉＮ膜のうちの少なくとも１つを含んでいてもよい。抵抗膜５０は、この形態では、導電性ポリシリコンを含む。 The gate resistor 40 includes a resistive film 50 covering at least one (in this embodiment, multiple) trench resistor structures 41 on the first main surface 3 (active surface 8). The resistive film 50 includes at least one of a conductive polysilicon film and an alloy crystal film. The alloy crystal film includes alloy crystals composed of a metal element and a nonmetal element. The alloy crystal film may include at least one of a CrSi film, a CrSiN film, a CrSiO film, a TaN film, and a TiN film. In this embodiment, the resistive film 50 includes conductive polysilicon.
　抵抗膜５０は、主面絶縁膜１６の上に配置され、活性面８を被覆する部分および複数のトレンチ抵抗構造４１を被覆する部分を有している。抵抗膜５０は、この形態では、複数のトレンチ抵抗構造４１の短手方向（第２方向Ｙ）に関して全てのトレンチ抵抗構造４１を被覆している。抵抗膜５０は、複数のトレンチ抵抗構造４１を被覆する部分において第１埋設電極４６および第２埋設電極４９に接続されている。 The resistive film 50 is disposed on the main surface insulating film 16, and has a portion covering the active surface 8 and a portion covering the multiple trench resistance structures 41. In this form, the resistive film 50 covers all of the multiple trench resistance structures 41 in the short direction (second direction Y) of the multiple trench resistance structures 41. The resistive film 50 is connected to the first buried electrode 46 and the second buried electrode 49 in the portion covering the multiple trench resistance structures 41.
　抵抗膜５０は、この形態では、第１埋設電極４６および第２埋設電極４９と一体的に形成されている。つまり、抵抗膜５０は、第１埋設電極４６の一部および第２埋設電極４９の一部が活性面８（主面絶縁膜１６）の上に膜状に引き出された部分からなる。むろん、抵抗膜５０は、第１埋設電極４６および第２埋設電極４９とは別体的に形成されていてもよい。 In this embodiment, the resistive film 50 is formed integrally with the first buried electrode 46 and the second buried electrode 49. In other words, the resistive film 50 is made up of a portion of the first buried electrode 46 and a portion of the second buried electrode 49 that are pulled out in a film shape onto the active surface 8 (main surface insulating film 16). Of course, the resistive film 50 may be formed separately from the first buried electrode 46 and the second buried electrode 49.
　抵抗膜５０は、第２方向Ｙにトレンチゲート構造２０および第１トレンチソース構造２５に対向している。抵抗膜５０は、第２方向Ｙに第２トレンチソース構造３０に対向しないように第２トレンチソース構造３０から第１方向Ｘに間隔を空けて配置されている。抵抗膜５０は、この形態では、平面視において第１方向Ｘに延びる帯状に形成されている。抵抗膜５０の平面形状は任意であり、達成すべき抵抗値に応じて適宜調整される。 The resistive film 50 faces the trench gate structure 20 and the first trench source structure 25 in the second direction Y. The resistive film 50 is spaced apart from the second trench source structure 30 in the first direction X so as not to face the second trench source structure 30 in the second direction Y. In this embodiment, the resistive film 50 is formed in a band shape extending in the first direction X in a plan view. The planar shape of the resistive film 50 is arbitrary and is adjusted appropriately according to the resistance value to be achieved.
　抵抗膜５０は、第１方向Ｘに第１トレンチ抵抗構造４２の第１抵抗長Ｌ１および第２トレンチ抵抗構造４３の第２抵抗長Ｌ２よりも短い第３抵抗長Ｌ３を有していることが好ましい。この場合、抵抗膜５０は、複数のトレンチ抵抗構造４１の長手方向（第１方向Ｘ）に関して、複数のトレンチ抵抗構造４１の両端部から内方に間隔を空けて複数のトレンチ抵抗構造４１の内方部を被覆していることが好ましい。つまり、抵抗膜５０は、複数の第１トレンチ抵抗構造４２の両端部および複数の第２トレンチ抵抗構造４３の両端部を露出させていることが好ましい。 The resistive film 50 preferably has a third resistance length L3 in the first direction X that is shorter than the first resistance length L1 of the first trench resistance structure 42 and the second resistance length L2 of the second trench resistance structure 43. In this case, the resistive film 50 preferably covers the inner portions of the multiple trench resistance structures 41 with a gap inward from both ends of the multiple trench resistance structures 41 in the longitudinal direction (first direction X) of the multiple trench resistance structures 41. In other words, the resistive film 50 preferably exposes both ends of the multiple first trench resistance structures 42 and both ends of the multiple second trench resistance structures 43.
　抵抗膜５０を複数のトレンチ抵抗構造４１の両端部に対して内方側にセットバックさせることにより、複数のトレンチ抵抗構造４１の両端部よりも活性面８の周縁側の領域において抵抗膜５０が第１主面３に対向することを抑制できる。したがって、複数のトレンチ抵抗構造４１の両端部外の領域において、第１主面３および抵抗膜５０の間に不所望な電位差（電界）が形成されることが抑制される。 By setting back the resistive film 50 inward from both ends of the multiple trench resistance structures 41, it is possible to prevent the resistive film 50 from facing the first main surface 3 in the area closer to the periphery of the active surface 8 than both ends of the multiple trench resistance structures 41. Therefore, in the area outside both ends of the multiple trench resistance structures 41, the formation of an undesirable potential difference (electric field) between the first main surface 3 and the resistive film 50 is prevented.
　むろん、抵抗膜５０は、複数のトレンチ抵抗構造４１の全域を被覆していてもよい。つまり、第３抵抗長Ｌ３は、第１抵抗長Ｌ１よりも大きくてもよい。また、抵抗膜５０は、複数の第１トレンチ抵抗構造４２の両端部を露出させ、複数の第２トレンチ抵抗構造４３の両端部を被覆していてもよい。つまり、第３抵抗長Ｌ３は、第１抵抗長Ｌ１よりも小さく、第２抵抗長Ｌ２よりも大きくてもよい。 Of course, the resistive film 50 may cover the entire area of the multiple trench resistance structures 41. That is, the third resistance length L3 may be greater than the first resistance length L1. The resistive film 50 may also expose both ends of the multiple first trench resistance structures 42 and cover both ends of the multiple second trench resistance structures 43. That is, the third resistance length L3 may be smaller than the first resistance length L1 and greater than the second resistance length L2.
　抵抗膜５０は、法線方向Ｚに抵抗厚さＴＲを有している。抵抗厚さＴＲは、達成すべき抵抗値に応じて適宜調整される。つまり、抵抗膜５０の抵抗値は、抵抗厚さＴＲの増減および第３抵抗長Ｌ３の増減によって調節される。抵抗厚さＴＲは、前述の第４幅Ｗ４（第５幅Ｗ５）の０．５倍以上であることが好ましい。 The resistive film 50 has a resistive thickness TR in the normal direction Z. The resistive thickness TR is adjusted as appropriate according to the resistance value to be achieved. In other words, the resistance value of the resistive film 50 is adjusted by increasing or decreasing the resistive thickness TR and increasing or decreasing the third resistive length L3. It is preferable that the resistive thickness TR be 0.5 or more times the aforementioned fourth width W4 (fifth width W5).
　この条件を満たす抵抗厚さＴＲによれば、ＣＶＤ法によって第１トレンチ４４および第２トレンチ４７を埋めて第１主面３（活性面８）を被覆する導電性ポリシリコン膜を形成する場合、当該導電性ポリシリコン膜の一部を利用して第１埋設電極４６、第２埋設電極４９および抵抗膜５０を形成できる。抵抗厚さＴＲは、前述の外周深さＤＯ以下であることが好ましい。抵抗厚さＴＲは、前述の第５深さＤ５（前述の第２深さＤ２）以下であることが好ましい。 If the resistor thickness TR satisfies this condition, when a conductive polysilicon film is formed by CVD to fill the first trench 44 and the second trench 47 and cover the first main surface 3 (active surface 8), the first buried electrode 46, the second buried electrode 49, and the resistor film 50 can be formed using a portion of the conductive polysilicon film. It is preferable that the resistor thickness TR is equal to or less than the aforementioned outer periphery depth DO. It is preferable that the resistor thickness TR is equal to or less than the aforementioned fifth depth D5 (the aforementioned second depth D2).
　抵抗厚さＴＲは、第５深さＤ５未満であること特に好ましい。抵抗厚さＴＲは、前述の第４深さＤ４（第１深さＤ１）以下であることが好ましい。抵抗厚さＴＲは、第４深さＤ４未満であることが特に好ましい。抵抗厚さＴＲは、前述の電極厚さＴＥとほぼ等しいことが好ましい。抵抗厚さＴＲは、０．０５μｍ以上２．５μｍ以下であってもよい。抵抗厚さＴＲは、０．５μｍ以上１．５μｍ以下であることが好ましい。 It is particularly preferred that the resistor thickness TR is less than the fifth depth D5. It is preferred that the resistor thickness TR is less than the aforementioned fourth depth D4 (first depth D1). It is particularly preferred that the resistor thickness TR is less than the fourth depth D4. It is preferred that the resistor thickness TR is approximately equal to the aforementioned electrode thickness TE. The resistor thickness TR may be 0.05 μm or more and 2.5 μm or less. It is preferred that the resistor thickness TR is 0.5 μm or more and 1.5 μm or less.
　むろん、抵抗厚さＴＲは、第４深さＤ４よりも大きくてもよい。また、抵抗厚さＴＲは、外周深さＤＯ（第５深さＤ５）以上であってもよい。また、抵抗膜５０が合金結晶膜からなる場合、抵抗厚さＴＲは第４深さＤ４未満であってもよい。この場合、抵抗厚さＴＲは、０．１ｎｍ以上１００ｎｍであってもよい。 Of course, the resistor thickness TR may be greater than the fourth depth D4. Also, the resistor thickness TR may be greater than or equal to the outer circumferential depth DO (fifth depth D5). Also, when the resistor film 50 is made of an alloy crystal film, the resistor thickness TR may be less than the fourth depth D4. In this case, the resistor thickness TR may be greater than or equal to 0.1 nm and less than or equal to 100 nm.
　図１３～図２３を参照して、半導体装置１は、第１終端領域１５Ａにおいて第１主面３（活性面８）に形成されたダミー構造５５を含む。ダミー構造５５は、ゲート抵抗４０の近傍における局所的な電界集中を緩和し、耐圧（たとえばブレークダウン電圧）を向上させることを１つの目的として活性面８（第１終端領域１５Ａ）に組み込まれている。ダミー構造５５の有無は任意であり、ダミー構造５５を備えない形態が採用されてもよい。 Referring to Figures 13 to 23, the semiconductor device 1 includes a dummy structure 55 formed on the first main surface 3 (active surface 8) in the first termination region 15A. The dummy structure 55 is incorporated in the active surface 8 (first termination region 15A) for one purpose, which is to reduce localized electric field concentration in the vicinity of the gate resistor 40 and improve the breakdown voltage (e.g., breakdown voltage). The presence or absence of the dummy structure 55 is optional, and a configuration without the dummy structure 55 may be adopted.
　ダミー構造５５は、第１ダミー構造５６および第２ダミー構造５７を含む。第１ダミー構造５６は、ゲート抵抗４０に対して第３側面５Ｃ側（第３接続面１０Ｃ側）の領域に配置されている。第１ダミー構造５６は、第１方向Ｘにゲート抵抗４０に対向し、第２方向Ｙに活性領域１２および第１周縁領域１４Ａに対向している。第２ダミー構造５７は、ゲート抵抗４０に対して第４側面５Ｄ側（第４接続面１０Ｄ側）の領域に配置されている。 The dummy structure 55 includes a first dummy structure 56 and a second dummy structure 57. The first dummy structure 56 is arranged in a region on the third side surface 5C side (third connection surface 10C side) of the gate resistor 40. The first dummy structure 56 faces the gate resistor 40 in the first direction X, and faces the active region 12 and the first peripheral region 14A in the second direction Y. The second dummy structure 57 is arranged in a region on the fourth side surface 5D side (fourth connection surface 10D side) of the gate resistor 40.
　第２ダミー構造５７は、第１方向Ｘにゲート抵抗４０を挟んで第１ダミー構造５６に対向し、第２方向Ｙに活性領域１２および第２周縁領域１４Ｂに対向している。第２ダミー構造５７のレイアウトは第１ダミー構造５６のレイアウトとほぼ同様であるため、以下では第１ダミー構造５６の構成が説明される。第２ダミー構造５７のレイアウトは、以下の説明において「第３接続面１０Ｃ」を「第４接続面１０Ｄ」に置き換えることによって得られる。 The second dummy structure 57 faces the first dummy structure 56 across the gate resistor 40 in the first direction X, and faces the active region 12 and the second peripheral region 14B in the second direction Y. Since the layout of the second dummy structure 57 is substantially similar to the layout of the first dummy structure 56, the configuration of the first dummy structure 56 will be described below. The layout of the second dummy structure 57 can be obtained by replacing "third connection surface 10C" with "fourth connection surface 10D" in the following description.
　第１ダミー構造５６は、第１終端領域１５Ａにおいて第１主面３（活性面８）に形成された少なくとも１つ（この形態では複数）のダミートレンチ構造６０を含む。複数のダミートレンチ構造６０には、第２電位としてのソース電位ＶＳが付与される。複数のダミートレンチ構造６０は、第１方向Ｘに延びる帯状にそれぞれ形成され、第２方向Ｙに間隔を空けて配列されている。 The first dummy structure 56 includes at least one (in this embodiment, multiple) dummy trench structures 60 formed in the first main surface 3 (active surface 8) in the first termination region 15A. A source potential VS is applied to the multiple dummy trench structures 60 as a second potential. The multiple dummy trench structures 60 are each formed in a band shape extending in the first direction X, and are arranged at intervals in the second direction Y.
　複数のダミートレンチ構造６０は、第１方向Ｘに複数のトレンチ抵抗構造４１に１対１の対応関係で対向している。複数のダミートレンチ構造６０は、第２方向Ｙに第１トレンチソース構造２５および第２トレンチソース構造３０に対向している。複数のダミートレンチ構造６０は、第１半導体領域６に至るようにボディ領域１７を貫通している。複数のダミートレンチ構造６０は、この形態では、第３接続面１０Ｃを貫通し、第３接続面１０Ｃから露出している。複数のトレンチゲート構造２０は、第１半導体領域６の底部から活性面８側に間隔を空けて形成されている。 The multiple dummy trench structures 60 face the multiple trench resistor structures 41 in a one-to-one correspondence in the first direction X. The multiple dummy trench structures 60 face the first trench source structure 25 and the second trench source structure 30 in the second direction Y. The multiple dummy trench structures 60 penetrate the body region 17 to reach the first semiconductor region 6. In this embodiment, the multiple dummy trench structures 60 penetrate the third connection surface 10C and are exposed from the third connection surface 10C. The multiple trench gate structures 20 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.
　複数のダミートレンチ構造６０は、この形態では、複数の第１ダミートレンチ構造６１および複数の第２ダミートレンチ構造６２を含む。複数の第１ダミートレンチ構造６１は、活性面８の周縁および複数の第１トレンチ抵抗構造４２の間の領域に配置されている。複数の第１ダミートレンチ構造６１は、第１方向Ｘに延びる帯状にそれぞれ形成され、第２方向Ｙに間隔を空けて配列されている。 In this embodiment, the multiple dummy trench structures 60 include multiple first dummy trench structures 61 and multiple second dummy trench structures 62. The multiple first dummy trench structures 61 are arranged in the region between the periphery of the active surface 8 and the multiple first trench resistance structures 42. The multiple first dummy trench structures 61 are each formed in a band shape extending in the first direction X, and are arranged at intervals in the second direction Y.
　複数の第１ダミートレンチ構造６１は、第１方向Ｘに複数の第１トレンチ抵抗構造４２に１対１の対応関係で対向している。つまり、ゲート電位ＶＧが印加される第１トレンチ抵抗構造４２およびソース電位ＶＳが印加される第１ダミートレンチ構造６１が第１方向Ｘに対向している。複数の第１ダミートレンチ構造６１は、第２方向Ｙに第１トレンチソース構造２５および第２トレンチソース構造３０に対向している。 The multiple first dummy trench structures 61 face the multiple first trench resistance structures 42 in a one-to-one correspondence in the first direction X. In other words, the first trench resistance structure 42 to which the gate potential VG is applied and the first dummy trench structure 61 to which the source potential VS is applied face each other in the first direction X. The multiple first dummy trench structures 61 face the first trench source structure 25 and the second trench source structure 30 in the second direction Y.
　複数の第１ダミートレンチ構造６１は、この形態では、第３接続面１０Ｃを貫通し、第３接続面１０Ｃから露出している。複数の第１ダミートレンチ構造６１は、第１半導体領域６に至るようにボディ領域１７を貫通している。複数の第１ダミートレンチ構造６１は、第１半導体領域６の底部から活性面８側に間隔を空けて形成されている。 In this embodiment, the multiple first dummy trench structures 61 penetrate the third connection surface 10C and are exposed from the third connection surface 10C. The multiple first dummy trench structures 61 penetrate the body region 17 to reach the first semiconductor region 6. The multiple first dummy trench structures 61 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.
　以下、１つの第１ダミートレンチ構造６１が説明される。第１ダミートレンチ構造６１は、第２方向Ｙに第６幅Ｗ６を有し、法線方向Ｚに第６深さＤ６を有している。第６幅Ｗ６は、第１トレンチ抵抗構造４２の第４幅Ｗ４とほぼ等しいことが好ましい。第６幅Ｗ６は、トレンチゲート構造２０の第１幅Ｗ１とほぼ等しいことが好ましい。第６幅Ｗ６は、０．１μｍ以上３μｍ以下であってもよい。第６幅Ｗ６は、０．５μｍ以上２μｍ以下であることが好ましい。 Below, one first dummy trench structure 61 is described. The first dummy trench structure 61 has a sixth width W6 in the second direction Y and a sixth depth D6 in the normal direction Z. The sixth width W6 is preferably approximately equal to the fourth width W4 of the first trench resistor structure 42. The sixth width W6 is preferably approximately equal to the first width W1 of the trench gate structure 20. The sixth width W6 may be 0.1 μm or more and 3 μm or less. The sixth width W6 is preferably 0.5 μm or more and 2 μm or less.
　第６深さＤ６は、第２トレンチ抵抗構造４３の第５深さＤ５（第１トレンチソース構造２５の第２深さＤ２）未満である。第６深さＤ６は、外周面９の外周深さＤＯ未満である。第６深さＤ６は、第１トレンチ抵抗構造４２の第４深さＤ４（トレンチゲート構造２０の第１深さＤ１）とほぼ等しいことが好ましい。第６深さＤ６は、０．１μｍ以上３μｍ以下であってもよい。第６深さＤ６は、０．５μｍ以上１．５μｍ以下であることが好ましい。 The sixth depth D6 is less than the fifth depth D5 of the second trench resistance structure 43 (the second depth D2 of the first trench source structure 25). The sixth depth D6 is less than the outer circumferential depth DO of the outer circumferential surface 9. It is preferable that the sixth depth D6 is approximately equal to the fourth depth D4 of the first trench resistance structure 42 (the first depth D1 of the trench gate structure 20). The sixth depth D6 may be 0.1 μm or more and 3 μm or less. It is preferable that the sixth depth D6 is 0.5 μm or more and 1.5 μm or less.
　第１ダミートレンチ構造６１は、第１方向Ｘに第１トレンチ抵抗構造４２から第５間隔Ｉ５を空けて配置されている。第５間隔Ｉ５は、第４幅Ｗ４（第６幅Ｗ６）の０．５倍以上２倍以下であることが好ましい。第５間隔Ｉ５は、第１トレンチ抵抗構造４２および第２トレンチ抵抗構造４３の間の第４間隔Ｉ４の０．５倍以上２倍以下であることが好ましい。第５間隔Ｉ５は、第４間隔Ｉ４の１．５倍以下であることが特に好ましい。第５間隔Ｉ５は、第４間隔Ｉ４とほぼ等しくてもよい。第５間隔Ｉ５は、０．１μｍ以上２．５μｍ以下であってもよい。第５間隔Ｉ５は、０．５μｍ以上１．５μｍ以下であることが好ましい。 The first dummy trench structure 61 is disposed in the first direction X at a fifth interval I5 from the first trench resistance structure 42. The fifth interval I5 is preferably 0.5 to 2 times the fourth width W4 (sixth width W6). The fifth interval I5 is preferably 0.5 to 2 times the fourth interval I4 between the first trench resistance structure 42 and the second trench resistance structure 43. It is particularly preferable that the fifth interval I5 is 1.5 times or less than the fourth interval I4. The fifth interval I5 may be approximately equal to the fourth interval I4. The fifth interval I5 may be 0.1 μm to 2.5 μm. It is preferable that the fifth interval I5 is 0.5 μm to 1.5 μm.
　活性領域１２側の最内の第１ダミートレンチ構造６１は、この形態では、第２方向Ｙに最外の第１トレンチソース構造２５に隣り合うように最外の第１トレンチソース構造２５から前述の第１間隔Ｉ１を空けて配置されている。 In this embodiment, the innermost first dummy trench structure 61 on the active region 12 side is arranged adjacent to the outermost first trench source structure 25 in the second direction Y, with the aforementioned first distance I1 from the outermost first trench source structure 25.
　第１ダミートレンチ構造６１は、第１ダミートレンチ６３、第１ダミー絶縁膜６４および第１ダミー埋設電極６５を含む。第１ダミートレンチ６３は、活性面８に形成され、第１ダミートレンチ構造６１の壁面を区画している。第１ダミートレンチ６３の側壁および底壁は、第３接続面１０Ｃに連通している。 The first dummy trench structure 61 includes a first dummy trench 63, a first dummy insulating film 64, and a first dummy buried electrode 65. The first dummy trench 63 is formed in the active surface 8 and defines the wall surface of the first dummy trench structure 61. The sidewall and bottom wall of the first dummy trench 63 are connected to the third connection surface 10C.
　第１ダミー絶縁膜６４は、第１ダミートレンチ６３の壁面を被覆し、活性面８において主面絶縁膜１６に接続されている。第１ダミー絶縁膜６４は、第３接続面１０Ｃの連通部において主面絶縁膜１６に接続されている。第１ダミー絶縁膜６４は、酸化シリコン膜、窒化シリコン膜および酸窒化シリコン膜のうちの少なくとも１つを含んでいてもよい。 The first dummy insulating film 64 covers the wall surface of the first dummy trench 63 and is connected to the main surface insulating film 16 at the active surface 8. The first dummy insulating film 64 is connected to the main surface insulating film 16 at the communicating portion of the third connection surface 10C. The first dummy insulating film 64 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
　第１ダミー絶縁膜６４は、この形態では、酸化シリコン膜からなる単層構造を有している。第１ダミー絶縁膜６４は、チップ２の酸化物からなる酸化シリコン膜を含むことが特に好ましい。第１ダミー埋設電極６５は、第１ダミー絶縁膜６４を挟んで第１ダミートレンチ６３に埋設されている。第１ダミー埋設電極６５は、導電性ポリシリコンを含んでいてもよい。 In this embodiment, the first dummy insulating film 64 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the first dummy insulating film 64 includes a silicon oxide film made of an oxide of the chip 2. The first dummy buried electrode 65 is buried in the first dummy trench 63 with the first dummy insulating film 64 in between. The first dummy buried electrode 65 may include conductive polysilicon.
　複数の第２ダミートレンチ構造６２は、活性面８の周縁および複数の第２トレンチ抵抗構造４３の間の領域に配置されている。複数の第２ダミートレンチ構造６２は、第２方向Ｙに隣り合う２つの第１ダミートレンチ構造６１の間の領域に配置されている。複数の第２ダミートレンチ構造６２は、第２方向Ｙに複数の第１ダミートレンチ構造６１と交互に配列され、第１方向Ｘに複数の第２トレンチ抵抗構造４３に１対１の対応関係で対向している。 The multiple second dummy trench structures 62 are arranged in the region between the periphery of the active surface 8 and the multiple second trench resistance structures 43. The multiple second dummy trench structures 62 are arranged in the region between two first dummy trench structures 61 adjacent in the second direction Y. The multiple second dummy trench structures 62 are arranged alternately with the multiple first dummy trench structures 61 in the second direction Y, and face the multiple second trench resistance structures 43 in a one-to-one correspondence in the first direction X.
　つまり、ゲート電位ＶＧが印加される第２トレンチ抵抗構造４３およびソース電位ＶＳが印加される第２ダミートレンチ構造６２が第１方向Ｘに対向している。複数の第２ダミートレンチ構造６２は、平面視において第１方向Ｘに延びる帯状にそれぞれ形成されている。 In other words, the second trench resistance structure 43 to which the gate potential VG is applied and the second dummy trench structure 62 to which the source potential VS is applied face each other in the first direction X. The multiple second dummy trench structures 62 are each formed in a band shape extending in the first direction X in a plan view.
　複数の第２ダミートレンチ構造６２は、第２方向Ｙに第１トレンチソース構造２５および第２トレンチソース構造３０に対向している。複数の第２ダミートレンチ構造６２は、複数の第１トレンチ抵抗構造４２の端部に対して複数の第２トレンチ抵抗構造４３の端部側に引き出された部分を有している。 The second dummy trench structures 62 face the first trench source structure 25 and the second trench source structure 30 in the second direction Y. The second dummy trench structures 62 have portions that are extended toward the ends of the second trench resistance structures 43 relative to the ends of the first trench resistance structures 42.
　具体的には、複数の第２ダミートレンチ構造６２は、第１トレンチ抵抗構造４２および第１ダミートレンチ構造６１の間の領域に対して複数の第２トレンチ抵抗構造４３の端部側に引き出されている。これにより、複数の第２ダミートレンチ構造６２の端部は、第２方向Ｙに第１トレンチ抵抗構造４２に対向している。つまり、複数の第２ダミートレンチ構造６２は、第２方向Ｙに第１トレンチ抵抗構造４２に対向する部分を有し、第２方向Ｙに第１ダミートレンチ構造６１に対向する部分を有している。 Specifically, the multiple second dummy trench structures 62 are pulled out toward the ends of the multiple second trench resistance structures 43 with respect to the region between the first trench resistance structure 42 and the first dummy trench structure 61. As a result, the ends of the multiple second dummy trench structures 62 face the first trench resistance structure 42 in the second direction Y. In other words, the multiple second dummy trench structures 62 have a portion facing the first trench resistance structure 42 in the second direction Y, and a portion facing the first dummy trench structure 61 in the second direction Y.
　複数の第２ダミートレンチ構造６２は、この形態では、第３接続面１０Ｃを貫通し、第３接続面１０Ｃから露出している。複数の第２ダミートレンチ構造６２は、第１半導体領域６に至るようにボディ領域１７を貫通している。複数の第２ダミートレンチ構造６２は、第１半導体領域６の底部から活性面８側に間隔を空けて形成されている。 In this embodiment, the multiple second dummy trench structures 62 penetrate the third connection surface 10C and are exposed from the third connection surface 10C. The multiple second dummy trench structures 62 penetrate the body region 17 to reach the first semiconductor region 6. The multiple second dummy trench structures 62 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.
　以下、１つの第２ダミートレンチ構造６２が説明される。第２ダミートレンチ構造６２は、第２方向Ｙに第７幅Ｗ７を有し、法線方向Ｚに第７深さＤ７を有している。第７幅Ｗ７は、第２トレンチ抵抗構造４３の第５幅Ｗ５とほぼ等しいことが好ましい。第７幅Ｗ７は、第１トレンチソース構造２５の第２幅Ｗ２（トレンチゲート構造２０の第１幅Ｗ１）とほぼ等しいことが好ましい。第７幅Ｗ７は、０．１μｍ以上３μｍ以下であってもよい。第７幅Ｗ７は、０．５μｍ以上２μｍ以下であることが好ましい。 Below, one second dummy trench structure 62 is described. The second dummy trench structure 62 has a seventh width W7 in the second direction Y and a seventh depth D7 in the normal direction Z. The seventh width W7 is preferably approximately equal to the fifth width W5 of the second trench resistor structure 43. The seventh width W7 is preferably approximately equal to the second width W2 of the first trench source structure 25 (the first width W1 of the trench gate structure 20). The seventh width W7 may be 0.1 μm or more and 3 μm or less. The seventh width W7 is preferably 0.5 μm or more and 2 μm or less.
　第７深さＤ７は、第１ダミートレンチ構造６１の第６深さＤ６（第１トレンチ抵抗構造４２の第４深さＤ４）以上である。第７深さＤ７は、この形態では、第６深さＤ６（第４深さＤ４）よりも大きい。第７深さＤ７は、第６深さＤ６（第４深さＤ４）の１．５倍以上３倍以下であることが好ましい。 The seventh depth D7 is equal to or greater than the sixth depth D6 of the first dummy trench structure 61 (the fourth depth D4 of the first trench resistor structure 42). In this embodiment, the seventh depth D7 is greater than the sixth depth D6 (the fourth depth D4). It is preferable that the seventh depth D7 is greater than or equal to 1.5 times and less than or equal to 3 times the sixth depth D6 (the fourth depth D4).
　第７深さＤ７は、第２トレンチ抵抗構造４３の第５深さＤ５（第１トレンチソース構造２５の第２深さＤ２）とほぼ等しいことが好ましい。第７深さＤ７は、この形態では、外周面９の外周深さＤＯとほぼ等しい。第７深さＤ７は、０．５μｍ以上５μｍ以下であってもよい。第７深さＤ７は、２．５μｍ以下であることが特に好ましい。 The seventh depth D7 is preferably approximately equal to the fifth depth D5 of the second trench resistor structure 43 (the second depth D2 of the first trench source structure 25). In this embodiment, the seventh depth D7 is approximately equal to the outer circumferential depth DO of the outer circumferential surface 9. The seventh depth D7 may be 0.5 μm or more and 5 μm or less. It is particularly preferable that the seventh depth D7 is 2.5 μm or less.
　第２ダミートレンチ構造６２は、第２方向Ｙに第１ダミートレンチ構造６１から第６間隔Ｉ６を空けて配置されている。第６間隔Ｉ６は、第６幅Ｗ６（第７幅Ｗ７）の０．５倍以上２倍以下であることが好ましい。第６間隔Ｉ６は、第６幅Ｗ６（第７幅Ｗ７）未満であることが特に好ましい。 The second dummy trench structure 62 is disposed at a sixth interval I6 from the first dummy trench structure 61 in the second direction Y. The sixth interval I6 is preferably 0.5 to 2 times the sixth width W6 (seventh width W7). It is particularly preferable that the sixth interval I6 is less than the sixth width W6 (seventh width W7).
　第６間隔Ｉ６は、第１トレンチ抵抗構造４２および第２トレンチ抵抗構造４３の間の第４間隔Ｉ４とほぼ等しいことが好ましい。第６間隔Ｉ６は、トレンチゲート構造２０および第１トレンチソース構造２５の間の第１間隔Ｉ１とほぼ等しいことが好ましい。第６間隔Ｉ６は、０．１μｍ以上２．５μｍ以下であってもよい。第６間隔Ｉ６は、０．５μｍ以上１．５μｍ以下であることが好ましい。 The sixth interval I6 is preferably approximately equal to the fourth interval I4 between the first trench resistor structure 42 and the second trench resistor structure 43. The sixth interval I6 is preferably approximately equal to the first interval I1 between the trench gate structure 20 and the first trench source structure 25. The sixth interval I6 may be 0.1 μm or more and 2.5 μm or less. The sixth interval I6 is preferably 0.5 μm or more and 1.5 μm or less.
　第２ダミートレンチ構造６２は、第１方向Ｘに第２トレンチ抵抗構造４３から第７間隔Ｉ７を空けて配置されている。第７間隔Ｉ７は、第６幅Ｗ６（第７幅Ｗ７）の０．５倍以上２倍以下であることが好ましい。第７間隔Ｉ７は、第６幅Ｗ６（第７幅Ｗ７）の０．５倍以上２倍以下であることが好ましい。 The second dummy trench structure 62 is disposed in the first direction X at a seventh interval I7 from the second trench resistor structure 43. The seventh interval I7 is preferably 0.5 to 2 times the sixth width W6 (seventh width W7). The seventh interval I7 is preferably 0.5 to 2 times the sixth width W6 (seventh width W7).
　第７間隔Ｉ７は、第６間隔Ｉ６（第４間隔Ｉ４）の１．５倍以下であることが特に好ましい。第７間隔Ｉ７は、前述の第５間隔Ｉ５とほぼ等しいことが好ましい。第７間隔Ｉ７は、第６間隔Ｉ６（第４間隔Ｉ４）とほぼ等しくてもよい。第７間隔Ｉ７は、０．１μｍ以上２．５μｍ以下であってもよい。第７間隔Ｉ７は、０．５μｍ以上１．５μｍ以下であることが好ましい。 It is particularly preferable that the seventh interval I7 is 1.5 times or less the sixth interval I6 (fourth interval I4). It is preferable that the seventh interval I7 is approximately equal to the aforementioned fifth interval I5. The seventh interval I7 may be approximately equal to the sixth interval I6 (fourth interval I4). The seventh interval I7 may be 0.1 μm or more and 2.5 μm or less. It is preferable that the seventh interval I7 is 0.5 μm or more and 1.5 μm or less.
　第２ダミートレンチ構造６２は、第２ダミートレンチ６６、第２ダミー絶縁膜６７および第２ダミー埋設電極６８を含む。第２ダミートレンチ６６は、活性面８に形成され、第２ダミートレンチ構造６２の壁面を区画している。第２ダミートレンチ６６の側壁は、第３接続面１０Ｃに連通している。また、第２ダミートレンチ６６の底壁は、外周面９に連通している。 The second dummy trench structure 62 includes a second dummy trench 66, a second dummy insulating film 67, and a second dummy buried electrode 68. The second dummy trench 66 is formed in the active surface 8 and defines the wall surface of the second dummy trench structure 62. The side wall of the second dummy trench 66 is connected to the third connection surface 10C. In addition, the bottom wall of the second dummy trench 66 is connected to the outer peripheral surface 9.
　第２ダミー絶縁膜６７は、第２ダミートレンチ６６の壁面を被覆し、活性面８において主面絶縁膜１６に接続されている。第２ダミー絶縁膜６７は、第３接続面１０Ｃの連通部および外周面９の連通部において主面絶縁膜１６に接続されている。第２ダミー絶縁膜６７は、酸化シリコン膜、窒化シリコン膜および酸窒化シリコン膜のうちの少なくとも１つを含んでいてもよい。 The second dummy insulating film 67 covers the wall surface of the second dummy trench 66 and is connected to the main surface insulating film 16 at the active surface 8. The second dummy insulating film 67 is connected to the main surface insulating film 16 at the communicating portion of the third connection surface 10C and the communicating portion of the outer peripheral surface 9. The second dummy insulating film 67 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
　第２ダミー絶縁膜６７は、この形態では、酸化シリコン膜からなる単層構造を有している。第２ダミー絶縁膜６７は、チップ２の酸化物からなる酸化シリコン膜を含むことが特に好ましい。第２ダミー埋設電極６８は、第２ダミー絶縁膜６７を挟んで第２ダミートレンチ６６に埋設されている。第２ダミー埋設電極６８は、導電性ポリシリコンを含んでいてもよい。 In this embodiment, the second dummy insulating film 67 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the second dummy insulating film 67 includes a silicon oxide film made of an oxide of the chip 2. The second dummy buried electrode 68 is buried in the second dummy trench 66 with the second dummy insulating film 67 in between. The second dummy buried electrode 68 may include conductive polysilicon.
　図１６および図２３を参照して、半導体装置１は、複数のメインメサ部７０、複数の第１メサ部７１および複数の第２メサ部７２を含む。各メインメサ部７０は、第１トレンチ抵抗構造４２および第２トレンチ抵抗構造４３の間の領域、ならびに、第１ダミートレンチ構造６１および第２ダミートレンチ構造６２の間の領域に区画されている。各メインメサ部７０は、第１方向Ｘに帯状に延びている。各メインメサ部７０の第２方向Ｙの幅は、前述の第４間隔Ｉ４および第６間隔Ｉ６によって規定される。 16 and 23, the semiconductor device 1 includes a plurality of main mesa portions 70, a plurality of first mesa portions 71, and a plurality of second mesa portions 72. Each main mesa portion 70 is partitioned into a region between the first trench resistance structure 42 and the second trench resistance structure 43, and a region between the first dummy trench structure 61 and the second dummy trench structure 62. Each main mesa portion 70 extends in a strip shape in the first direction X. The width of each main mesa portion 70 in the second direction Y is determined by the aforementioned fourth interval I4 and sixth interval I6.
　各第１メサ部７１は、第１トレンチ抵抗構造４２および第１ダミートレンチ構造６１の間の領域に区画され、メインメサ部７０に接続されている。各第１メサ部７１は、第１方向Ｘにゲート電位ＶＧおよびソース電位ＶＳの間の電圧降下が生じる領域である。各第１メサ部７１の第１方向Ｘの幅は、前述の第５間隔Ｉ５によって規定される。 Each first mesa portion 71 is partitioned into an area between the first trench resistor structure 42 and the first dummy trench structure 61, and is connected to the main mesa portion 70. Each first mesa portion 71 is an area in which a voltage drop occurs between the gate potential VG and the source potential VS in the first direction X. The width of each first mesa portion 71 in the first direction X is determined by the fifth interval I5 described above.
　各第１メサ部７１は、この形態では、第２方向Ｙに第２ダミートレンチ構造６２に対向し、第２方向Ｙに第２トレンチ抵抗構造４３に対向しないように、第２トレンチ抵抗構造４３の端部に対して第２ダミートレンチ構造６２側にずれている。各第１メサ部７１は、抵抗膜５０の周縁から第１方向Ｘに間隔を空けて形成され、法線方向Ｚに抵抗膜５０に対向していない。 In this embodiment, each first mesa portion 71 faces the second dummy trench structure 62 in the second direction Y, but is shifted toward the second dummy trench structure 62 with respect to the end of the second trench resistance structure 43 so as not to face the second trench resistance structure 43 in the second direction Y. Each first mesa portion 71 is formed at a distance from the periphery of the resistance film 50 in the first direction X, and does not face the resistance film 50 in the normal direction Z.
　したがって、各第１メサ部７１に対する抵抗膜５０の電気的な干渉が抑制され、抵抗膜５０に対する各第１メサ部７１の電気的な干渉が抑制されている。むろん、複数のトレンチ抵抗構造４１よりも幅広な抵抗膜５０が形成された場合、各第１メサ部７１は法線方向Ｚに抵抗膜５０に対向していてもよい。 Therefore, electrical interference of the resistive film 50 with each first mesa portion 71 is suppressed, and electrical interference of each first mesa portion 71 with the resistive film 50 is suppressed. Of course, if a resistive film 50 wider than the multiple trench resistance structures 41 is formed, each first mesa portion 71 may face the resistive film 50 in the normal direction Z.
　各第１メサ部７１は、平面視において１つのメインメサ部７０とＴ字状のメサを区画している。別視点において、各第１メサ部７１は、平面視において２つのメインメサ部７０とＨ字状のメサを区画している。複数の第１メサ部７１は、この形態では、第２方向Ｙに沿って同一直線上に形成されている。むろん、複数の第１メサ部７１は、第２方向Ｙに沿って同一直線上に位置しないように第１方向Ｘに互いにずれて形成されていてもよい。 Each first mesa portion 71 defines one main mesa portion 70 and a T-shaped mesa in plan view. From another perspective, each first mesa portion 71 defines two main mesa portions 70 and an H-shaped mesa in plan view. In this embodiment, the multiple first mesa portions 71 are formed on the same straight line along the second direction Y. Of course, the multiple first mesa portions 71 may be formed offset from each other in the first direction X so as not to be positioned on the same straight line along the second direction Y.
　各第２メサ部７２は、第２トレンチ抵抗構造４３および第２ダミートレンチ構造６２の間の領域に区画され、メインメサ部７０に接続されている。各第２メサ部７２は、第１方向Ｘにゲート電位ＶＧおよびソース電位ＶＳの間の電圧降下が生じる領域である。各第２メサ部７２の第１方向Ｘの幅は、前述の第７間隔Ｉ７によって規定される。 Each second mesa portion 72 is partitioned into an area between the second trench resistor structure 43 and the second dummy trench structure 62, and is connected to the main mesa portion 70. Each second mesa portion 72 is an area in which a voltage drop occurs between the gate potential VG and the source potential VS in the first direction X. The width of each second mesa portion 72 in the first direction X is determined by the seventh interval I7 described above.
　各第２メサ部７２は、第２方向Ｙに第１メサ部７１に対向しないように、第１メサ部７１から第１方向Ｘに間隔を空けて形成されている。各第２メサ部７２は、この形態では、第２方向Ｙに第１トレンチ抵抗構造４２に対向し、第２方向Ｙに第１ダミートレンチ構造６１に対向しないように、第１ダミートレンチ構造６１の端部に対して第１トレンチ抵抗構造４２側にずれている。 Each second mesa portion 72 is formed at a distance from the first mesa portion 71 in the first direction X so as not to face the first mesa portion 71 in the second direction Y. In this embodiment, each second mesa portion 72 faces the first trench resistance structure 42 in the second direction Y, and is shifted toward the first trench resistance structure 42 with respect to the end of the first dummy trench structure 61 so as not to face the first dummy trench structure 61 in the second direction Y.
　各第２メサ部７２は、平面視において抵抗膜５０の周縁から第１方向Ｘに間隔を空けて形成され、法線方向Ｚに抵抗膜５０に対向していない。したがって、各第２メサ部７２に対する抵抗膜５０の電気的な干渉が抑制され、抵抗膜５０に対する各第２メサ部７２の電気的な干渉が抑制されている。むろん、複数のトレンチ抵抗構造４１よりも幅広な抵抗膜５０が形成された場合、各第２メサ部７２は法線方向Ｚに抵抗膜５０に対向していてもよい。 Each second mesa portion 72 is formed at a distance from the periphery of the resistive film 50 in the first direction X in a plan view, and does not face the resistive film 50 in the normal direction Z. Therefore, electrical interference of the resistive film 50 with each second mesa portion 72 is suppressed, and electrical interference of each second mesa portion 72 with the resistive film 50 is suppressed. Of course, if a resistive film 50 wider than the multiple trench resistance structures 41 is formed, each second mesa portion 72 may face the resistive film 50 in the normal direction Z.
　各第２メサ部７２は、平面視において１つのメインメサ部７０とＴ字状のメサを区画している。別視点において、各第２メサ部７２は、平面視において２つのメインメサ部７０とＨ字状のメサを区画している。複数の第２メサ部７２は、この形態では、第２方向Ｙに沿って同一直線上に形成されている。 Each second mesa portion 72 defines one main mesa portion 70 and a T-shaped mesa in plan view. From another perspective, each second mesa portion 72 defines two main mesa portions 70 and an H-shaped mesa in plan view. In this embodiment, the multiple second mesa portions 72 are formed on the same straight line along the second direction Y.
　むろん、複数の第２メサ部７２は、第２方向Ｙに沿って同一直線上に位置しないように第１方向Ｘに互いにずれて形成されていてもよい。この場合においても、複数の第２メサ部７２は、第２方向Ｙに第１メサ部７１に対向しないように、第１メサ部７１から第１方向Ｘに間隔を空けて形成される。 Of course, the multiple second mesa portions 72 may be formed offset from each other in the first direction X so as not to be positioned on the same straight line along the second direction Y. Even in this case, the multiple second mesa portions 72 are formed at intervals from the first mesa portion 71 in the first direction X so as not to face the first mesa portion 71 in the second direction Y.
　半導体装置１は、第１終端領域１５Ａにおいて複数の第１トレンチ抵抗構造４２に沿う領域に形成されたｐ型の複数の第４ウェル領域７５を含む。第４ウェル領域７５は、この形態では、ボディ領域１７よりも高いｐ型不純物濃度を有している。むろん、第４ウェル領域７５のｐ型不純物濃度は、ボディ領域１７よりも低くてもよい。第４ウェル領域７５のｐ型不純物濃度は、第１ウェル領域３５のｐ型不純物濃度とほぼ等しいことが好ましい。 The semiconductor device 1 includes a plurality of fourth well regions 75 of p-type formed in a region along the plurality of first trench resistance structures 42 in the first termination region 15A. In this embodiment, the fourth well region 75 has a higher p-type impurity concentration than the body region 17. Of course, the p-type impurity concentration of the fourth well region 75 may be lower than the body region 17. It is preferable that the p-type impurity concentration of the fourth well region 75 is approximately equal to the p-type impurity concentration of the first well region 35.
　複数の第４ウェル領域７５は、第２トレンチ抵抗構造４３、第１ダミートレンチ構造６１および第２ダミートレンチ構造６２から間隔を空けて対応する第１トレンチ抵抗構造４２の壁面を被覆し、活性面８の表層部においてボディ領域１７に電気的に接続されている。 The multiple fourth well regions 75 cover the wall surfaces of the corresponding first trench resistance structures 42 at intervals from the second trench resistance structure 43, the first dummy trench structure 61, and the second dummy trench structure 62, and are electrically connected to the body region 17 in the surface portion of the active surface 8.
　各第４ウェル領域７５は、各第１メサ部７１内において各第１トレンチ抵抗構造４２の壁面を被覆する部分を含み、第１方向Ｘに各第１ダミートレンチ構造６１に対向している。各第４ウェル領域７５は、この形態では、第２方向Ｙに第２トレンチ抵抗構造４３に対向する部分を有し、第２方向Ｙに第２ダミートレンチ構造６２に対向する部分を有している。 Each fourth well region 75 includes a portion that covers the wall surface of each first trench resistance structure 42 in each first mesa portion 71, and faces each first dummy trench structure 61 in the first direction X. In this embodiment, each fourth well region 75 has a portion that faces the second trench resistance structure 43 in the second direction Y, and a portion that faces the second dummy trench structure 62 in the second direction Y.
　複数の第４ウェル領域７５は、第１半導体領域６の底部から活性面８側に間隔を空けて形成され、第１半導体領域６の一部を挟んで第２半導体領域７に対向している。複数の第４ウェル領域７５の底部は、複数の第２ウェル領域３６の底部の深さ位置に対して活性面８側に位置している。複数の第４ウェル領域７５の底部は、複数の第１ウェル領域３５の底部とほぼ等しい深さに形成されている。複数の第４ウェル領域７５は、第１半導体領域６とｐｎ接合部を形成している。 The multiple fourth well regions 75 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 across a portion of the first semiconductor region 6. The bottoms of the multiple fourth well regions 75 are located on the active surface 8 side relative to the depth position of the bottoms of the multiple second well regions 36. The bottoms of the multiple fourth well regions 75 are formed at approximately the same depth as the bottoms of the multiple first well regions 35. The multiple fourth well regions 75 form pn junctions with the first semiconductor region 6.
　半導体装置１は、第１終端領域１５Ａにおいて複数の第２トレンチ抵抗構造４３に沿う領域に形成されたｐ型の複数の第５ウェル領域７６を含む。第５ウェル領域７６は、この形態では、ボディ領域１７よりも高いｐ型不純物濃度を有している。むろん、第５ウェル領域７６のｐ型不純物濃度は、ボディ領域１７よりも低くてもよい。第５ウェル領域７６のｐ型不純物濃度は、複数の第４ウェル領域７５（第２ウェル領域３６）のｐ型不純物濃度とほぼ等しいことが好ましい。 The semiconductor device 1 includes a plurality of p-type fifth well regions 76 formed in a region along the plurality of second trench resistance structures 43 in the first termination region 15A. In this embodiment, the fifth well region 76 has a higher p-type impurity concentration than the body region 17. Of course, the p-type impurity concentration of the fifth well region 76 may be lower than the body region 17. It is preferable that the p-type impurity concentration of the fifth well region 76 is approximately equal to the p-type impurity concentration of the plurality of fourth well regions 75 (second well region 36).
　複数の第５ウェル領域７６は、第１トレンチ抵抗構造４２、第１ダミートレンチ構造６１および第２ダミートレンチ構造６２から間隔を空けて対応する第２トレンチ抵抗構造４３の壁面を被覆し、活性面８の表層部においてボディ領域１７に電気的に接続されている。各第５ウェル領域７６は、各第２メサ部７２内において各第２トレンチ抵抗構造４３の壁面を被覆する部分を含み、第１方向Ｘに第２ダミートレンチ構造６２に対向している。各第５ウェル領域７６は、この形態では、第２方向Ｙに第１トレンチ抵抗構造４２に対向し、第２方向Ｙに第１ダミートレンチ構造６１に対向していない。 The plurality of fifth well regions 76 cover the wall surfaces of the corresponding second trench resistance structures 43 at intervals from the first trench resistance structure 42, the first dummy trench structure 61, and the second dummy trench structure 62, and are electrically connected to the body region 17 at the surface portion of the active surface 8. Each fifth well region 76 includes a portion that covers the wall surface of each second trench resistance structure 43 in each second mesa portion 72, and faces the second dummy trench structure 62 in the first direction X. In this embodiment, each fifth well region 76 faces the first trench resistance structure 42 in the second direction Y, but does not face the first dummy trench structure 61 in the second direction Y.
　複数の第５ウェル領域７６は、第１半導体領域６の底部から活性面８側に間隔を空けて形成され、第１半導体領域６の一部を挟んで第２半導体領域７に対向している。複数の第５ウェル領域７６の底部は、複数の第４ウェル領域７５（第１ウェル領域３５）の底部の深さ位置に対して第１半導体領域６の底部側に位置している。複数の第５ウェル領域７６の底部は、複数の第２ウェル領域３６の底部とほぼ等しい深さに形成されている。複数の第５ウェル領域７６は、第１半導体領域６とｐｎ接合部を形成している。 The multiple fifth well regions 76 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 across a portion of the first semiconductor region 6. The bottoms of the multiple fifth well regions 76 are located on the bottom side of the first semiconductor region 6 relative to the depth position of the bottoms of the multiple fourth well regions 75 (first well regions 35). The bottoms of the multiple fifth well regions 76 are formed at a depth approximately equal to the bottoms of the multiple second well regions 36. The multiple fifth well regions 76 form pn junctions with the first semiconductor region 6.
　半導体装置１は、第１終端領域１５Ａにおいて複数の第１ダミートレンチ構造６１に沿う領域に形成されたｐ型の複数の第６ウェル領域７７を含む。第６ウェル領域７７は、この形態では、ボディ領域１７よりも高いｐ型不純物濃度を有している。むろん、第６ウェル領域７７のｐ型不純物濃度は、ボディ領域１７よりも低くてもよい。第６ウェル領域７７のｐ型不純物濃度は、第４ウェル領域７５（第１ウェル領域３５）のｐ型不純物濃度とほぼ等しいことが好ましい。 The semiconductor device 1 includes a plurality of sixth well regions 77 of p-type formed in a region along the plurality of first dummy trench structures 61 in the first termination region 15A. In this embodiment, the sixth well region 77 has a higher p-type impurity concentration than the body region 17. Of course, the p-type impurity concentration of the sixth well region 77 may be lower than the body region 17. It is preferable that the p-type impurity concentration of the sixth well region 77 is approximately equal to the p-type impurity concentration of the fourth well region 75 (first well region 35).
　複数の第６ウェル領域７７は、第１トレンチ抵抗構造４２、第２トレンチ抵抗構造４３および第２ダミートレンチ構造６２から間隔を空けて対応する第１ダミートレンチ構造６１の壁面を被覆し、活性面８の表層部においてボディ領域１７に電気的に接続されている。各第６ウェル領域７７は、各第１メサ部７１内において各第１ダミートレンチ構造６１の壁面を被覆する部分を含み、第１方向Ｘに第１トレンチ抵抗構造４２に対向している。 The sixth well regions 77 cover the walls of the corresponding first dummy trench structures 61 at intervals from the first trench resistance structure 42, the second trench resistance structure 43, and the second dummy trench structure 62, and are electrically connected to the body region 17 at the surface portion of the active surface 8. Each sixth well region 77 includes a portion that covers the wall of each first dummy trench structure 61 in each first mesa portion 71, and faces the first trench resistance structure 42 in the first direction X.
　各第６ウェル領域７７は、各第１メサ部７１内において各第４ウェル領域７５から間隔を空けて形成されていてもよいし、各第４ウェル領域７５と一体化していてもよい。各第６ウェル領域７７は、第２方向Ｙに第２ダミートレンチ構造６２に対向し、第２方向Ｙに第２トレンチ抵抗構造４３に対向していない。 Each sixth well region 77 may be formed in each first mesa portion 71 at a distance from each fourth well region 75, or may be integrated with each fourth well region 75. Each sixth well region 77 faces the second dummy trench structure 62 in the second direction Y, but does not face the second trench resistor structure 43 in the second direction Y.
　複数の第６ウェル領域７７は、第１半導体領域６の底部から活性面８側に間隔を空けて形成され、第１半導体領域６の一部を挟んで第２半導体領域７に対向している。複数の第６ウェル領域７７の底部は、複数の第５ウェル領域７６（第２ウェル領域３６）の底部の深さ位置に対して活性面８側に位置している。複数の第６ウェル領域７７の底部は、複数の第４ウェル領域７５（第１ウェル領域３５）の底部とほぼ等しい深さに形成されている。複数の第６ウェル領域７７は、第１半導体領域６とｐｎ接合部を形成している。 The multiple sixth well regions 77 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 across a portion of the first semiconductor region 6. The bottoms of the multiple sixth well regions 77 are located on the active surface 8 side relative to the depth position of the bottoms of the multiple fifth well regions 76 (second well regions 36). The bottoms of the multiple sixth well regions 77 are formed at a depth approximately equal to the bottoms of the multiple fourth well regions 75 (first well regions 35). The multiple sixth well regions 77 form pn junctions with the first semiconductor region 6.
　半導体装置１は、第１終端領域１５Ａにおいて複数の第２ダミートレンチ構造６２に沿う領域に形成されたｐ型の複数の第７ウェル領域７８を含む。第７ウェル領域７８は、この形態では、ボディ領域１７よりも高いｐ型不純物濃度を有している。むろん、第７ウェル領域７８のｐ型不純物濃度は、ボディ領域１７よりも低くてもよい。第７ウェル領域７８のｐ型不純物濃度は、第５ウェル領域７６（第２ウェル領域３６）のｐ型不純物濃度とほぼ等しいことが好ましい。 The semiconductor device 1 includes a plurality of p-type seventh well regions 78 formed in a region along the plurality of second dummy trench structures 62 in the first termination region 15A. In this embodiment, the seventh well regions 78 have a higher p-type impurity concentration than the body region 17. Of course, the p-type impurity concentration of the seventh well regions 78 may be lower than the body region 17. It is preferable that the p-type impurity concentration of the seventh well regions 78 is approximately equal to the p-type impurity concentration of the fifth well region 76 (second well region 36).
　複数の第７ウェル領域７８は、第１トレンチ抵抗構造４２、第２トレンチ抵抗構造４３および第１ダミートレンチ構造６１から間隔を空けて対応する第２ダミートレンチ構造６２の壁面を被覆し、活性面８の表層部においてボディ領域１７に電気的に接続されている。各第７ウェル領域７８は、各第２メサ部７２内において各第２ダミートレンチ構造６２の壁面を被覆する部分を含み、第１方向Ｘに第２トレンチ抵抗構造４３に対向している。 The seventh well regions 78 cover the walls of the corresponding second dummy trench structures 62 at intervals from the first trench resistance structure 42, the second trench resistance structure 43, and the first dummy trench structure 61, and are electrically connected to the body region 17 at the surface portion of the active surface 8. Each seventh well region 78 includes a portion that covers the wall of each second dummy trench structure 62 in each second mesa portion 72, and faces the second trench resistance structure 43 in the first direction X.
　各第７ウェル領域７８は、各第２メサ部７２内において各第５ウェル領域７６から間隔を空けて形成されていてもよいし、各第５ウェル領域７６と一体化していてもよい。各第７ウェル領域７８は、第２方向Ｙに第１ダミートレンチ構造６１に対向する部分を有し、第２方向Ｙに第１トレンチ抵抗構造４２に対向する部分を有している。 Each seventh well region 78 may be formed in each second mesa portion 72 at a distance from each fifth well region 76, or may be integrated with each fifth well region 76. Each seventh well region 78 has a portion facing the first dummy trench structure 61 in the second direction Y, and a portion facing the first trench resistor structure 42 in the second direction Y.
　複数の第７ウェル領域７８は、第１半導体領域６の底部から活性面８側に間隔を空けて形成され、第１半導体領域６の一部を挟んで第２半導体領域７に対向している。複数の第７ウェル領域７８の底部は、複数の第６ウェル領域７７（第４ウェル領域７５）の底部の深さ位置に対して第１半導体領域６の底部側に位置している。複数の第７ウェル領域７８の底部は、複数の第５ウェル領域７６（第２ウェル領域３６）の底部とほぼ等しい深さに形成されている。複数の第７ウェル領域７８は、第１半導体領域６とｐｎ接合部を形成している。 The multiple seventh well regions 78 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 across a portion of the first semiconductor region 6. The bottoms of the multiple seventh well regions 78 are located on the bottom side of the first semiconductor region 6 relative to the depth position of the bottoms of the multiple sixth well regions 77 (fourth well regions 75). The bottoms of the multiple seventh well regions 78 are formed at a depth approximately equal to the bottoms of the multiple fifth well regions 76 (second well regions 36). The multiple seventh well regions 78 form pn junctions with the first semiconductor region 6.
　半導体装置１は、第１終端領域１５Ａにおいて複数の第２トレンチ抵抗構造４３に沿う領域に形成されたｐ型の複数の第２コンタクト領域７９を含む。第２コンタクト領域７９は、ボディ領域１７よりも高いｐ型不純物濃度を有している。第２コンタクト領域７９のｐ型不純物濃度は、第５ウェル領域７６よりも高い。第２コンタクト領域７９のｐ型不純物濃度は、第１コンタクト領域３８のｐ型不純物濃度とほぼ等しいことが好ましい。 The semiconductor device 1 includes a plurality of second contact regions 79 of p-type formed in a region along the plurality of second trench resistance structures 43 in the first termination region 15A. The second contact regions 79 have a higher p-type impurity concentration than the body region 17. The p-type impurity concentration of the second contact regions 79 is higher than the fifth well region 76. It is preferable that the p-type impurity concentration of the second contact regions 79 is approximately equal to the p-type impurity concentration of the first contact region 38.
　複数の第２コンタクト領域７９は、対応する第５ウェル領域７６内において対応する第２トレンチ抵抗構造４３の壁面を被覆している。複数の第２コンタクト領域７９は、各第２トレンチ抵抗構造４３に対して１対多の対応関係で形成されている。複数の第２コンタクト領域７９は、対応する第２トレンチ抵抗構造４３に沿って間隔を空けて形成されている。複数の第２コンタクト領域７９は、対応する第５ウェル領域７６内から対応する第２トレンチ抵抗構造４３の壁面に沿ってボディ領域１７の表層部に引き出され、活性面８から露出している。 The second contact regions 79 cover the wall surfaces of the corresponding second trench resistance structures 43 in the corresponding fifth well regions 76. The second contact regions 79 are formed in a one-to-many correspondence with each second trench resistance structure 43. The second contact regions 79 are formed at intervals along the corresponding second trench resistance structures 43. The second contact regions 79 are extended from the corresponding fifth well regions 76 along the wall surfaces of the corresponding second trench resistance structures 43 to the surface layer of the body region 17 and exposed from the active surface 8.
　複数の第２コンタクト領域７９は、この形態では、平面視において第１方向Ｘに延びる帯状にそれぞれ形成されている。複数の第２コンタクト領域７９の第１方向Ｘの長さは、第２トレンチ抵抗構造４３の第５幅Ｗ５以上であることが好ましい。複数の第２コンタクト領域７９の長さは、第１方向Ｘに隣り合う２つの第２コンタクト領域７９の間の距離よりも大きいことが好ましい。複数の第２コンタクト領域７９の長さは、第１メサ部７１および第２メサ部７２の間の距離未満であることが好ましい。複数の第２コンタクト領域７９の長さは、複数の第１コンタクト領域３８の長さとほぼ等しいことが好ましい。 In this embodiment, the multiple second contact regions 79 are each formed in a band shape extending in the first direction X in a plan view. The length of the multiple second contact regions 79 in the first direction X is preferably equal to or greater than the fifth width W5 of the second trench resistance structure 43. The length of the multiple second contact regions 79 is preferably greater than the distance between two adjacent second contact regions 79 in the first direction X. The length of the multiple second contact regions 79 is preferably less than the distance between the first mesa portion 71 and the second mesa portion 72. The length of the multiple second contact regions 79 is preferably approximately equal to the length of the multiple first contact regions 38.
　複数の第２コンタクト領域７９は、各第２トレンチ抵抗構造４３の端部に沿う領域を被覆する最外の第２コンタクト領域７９を含む。最外の第２コンタクト領域７９は、第２メサ部７２から間隔を空けて形成されていることが好ましい。つまり、最外の第２コンタクト領域７９は、第２方向Ｙに第１トレンチ抵抗構造４２に対向し、第２方向Ｙに第１ダミートレンチ構造６１に対向していないことが好ましい。 The multiple second contact regions 79 include an outermost second contact region 79 that covers an area along the end of each second trench resistance structure 43. The outermost second contact region 79 is preferably formed at a distance from the second mesa portion 72. In other words, the outermost second contact region 79 preferably faces the first trench resistance structure 42 in the second direction Y, but does not face the first dummy trench structure 61 in the second direction Y.
　たとえば、第１方向Ｘに関して、第２メサ部７２および最外の第２コンタクト領域７９の間の距離は、第２コンタクト領域７９の長さ未満であってもよい。第２メサ部７２および最外の第２コンタクト領域７９の間の距離は、第２トレンチ抵抗構造４３の第５幅Ｗ５未満であってもよい。第２メサ部７２および最外の第２コンタクト領域７９の間の距離は、第２メサ部７２の幅（第７間隔Ｉ７）未満であることが特に好ましい。 For example, with respect to the first direction X, the distance between the second mesa portion 72 and the outermost second contact region 79 may be less than the length of the second contact region 79. The distance between the second mesa portion 72 and the outermost second contact region 79 may be less than the fifth width W5 of the second trench resistor structure 43. It is particularly preferable that the distance between the second mesa portion 72 and the outermost second contact region 79 is less than the width (seventh interval I7) of the second mesa portion 72.
　１つの第２トレンチ抵抗構造４３に沿う複数の第２コンタクト領域７９は、他の第２トレンチ抵抗構造４３に沿う複数の第２コンタクト領域７９に第２方向Ｙに対向している。つまり、複数の第２コンタクト領域７９は、この形態では、平面視において全体として第１方向Ｘおよび第２方向Ｙに間隔を空けて行列状に配列されている。複数の第２コンタクト領域７９は、第２方向Ｙに複数の第１コンタクト領域３８に対向していてもよい。この場合、複数の第２コンタクト領域７９は、複数の第１コンタクト領域３８と共に行列状に配列されていてもよい。 The second contact regions 79 along one second trench resistance structure 43 face the second contact regions 79 along the other second trench resistance structures 43 in the second direction Y. That is, in this embodiment, the second contact regions 79 are arranged in a matrix with gaps in the first direction X and the second direction Y as a whole in a plan view. The second contact regions 79 may face the first contact regions 38 in the second direction Y. In this case, the second contact regions 79 may be arranged in a matrix with the first contact regions 38.
　１つの第２トレンチ抵抗構造４３に沿う複数の第２コンタクト領域７９は、他の第２トレンチ抵抗構造４３に沿う複数の第２コンタクト領域７９の間の領域に第２方向Ｙに対向するように第１方向Ｘにずれて配列されていてもよい。つまり、複数の第２コンタクト領域７９は、平面視において全体として第１方向Ｘおよび第２方向Ｙに間隔を空けて千鳥状に配列されていてもよい。複数の第２コンタクト領域７９は、第２方向Ｙに複数の第１コンタクト領域３８の間の領域に対向していてもよい。この場合、複数の第２コンタクト領域７９は、複数の第１コンタクト領域３８と共に千鳥状に配列されていてもよい。 The second contact regions 79 along one second trench resistance structure 43 may be arranged offset in the first direction X so as to face the regions between the second contact regions 79 along the other second trench resistance structures 43 in the second direction Y. In other words, the second contact regions 79 may be arranged in a staggered manner with gaps in the first direction X and the second direction Y as a whole in a plan view. The second contact regions 79 may face the regions between the first contact regions 38 in the second direction Y. In this case, the second contact regions 79 may be arranged in a staggered manner together with the first contact regions 38.
　半導体装置１は、第１終端領域１５Ａにおいて複数の第２ダミートレンチ構造６２に沿う領域に形成されたｐ型の複数の第３コンタクト領域８０を含む。第３コンタクト領域８０は、ボディ領域１７よりも高いｐ型不純物濃度を有している。第３コンタクト領域８０のｐ型不純物濃度は、第７ウェル領域７８よりも高い。第３コンタクト領域８０のｐ型不純物濃度は、第２コンタクト領域７９（第１コンタクト領域３８）のｐ型不純物濃度とほぼ等しいことが好ましい。 The semiconductor device 1 includes a plurality of p-type third contact regions 80 formed in a region along the plurality of second dummy trench structures 62 in the first termination region 15A. The third contact regions 80 have a higher p-type impurity concentration than the body region 17. The p-type impurity concentration of the third contact regions 80 is higher than the seventh well region 78. It is preferable that the p-type impurity concentration of the third contact regions 80 is approximately equal to the p-type impurity concentration of the second contact region 79 (first contact region 38).
　複数の第３コンタクト領域８０は、対応する第７ウェル領域７８内において対応する第２ダミートレンチ構造６２の壁面を被覆している。複数の第３コンタクト領域８０は、各第２ダミートレンチ構造６２に対して１対多の対応関係で形成されている。複数の第３コンタクト領域８０は、対応する第２ダミートレンチ構造６２に沿って間隔を空けて形成されている。複数の第３コンタクト領域８０は、対応する第７ウェル領域７８内から対応する第２ダミートレンチ構造６２の壁面に沿ってボディ領域１７の表層部に引き出され、活性面８から露出している。 The multiple third contact regions 80 cover the wall surfaces of the corresponding second dummy trench structures 62 in the corresponding seventh well regions 78. The multiple third contact regions 80 are formed in a one-to-many correspondence with each second dummy trench structure 62. The multiple third contact regions 80 are formed at intervals along the corresponding second dummy trench structures 62. The multiple third contact regions 80 are extended from the corresponding seventh well regions 78 along the wall surfaces of the corresponding second dummy trench structures 62 to the surface layer of the body region 17 and exposed from the active surface 8.
　複数の第３コンタクト領域８０は、この形態では、平面視において第１方向Ｘに延びる帯状にそれぞれ形成されている。複数の第３コンタクト領域８０の第１方向Ｘの長さは、前述の第７幅Ｗ７以上であることが好ましい。複数の第３コンタクト領域８０の長さは、第１方向Ｘに隣り合う２つの第３コンタクト領域８０の間の距離よりも大きいことが好ましい。複数の第３コンタクト領域８０の長さは、第１メサ部７１および第２メサ部７２の間の距離未満であることが好ましい。複数の第３コンタクト領域８０の長さは、複数の第２コンタクト領域７９（第１コンタクト領域３８）の長さとほぼ等しいことが好ましい。 In this embodiment, the multiple third contact regions 80 are each formed in a band shape extending in the first direction X in a plan view. The length of the multiple third contact regions 80 in the first direction X is preferably equal to or greater than the seventh width W7 described above. The length of the multiple third contact regions 80 is preferably greater than the distance between two adjacent third contact regions 80 in the first direction X. The length of the multiple third contact regions 80 is preferably less than the distance between the first mesa portion 71 and the second mesa portion 72. The length of the multiple third contact regions 80 is preferably approximately equal to the length of the multiple second contact regions 79 (first contact regions 38).
　複数の第３コンタクト領域８０は、第１メサ部７１に対して第３接続面１０Ｃ側の領域において、第２方向Ｙに第１ダミートレンチ構造６１に対向している。複数の第３コンタクト領域８０は、互いに隣り合う２つの第３コンタクト領域８０の間に第１メサ部７１が位置するように各第２ダミートレンチ構造６２に沿って間隔を空けて形成されている。複数の第３コンタクト領域８０は、第１メサ部７１に対向しないように第１メサ部７１から第１方向Ｘに間隔を空けて形成されていることが好ましい。 The multiple third contact regions 80 face the first dummy trench structure 61 in the second direction Y in the region on the third connection surface 10C side relative to the first mesa portion 71. The multiple third contact regions 80 are formed at intervals along each second dummy trench structure 62 so that the first mesa portion 71 is located between two adjacent third contact regions 80. It is preferable that the multiple third contact regions 80 are formed at intervals in the first direction X from the first mesa portion 71 so as not to face the first mesa portion 71.
　たとえば、第１方向Ｘに関して、第１メサ部７１および第３コンタクト領域８０の間の距離は、第３コンタクト領域８０の長さ未満であることが好ましい。第１メサ部７１および第３コンタクト領域８０の間の距離は、前述の第７幅Ｗ７未満であることが好ましい。第１メサ部７１および第３コンタクト領域８０の間の距離は、第１メサ部７１の幅（第５間隔Ｉ５）未満であることが特に好ましい。 For example, in the first direction X, it is preferable that the distance between the first mesa portion 71 and the third contact region 80 is less than the length of the third contact region 80. It is preferable that the distance between the first mesa portion 71 and the third contact region 80 is less than the seventh width W7 described above. It is particularly preferable that the distance between the first mesa portion 71 and the third contact region 80 is less than the width of the first mesa portion 71 (the fifth interval I5).
　複数の第３コンタクト領域８０は、第１メサ部７１および第２メサ部７２の間の範囲に形成された少なくとも１つ（この例では１つ）の最外の第３コンタクト領域８０を含む。最外の第３コンタクト領域８０は、第２方向Ｙに第１トレンチ抵抗構造４２に対向している。最外の第３コンタクト領域８０は、最外の第２コンタクト領域７９と共に第２メサ部７２を挟み込んでいる。 The multiple third contact regions 80 include at least one (in this example, one) outermost third contact region 80 formed in the range between the first mesa portion 71 and the second mesa portion 72. The outermost third contact region 80 faces the first trench resistor structure 42 in the second direction Y. The outermost third contact region 80, together with the outermost second contact region 79, sandwiches the second mesa portion 72.
　最外の第３コンタクト領域８０は、第１メサ部７１および第２メサ部７２から第１方向Ｘに間隔を空けて形成されていることが好ましい。つまり、最外の第３コンタクト領域８０は、第２方向Ｙに第１トレンチ抵抗構造４２に対向し、第２方向Ｙに第１ダミートレンチ構造６１に対向していないことが好ましい。 The outermost third contact region 80 is preferably formed at a distance in the first direction X from the first mesa portion 71 and the second mesa portion 72. In other words, the outermost third contact region 80 preferably faces the first trench resistor structure 42 in the second direction Y, but does not face the first dummy trench structure 61 in the second direction Y.
　たとえば、第１方向Ｘに関して、第２メサ部７２および第３コンタクト領域８０の間の距離は、第３コンタクト領域８０の長さ未満であることが好ましい。第２メサ部７２および第３コンタクト領域８０の間の距離は、前述の第７幅Ｗ７未満であることが好ましい。 For example, in the first direction X, the distance between the second mesa portion 72 and the third contact region 80 is preferably less than the length of the third contact region 80. The distance between the second mesa portion 72 and the third contact region 80 is preferably less than the aforementioned seventh width W7.
　第２メサ部７２および最外の第３コンタクト領域８０の間の距離は、第２メサ部７２の幅（第７間隔Ｉ７）未満であることが特に好ましい。第２メサ部７２を挟んで隣り合う最外の第２コンタクト領域７９および最外の第３コンタクト領域８０の間の距離は、第１メサ部７１を挟んで隣り合う２つの第３コンタクト領域８０の間の距離とほぼ等しいことが好ましい。 It is particularly preferable that the distance between the second mesa portion 72 and the outermost third contact region 80 is less than the width (seventh interval I7) of the second mesa portion 72. It is preferable that the distance between the outermost second contact region 79 and the outermost third contact region 80 adjacent to each other across the second mesa portion 72 is approximately equal to the distance between two adjacent third contact regions 80 across the first mesa portion 71.
　１つの第２ダミートレンチ構造６２に沿う複数の第３コンタクト領域８０は、他の第２ダミートレンチ構造６２に沿う複数の第３コンタクト領域８０に第２方向Ｙに対向している。つまり、複数の第３コンタクト領域８０は、この形態では、平面視において全体として第１方向Ｘおよび第２方向Ｙに間隔を空けて行列状に配列されている。この場合、複数の第３コンタクト領域８０は、複数の第２コンタクト領域７９と共に行列状に配列されていてもよい。また、複数の第３コンタクト領域８０は、複数の第１コンタクト領域３８と共に行列状に配列されていてもよい。 The multiple third contact regions 80 along one second dummy trench structure 62 face the multiple third contact regions 80 along the other second dummy trench structures 62 in the second direction Y. That is, in this embodiment, the multiple third contact regions 80 are arranged in a matrix with gaps in the first direction X and the second direction Y as a whole in a plan view. In this case, the multiple third contact regions 80 may be arranged in a matrix with the multiple second contact regions 79. The multiple third contact regions 80 may also be arranged in a matrix with the multiple first contact regions 38.
　１つの第２ダミートレンチ構造６２に沿う複数の第３コンタクト領域８０は、他の第２ダミートレンチ構造６２に沿う複数の第３コンタクト領域８０の間の領域に第２方向Ｙに対向するように第１方向Ｘにずれて配列されていてもよい。つまり、複数の第３コンタクト領域８０は、平面視において全体として第１方向Ｘおよび第２方向Ｙに間隔を空けて千鳥状に配列されていてもよい。この場合、複数の第３コンタクト領域８０は、複数の第２コンタクト領域７９と共に千鳥状に配列されていてもよい。また、複数の第３コンタクト領域８０は、複数の第１コンタクト領域３８と共に千鳥状に配列されていてもよい。 The third contact regions 80 along one second dummy trench structure 62 may be arranged offset in the first direction X so as to face the second direction Y in a region between the third contact regions 80 along the other second dummy trench structure 62. In other words, the third contact regions 80 may be arranged in a staggered manner with intervals in the first direction X and the second direction Y as a whole in a plan view. In this case, the third contact regions 80 may be arranged in a staggered manner together with the second contact regions 79. The third contact regions 80 may also be arranged in a staggered manner together with the first contact regions 38.
　図１３を参照して、半導体装置１は、第１終端領域１５Ａにおいて第１主面３（活性面８）に形成された終端ダミー構造８５を含む。終端ダミー構造８５は、ゲート抵抗４０の近傍における局所的な電界集中を緩和し、耐圧（たとえばブレークダウン電圧）を向上させることを１つの目的として活性面８（第１終端領域１５Ａ）に組み込まれている。終端ダミー構造８５の有無は任意であり、終端ダミー構造８５を備えない形態が採用されてもよい。 Referring to FIG. 13, the semiconductor device 1 includes a termination dummy structure 85 formed on the first main surface 3 (active surface 8) in the first termination region 15A. The termination dummy structure 85 is incorporated in the active surface 8 (first termination region 15A) for one purpose of alleviating local electric field concentration in the vicinity of the gate resistor 40 and improving the breakdown voltage (e.g., breakdown voltage). The presence or absence of the termination dummy structure 85 is optional, and a configuration not including the termination dummy structure 85 may be adopted.
　終端ダミー構造８５は、ゲート抵抗４０に対して第１側面５Ａ側（第１接続面１０Ａ側）の領域に配置されている。終端ダミー構造８５は、活性面８の終縁部に形成されている。終端ダミー構造８５は、第２方向Ｙにゲート抵抗４０およびダミー構造５５に対向している。終端ダミー構造８５は、第２方向Ｙにゲート抵抗４０を挟んで活性領域１２に対向し、第２方向Ｙに第１ダミー構造５６を挟んで第１周縁領域１４Ａに対向し、第２方向Ｙに第２ダミー構造５７を挟んで第２周縁領域１４Ｂに対向している。 The termination dummy structure 85 is disposed in a region on the first side surface 5A side (first connection surface 10A side) of the gate resistor 40. The termination dummy structure 85 is formed at the end edge of the active surface 8. The termination dummy structure 85 faces the gate resistor 40 and the dummy structure 55 in the second direction Y. The termination dummy structure 85 faces the active region 12 across the gate resistor 40 in the second direction Y, faces the first peripheral region 14A across the first dummy structure 56 in the second direction Y, and faces the second peripheral region 14B across the second dummy structure 57 in the second direction Y.
　以下、図２４～図２６を参照して、終端ダミー構造８５が具体的に説明される。図２４は、終端ダミー構造８５のレイアウトを示す拡大平面図である。図２５は、終端ダミー構造８５のレイアウトを示す更なる拡大平面図である。図２６は、図２５に示すXXVI-XXVI線に沿う断面図である。 Below, the termination dummy structure 85 will be described in detail with reference to Figures 24 to 26. Figure 24 is an enlarged plan view showing the layout of the termination dummy structure 85. Figure 25 is a further enlarged plan view showing the layout of the termination dummy structure 85. Figure 26 is a cross-sectional view taken along line XXVI-XXVI shown in Figure 25.
　図２４～図２６を参照して、終端ダミー構造８５は、第１終端領域１５Ａに形成された少なくとも１つ（この形態では複数）のトレンチ終端構造８６を含む。複数のトレンチ終端構造８６には、第２電位としてのソース電位ＶＳが付与される。複数のトレンチ終端構造８６は、第１方向Ｘに延びる帯状にそれぞれ形成され、第２方向Ｙに間隔を空けて配列されている。複数のトレンチ終端構造８６は、第２方向Ｙに第１トレンチ抵抗構造４２および第１ダミートレンチ構造６１に対向している。 Referring to Figures 24 to 26, the termination dummy structure 85 includes at least one (in this embodiment, multiple) trench termination structures 86 formed in the first termination region 15A. A source potential VS is applied to the multiple trench termination structures 86 as a second potential. The multiple trench termination structures 86 are each formed in a band shape extending in the first direction X and are arranged at intervals in the second direction Y. The multiple trench termination structures 86 face the first trench resistor structure 42 and the first dummy trench structure 61 in the second direction Y.
　複数のトレンチ終端構造８６は、第３接続面１０Ｃおよび第４接続面１０Ｄのうちの少なくとも一方から露出している。トレンチ終端構造８６は、この形態では、第３接続面１０Ｃおよび第４接続面１０Ｄの双方を貫通し、第３接続面１０Ｃおよび第４接続面１０Ｄの双方から露出している。複数のトレンチ終端構造８６は、第１半導体領域６に至るようにボディ領域１７を貫通している。複数のトレンチ終端構造８６は、第１半導体領域６の底部から活性面８側に間隔を空けて形成されている。 The multiple trench termination structures 86 are exposed from at least one of the third connection surface 10C and the fourth connection surface 10D. In this embodiment, the trench termination structure 86 penetrates both the third connection surface 10C and the fourth connection surface 10D and is exposed from both the third connection surface 10C and the fourth connection surface 10D. The multiple trench termination structures 86 penetrate the body region 17 to reach the first semiconductor region 6. The multiple trench termination structures 86 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.
　以下、１つのトレンチ終端構造８６が説明される。トレンチ終端構造８６は、第２方向Ｙに第８幅Ｗ８を有し、法線方向Ｚに第８深さＤ８を有している。第８幅Ｗ８は、前述の第５幅Ｗ５（第２幅Ｗ２）とほぼ等しいことが好ましい。第８幅Ｗ８は、０．１μｍ以上３μｍ以下であってもよい。第８幅Ｗ８は、０．５μｍ以上２μｍ以下であることが好ましい。 Below, one trench termination structure 86 is described. The trench termination structure 86 has an eighth width W8 in the second direction Y and an eighth depth D8 in the normal direction Z. The eighth width W8 is preferably approximately equal to the fifth width W5 (second width W2) described above. The eighth width W8 may be 0.1 μm or more and 3 μm or less. The eighth width W8 is preferably 0.5 μm or more and 2 μm or less.
　第８深さＤ８は、前述の第４深さＤ４（第１深さＤ１）以上である。第８深さＤ８は、この形態では、第４深さＤ４（第１深さＤ１）よりも大きい。第８深さＤ８は、第４深さＤ４（第１深さＤ１）の１．５倍以上３倍以下であることが好ましい。第８深さＤ８は、この形態では、前述の第５深さＤ５（第２深さＤ２）とほぼ等しい。第８深さＤ８は、外周面９の外周深さＤＯとほぼ等しい。第８深さＤ８は、０．５μｍ以上５μｍ以下であってもよい。第８深さＤ８は、２．５μｍ以下であることが特に好ましい。 The eighth depth D8 is equal to or greater than the fourth depth D4 (first depth D1) described above. In this embodiment, the eighth depth D8 is greater than the fourth depth D4 (first depth D1). It is preferable that the eighth depth D8 is 1.5 to 3 times the fourth depth D4 (first depth D1). In this embodiment, the eighth depth D8 is approximately equal to the fifth depth D5 (second depth D2) described above. The eighth depth D8 is approximately equal to the outer circumferential depth DO of the outer circumferential surface 9. The eighth depth D8 may be 0.5 μm to 5 μm. It is particularly preferable that the eighth depth D8 is 2.5 μm or less.
　複数のトレンチ終端構造８６は、第２方向Ｙに互いに第８間隔Ｉ８を空けて配置されている。第８間隔Ｉ８は、第８幅Ｗ８の０．５倍以上２倍以下であることが好ましい。第８間隔Ｉ８は、第８幅Ｗ８未満であることが特に好ましい。第８幅Ｗ８は、前述の第４間隔Ｉ４（第１間隔Ｉ１）とほぼ等しいことが好ましい。第８幅Ｗ８は、０．１μｍ以上２．５μｍ以下であってもよい。第８幅Ｗ８は、０．５μｍ以上１．５μｍ以下であることが好ましい。 The multiple trench termination structures 86 are arranged at an eighth interval I8 from each other in the second direction Y. The eighth interval I8 is preferably 0.5 to 2 times the eighth width W8. It is particularly preferable that the eighth interval I8 is less than the eighth width W8. It is preferable that the eighth width W8 is approximately equal to the aforementioned fourth interval I4 (first interval I1). The eighth width W8 may be 0.1 μm to 2.5 μm. It is preferable that the eighth width W8 is 0.5 μm to 1.5 μm.
　ゲート抵抗４０側の最内のトレンチ終端構造８６は、この形態では、第２方向Ｙに最外の第１トレンチ抵抗構造４２に隣り合うように最外の第１トレンチ抵抗構造４２から前述の第４間隔Ｉ４を空けて配置されている。また、最内のトレンチ終端構造８６は、この形態では、第２方向Ｙに最外の第１ダミートレンチ構造６１に隣り合うように最外の第１ダミートレンチ構造６１から前述の第６間隔Ｉ６を空けて配置されている。 In this embodiment, the innermost trench termination structure 86 on the gate resistor 40 side is disposed adjacent to the outermost first trench resistance structure 42 in the second direction Y, with the aforementioned fourth interval I4 between them. Also, in this embodiment, the innermost trench termination structure 86 is disposed adjacent to the outermost first dummy trench structure 61 in the second direction Y, with the aforementioned sixth interval I6 between them.
　トレンチ終端構造８６は、終端トレンチ８７、終端絶縁膜８８および終端埋設電極８９を含む。終端トレンチ８７は、活性面８に形成され、トレンチ終端構造８６の壁面を区画している。終端トレンチ８７の側壁は、第３接続面１０Ｃに連通している。終端トレンチ８７の底壁は、外周面９に連通している。 The trench termination structure 86 includes a termination trench 87, a termination insulating film 88, and a termination buried electrode 89. The termination trench 87 is formed in the active surface 8 and defines the wall surface of the trench termination structure 86. The side wall of the termination trench 87 is in communication with the third connection surface 10C. The bottom wall of the termination trench 87 is in communication with the outer peripheral surface 9.
　終端絶縁膜８８は、終端トレンチ８７の壁面を被覆し、活性面８において主面絶縁膜１６に接続されている。終端絶縁膜８８は、第３接続面１０Ｃの連通部および外周面９の連通部において主面絶縁膜１６に接続されている。終端絶縁膜８８は、酸化シリコン膜、窒化シリコン膜および酸窒化シリコン膜のうちの少なくとも１つを含んでいてもよい。 The termination insulating film 88 covers the wall surface of the termination trench 87 and is connected to the main surface insulating film 16 at the active surface 8. The termination insulating film 88 is connected to the main surface insulating film 16 at the communicating portion of the third connection surface 10C and the communicating portion of the outer peripheral surface 9. The termination insulating film 88 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
　終端絶縁膜８８は、この形態では、酸化シリコン膜からなる単層構造を有している。終端絶縁膜８８は、チップ２の酸化物からなる酸化シリコン膜を含むことが特に好ましい。終端埋設電極８９は、終端絶縁膜８８を挟んで終端トレンチ８７に埋設されている。終端埋設電極８９は、導電性ポリシリコンを含んでいてもよい。 In this embodiment, the termination insulating film 88 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the termination insulating film 88 includes a silicon oxide film made of an oxide of the chip 2. The termination buried electrode 89 is embedded in the termination trench 87 with the termination insulating film 88 in between. The termination buried electrode 89 may include conductive polysilicon.
　半導体装置１は、第１終端領域１５Ａにおいて複数のトレンチ終端構造８６に沿う領域に形成されたｐ型の複数の第８ウェル領域９０を含む。第８ウェル領域９０は、この形態では、ボディ領域１７よりも高いｐ型不純物濃度を有している。むろん、第８ウェル領域９０のｐ型不純物濃度は、ボディ領域１７よりも低くてもよい。第８ウェル領域９０のｐ型不純物濃度は、第２ウェル領域３６（第１ウェル領域３５）のｐ型不純物濃度とほぼ等しいことが好ましい。 The semiconductor device 1 includes a plurality of p-type eighth well regions 90 formed in the first termination region 15A in a region along the plurality of trench termination structures 86. In this embodiment, the eighth well regions 90 have a higher p-type impurity concentration than the body region 17. Of course, the p-type impurity concentration of the eighth well regions 90 may be lower than the body region 17. It is preferable that the p-type impurity concentration of the eighth well regions 90 is approximately equal to the p-type impurity concentration of the second well region 36 (first well region 35).
　複数の第８ウェル領域９０は、隣り合うトレンチ終端構造８６から間隔を空けて対応するトレンチ終端構造８６の壁面を被覆し、活性面８の表層部においてボディ領域１７に電気的に接続されている。複数の第８ウェル領域９０は、平面視において対応するトレンチ終端構造８６に沿って帯状に延び、第３接続面１０Ｃおよび第４接続面１０Ｄから露出している。 The multiple eighth well regions 90 cover the wall surfaces of the corresponding trench termination structures 86 at intervals from the adjacent trench termination structures 86, and are electrically connected to the body region 17 at the surface portion of the active surface 8. The multiple eighth well regions 90 extend in a band shape along the corresponding trench termination structures 86 in a plan view, and are exposed from the third connection surface 10C and the fourth connection surface 10D.
　複数の第８ウェル領域９０は、第１半導体領域６の底部から活性面８側に間隔を空けて形成され、第１半導体領域６の一部を挟んで第２半導体領域７に対向している。複数の第８ウェル領域９０の底部は、複数の第１ウェル領域３５の底部の深さ位置に対して第１半導体領域６の底部側に位置している。複数の第８ウェル領域９０の底部は、複数の第２ウェル領域３６の底部とほぼ等しい深さに形成されている。複数の第８ウェル領域９０は、第１半導体領域６とｐｎ接合部を形成している。 The multiple eighth well regions 90 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 across a portion of the first semiconductor region 6. The bottoms of the multiple eighth well regions 90 are located on the bottom side of the first semiconductor region 6 relative to the depth position of the bottoms of the multiple first well regions 35. The bottoms of the multiple eighth well regions 90 are formed at a depth approximately equal to the bottoms of the multiple second well regions 36. The multiple eighth well regions 90 form pn junctions with the first semiconductor region 6.
　図４を再度参照して、半導体装置１は、第２終端領域１５Ｂにおいて第１主面３（活性面８）に形成されたダミー構造５５および終端ダミー構造８５を含む。半導体装置１は、第２終端領域１５Ｂにおいてゲート抵抗４０を含まない。第２終端領域１５Ｂ側のダミー構造５５は、活性領域１２に対して第４側面５Ｄ側（第４接続面１０Ｄ側）の領域に配置され、第２方向Ｙに活性領域１２および周縁領域１４に対向している。 Referring again to FIG. 4, the semiconductor device 1 includes a dummy structure 55 and a termination dummy structure 85 formed on the first main surface 3 (active surface 8) in the second termination region 15B. The semiconductor device 1 does not include a gate resistor 40 in the second termination region 15B. The dummy structure 55 on the second termination region 15B side is disposed in a region on the fourth side surface 5D side (fourth connection surface 10D side) of the active region 12, and faces the active region 12 and the peripheral region 14 in the second direction Y.
　第２終端領域１５Ｂ側のダミー構造５５は、第１終端領域１５Ａ側の第１ダミー構造５６と同様、複数のダミートレンチ構造６０（複数の第１ダミートレンチ構造６１および複数の第２ダミートレンチ構造６２）を含む。第２終端領域１５Ｂ側の複数のダミートレンチ構造６０は、第３接続面１０Ｃおよび第４接続面１０Ｄの双方を貫通し、第３接続面１０Ｃおよび第４接続面１０Ｄの双方から露出している。その他、第２終端領域１５Ｂ側のダミー構造５５の構成は、第１終端領域１５Ａ側のダミー構造５５（第１ダミー構造５６）の構成と同様である。 The dummy structure 55 on the second termination region 15B side includes multiple dummy trench structures 60 (multiple first dummy trench structures 61 and multiple second dummy trench structures 62), similar to the first dummy structure 56 on the first termination region 15A side. The multiple dummy trench structures 60 on the second termination region 15B side penetrate both the third connection surface 10C and the fourth connection surface 10D, and are exposed from both the third connection surface 10C and the fourth connection surface 10D. Otherwise, the configuration of the dummy structure 55 on the second termination region 15B side is similar to the configuration of the dummy structure 55 (first dummy structure 56) on the first termination region 15A side.
　第２終端領域１５Ｂ側の終端ダミー構造８５は、第１終端領域１５Ａ側の終端ダミー構造８５の構成と同様の構成を有している。第２終端領域１５Ｂ側の終端ダミー構造８５の他の説明については第１終端領域１５Ａ側の終端ダミー構造８５の説明が適用される。 The termination dummy structure 85 on the second termination region 15B side has a configuration similar to the configuration of the termination dummy structure 85 on the first termination region 15A side. For other descriptions of the termination dummy structure 85 on the second termination region 15B side, the description of the termination dummy structure 85 on the first termination region 15A side applies.
　具体的な図示は省略されるが、半導体装置１は、第２終端領域１５Ｂにおいても複数の第６ウェル領域７７、複数の第７ウェル領域７８、複数の第２コンタクト領域７９および複数の第８ウェル領域９０を含む。第２終端領域１５Ｂ側の第６ウェル領域７７、第７ウェル領域７８、第２コンタクト領域７９および第８ウェル領域９０の説明については、第１終端領域１５Ａ側の第６ウェル領域７７、第７ウェル領域７８、第２コンタクト領域７９および第８ウェル領域９０の説明が適用される。 Although specific illustrations are omitted, the semiconductor device 1 also includes a plurality of sixth well regions 77, a plurality of seventh well regions 78, a plurality of second contact regions 79, and a plurality of eighth well regions 90 in the second termination region 15B. The explanations of the sixth well region 77, the seventh well region 78, the second contact region 79, and the eighth well region 90 on the second termination region 15B side are the same as those of the sixth well region 77, the seventh well region 78, the second contact region 79, and the eighth well region 90 on the first termination region 15A side.
　次に、図２８の断面図を参照して、外周領域１３の構造が説明される。図２８を参照して、半導体装置１は、外周面９の表層部に形成されたｐ型のアウターウェル領域９１を含む。アウターウェル領域９１は、第１コンタクト領域３８よりも低いｐ型不純物濃度を有している。 Next, the structure of the peripheral region 13 will be described with reference to the cross-sectional view of FIG. 28. Referring to FIG. 28, the semiconductor device 1 includes a p-type outer well region 91 formed in the surface layer of the peripheral surface 9. The outer well region 91 has a lower p-type impurity concentration than the first contact region 38.
　アウターウェル領域９１のｐ型不純物濃度は、この形態では、ボディ領域１７よりも高い。むろん、アウターウェル領域９１のｐ型不純物濃度は、ボディ領域１７よりも低くてもよい。アウターウェル領域９１は、第１ウェル領域３５（第２ウェル領域３６）とほぼ等しいｐ型不純物濃度を有していることが好ましい。 In this embodiment, the p-type impurity concentration of the outer well region 91 is higher than that of the body region 17. Of course, the p-type impurity concentration of the outer well region 91 may be lower than that of the body region 17. It is preferable that the outer well region 91 has a p-type impurity concentration approximately equal to that of the first well region 35 (second well region 36).
　アウターウェル領域９１は、平面視において外周面９の周縁（第１～第４側面５Ａ～５Ｄ）から活性面８側に間隔を空けて形成され、活性面８に沿って帯状に延びている。アウターウェル領域９１は、この形態では、平面視において活性面８を取り囲む環状（具体的には四角環状）に形成されている。アウターウェル領域９１は、外周面９の表層部から第１～第４接続面１０Ａ～１０Ｄの表層部に向けて延び、第１～第４接続面１０Ａ～１０Ｄを被覆している。 The outer well region 91 is formed at a distance from the periphery of the outer peripheral surface 9 (first to fourth side surfaces 5A to 5D) toward the active surface 8 in a plan view, and extends in a band shape along the active surface 8. In this embodiment, the outer well region 91 is formed in a ring shape (specifically, a square ring shape) that surrounds the active surface 8 in a plan view. The outer well region 91 extends from the surface layer of the outer peripheral surface 9 toward the surface layers of the first to fourth connection surfaces 10A to 10D, and covers the first to fourth connection surfaces 10A to 10D.
　アウターウェル領域９１は、活性面８の表層部においてボディ領域１７に電気的に接続されている。アウターウェル領域９１は、第３接続面１０Ｃ（第４接続面１０Ｄ）および第１トレンチソース構造２５の連通部において第２ウェル領域３６に接続されている。アウターウェル領域９１は、第３接続面１０Ｃ（第４接続面１０Ｄ）および第２トレンチソース構造３０の連通部において第３ウェル領域３７に接続されている。 The outer well region 91 is electrically connected to the body region 17 at the surface portion of the active surface 8. The outer well region 91 is connected to the second well region 36 at the third connection surface 10C (fourth connection surface 10D) and the communication portion of the first trench source structure 25. The outer well region 91 is connected to the third well region 37 at the communication portion of the third connection surface 10C (fourth connection surface 10D) and the second trench source structure 30.
　アウターウェル領域９１は、第３接続面１０Ｃ（第４接続面１０Ｄ）および第１ダミートレンチ構造６１の連通部において第６ウェル領域７７に接続されている。アウターウェル領域９１は、第３接続面１０Ｃ（第４接続面１０Ｄ）および第２ダミートレンチ構造６２の連通部において第７ウェル領域７８に接続されている。アウターウェル領域９１は、第３接続面１０Ｃ（第４接続面１０Ｄ）およびトレンチ終端構造８６の連通部において第８ウェル領域９０に接続されている。 The outer well region 91 is connected to the sixth well region 77 at the third connection surface 10C (fourth connection surface 10D) and the communication portion of the first dummy trench structure 61. The outer well region 91 is connected to the seventh well region 78 at the communication portion of the third connection surface 10C (fourth connection surface 10D) and the second dummy trench structure 62. The outer well region 91 is connected to the eighth well region 90 at the communication portion of the third connection surface 10C (fourth connection surface 10D) and the trench termination structure 86.
　アウターウェル領域９１は、第１半導体領域６の底部から外周面９側に間隔を空けて形成され、第１半導体領域６の一部を挟んで第２半導体領域７に対向している。アウターウェル領域９１は、第１トレンチソース構造２５（第２トレンチ抵抗構造４３）の底壁よりも第１半導体領域６の底部側に位置している。アウターウェル領域９１の底部は、第１コンタクト領域３８の底部よりも第１半導体領域６の底部側に位置している。アウターウェル領域９１の底部は、第２ウェル領域３６の底部とほぼ等しい深さ位置に形成されていることが好ましい。アウターウェル領域９１は、第１半導体領域６とｐｎ接合部を形成している。 The outer well region 91 is formed at a distance from the bottom of the first semiconductor region 6 toward the outer circumferential surface 9, and faces the second semiconductor region 7 across a portion of the first semiconductor region 6. The outer well region 91 is located closer to the bottom of the first semiconductor region 6 than the bottom wall of the first trench source structure 25 (second trench resistor structure 43). The bottom of the outer well region 91 is located closer to the bottom of the first semiconductor region 6 than the bottom of the first contact region 38. It is preferable that the bottom of the outer well region 91 is formed at a depth position approximately equal to the bottom of the second well region 36. The outer well region 91 forms a pn junction with the first semiconductor region 6.
　半導体装置１は、アウターウェル領域９１の表層部に形成されたｐ型のアウターコンタクト領域９２を含む。アウターコンタクト領域９２は、ボディ領域１７よりも高いｐ型不純物濃度を有している。アウターコンタクト領域９２のｐ型不純物濃度は、アウターウェル領域９１よりも高い。アウターコンタクト領域９２のｐ型不純物濃度は、第１コンタクト領域３８（第２コンタクト領域７９）のｐ型不純物濃度とほぼ等しいことが好ましい。 The semiconductor device 1 includes a p-type outer contact region 92 formed in a surface layer of the outer well region 91. The outer contact region 92 has a higher p-type impurity concentration than the body region 17. The p-type impurity concentration of the outer contact region 92 is higher than that of the outer well region 91. It is preferable that the p-type impurity concentration of the outer contact region 92 is approximately equal to the p-type impurity concentration of the first contact region 38 (second contact region 79).
　アウターコンタクト領域９２は、平面視において活性面８の周縁（第１～第４接続面１０Ａ～１０Ｄ）および外周面９の周縁（第１～第４側面５Ａ～５Ｄ）から間隔を空けてアウターウェル領域９１の表層部に形成され、活性面８に沿って延びる帯状に形成されている。アウターコンタクト領域９２は、この形態では、平面視において活性面８を取り囲む環状（具体的には四角環状）に形成されている。 The outer contact region 92 is formed in the surface layer of the outer well region 91 at a distance from the periphery of the active surface 8 (first to fourth connection surfaces 10A to 10D) and the periphery of the outer peripheral surface 9 (first to fourth side surfaces 5A to 5D) in a plan view, and is formed in a band shape extending along the active surface 8. In this embodiment, the outer contact region 92 is formed in a ring shape (specifically, a square ring shape) surrounding the active surface 8 in a plan view.
　アウターコンタクト領域９２は、アウターウェル領域９１の底部から外周面９側に間隔を空けて形成され、アウターウェル領域９１の一部を挟んで第１半導体領域６に対向している。アウターコンタクト領域９２は、第１トレンチソース構造２５（第２トレンチ抵抗構造４３）の底壁よりも第１半導体領域６の底部側に位置している。アウターコンタクト領域９２の底部は、第１コンタクト領域３８（第２コンタクト領域７９）の底部とほぼ等しい深さ位置に形成されていることが好ましい。 The outer contact region 92 is formed at a distance from the bottom of the outer well region 91 toward the outer peripheral surface 9, and faces the first semiconductor region 6 across a portion of the outer well region 91. The outer contact region 92 is located closer to the bottom of the first semiconductor region 6 than the bottom wall of the first trench source structure 25 (second trench resistor structure 43). It is preferable that the bottom of the outer contact region 92 is formed at a depth position approximately equal to the bottom of the first contact region 38 (second contact region 79).
　半導体装置１は、外周面９の表層部において外周面９の周縁およびアウターウェル領域９１の間の領域に形成された少なくとも１つ（好ましくは２個以上２０個以下）のｐ型のフィールド領域９３を含む。半導体装置１は、この形態では、４個のフィールド領域９３を含む。複数のフィールド領域９３は、電気的に浮遊状態に形成され、外周面９においてチップ２内の電界を緩和する。 The semiconductor device 1 includes at least one (preferably 2 to 20) p-type field region 93 formed in the surface layer of the outer peripheral surface 9 in a region between the periphery of the outer peripheral surface 9 and the outer well region 91. In this embodiment, the semiconductor device 1 includes four field regions 93. The multiple field regions 93 are formed in an electrically floating state and reduce the electric field within the chip 2 at the outer peripheral surface 9.
　フィールド領域９３の個数、幅、深さ、ｐ型不純物濃度等は任意であり、緩和すべき電界に応じて種々の値を取り得る。フィールド領域９３は、アウターコンタクト領域９２よりも低いｐ型不純物濃度を有していてもよい。フィールド領域９３は、アウターウェル領域９１よりも高いｐ型不純物濃度を有していてもよい。フィールド領域９３は、アウターウェル領域９１よりも低いｐ型不純物濃度を有していてもよい。 The number, width, depth, p-type impurity concentration, etc. of the field regions 93 are arbitrary and can take various values depending on the electric field to be relaxed. The field regions 93 may have a lower p-type impurity concentration than the outer contact region 92. The field regions 93 may have a higher p-type impurity concentration than the outer well region 91. The field regions 93 may have a lower p-type impurity concentration than the outer well region 91.
　複数のフィールド領域９３は、アウターウェル領域９１側から外周面９の周縁側に間隔を空けて配列されている。複数のフィールド領域９３は、平面視において活性面８に沿って延びる帯状に形成されている。複数のフィールド領域９３は、この形態では、平面視において活性面８を取り囲む環状（具体的には四角環状）に形成されている。 The multiple field regions 93 are arranged at intervals from the outer well region 91 side to the peripheral edge side of the outer peripheral surface 9. The multiple field regions 93 are formed in a band shape extending along the active surface 8 in a plan view. In this embodiment, the multiple field regions 93 are formed in a ring shape (specifically, a square ring shape) surrounding the active surface 8 in a plan view.
　複数のフィールド領域９３は、第１半導体領域６の底部から外周面９側に間隔を空けて形成され、第１半導体領域６の一部を挟んで第２半導体領域７に対向している。複数のフィールド領域９３は、第１トレンチソース構造２５の底壁よりも第１半導体領域６の底部側に位置している。複数のフィールド領域９３の底部は、第１コンタクト領域３８の底部よりも第１半導体領域６の底部側に位置している。複数のフィールド領域９３の底部は、第２ウェル領域３６の底部とほぼ等しい深さ位置に形成されていてもよい。 The multiple field regions 93 are formed at intervals from the bottom of the first semiconductor region 6 toward the outer circumferential surface 9, and face the second semiconductor region 7 across a portion of the first semiconductor region 6. The multiple field regions 93 are located closer to the bottom of the first semiconductor region 6 than the bottom wall of the first trench source structure 25. The bottoms of the multiple field regions 93 are located closer to the bottom of the first semiconductor region 6 than the bottom of the first contact region 38. The bottoms of the multiple field regions 93 may be formed at a depth position approximately equal to the bottom of the second well region 36.
　半導体装置１は、第１～第４接続面１０Ａ～１０Ｄのうちの少なくとも１つを被覆するように外周面９の上に形成されたサイドウォール配線９５を含む。サイドウォール配線９５は、具体的には、主面絶縁膜１６の上に配置されている。サイドウォール配線９５は、活性面８および外周面９の間に形成された段差を緩和するサイドウォール構造としても機能する。 The semiconductor device 1 includes a sidewall wiring 95 formed on the outer peripheral surface 9 so as to cover at least one of the first to fourth connection surfaces 10A to 10D. Specifically, the sidewall wiring 95 is disposed on the main surface insulating film 16. The sidewall wiring 95 also functions as a sidewall structure that reduces the step formed between the active surface 8 and the outer peripheral surface 9.
　サイドウォール配線９５は、少なくとも第３接続面１０Ｃおよび第４接続面１０Ｄのいずれか一方に沿って延びる帯状に形成されていることが好ましい。サイドウォール配線９５は、この形態では、平面視において活性面８を取り囲むように第１～第４接続面１０Ａ～１０Ｄに沿って延びる環状（具体的には四角環状）に形成されている。サイドウォール配線９５のうち活性面８の四隅を被覆する部分は、外周面９側に向かう湾曲状に形成されている。 The sidewall wiring 95 is preferably formed in a band shape extending along at least one of the third connection surface 10C and the fourth connection surface 10D. In this embodiment, the sidewall wiring 95 is formed in a ring shape (specifically, a square ring shape) extending along the first to fourth connection surfaces 10A to 10D so as to surround the active surface 8 in a plan view. The portions of the sidewall wiring 95 that cover the four corners of the active surface 8 are formed in a curved shape toward the outer circumferential surface 9.
　サイドウォール配線９５は、外周面９に沿って膜状に延びる部分、および、第１～第４接続面１０Ａ～１０Ｄに沿って膜状に延びる部分を含む。サイドウォール配線９５のうち外周面９の上に位置する部分は、活性面８に対して外周面９側の領域において外周面９を被覆していてもよい。サイドウォール配線９５のうち外周面９の上に位置する部分は、活性台地１１の厚さ（外周深さＤＯ）未満の厚さを有していてもよい。 The sidewall wiring 95 includes a portion that extends in a film-like manner along the outer peripheral surface 9, and a portion that extends in a film-like manner along the first to fourth connection surfaces 10A to 10D. The portion of the sidewall wiring 95 located on the outer peripheral surface 9 may cover the outer peripheral surface 9 in a region on the outer peripheral surface 9 side relative to the active surface 8. The portion of the sidewall wiring 95 located on the outer peripheral surface 9 may have a thickness less than the thickness of the active plateau 11 (outer peripheral depth DO).
　サイドウォール配線９５は、外周面９において主面絶縁膜１６を挟んでアウターウェル領域９１に対向している。サイドウォール配線９５は、主面絶縁膜１６を挟んでアウターコンタクト領域９２に対向していてもよい。サイドウォール配線９５は、この形態では、平面視においてフィールド領域９３から活性面８側に間隔を空けて形成されている。 The sidewall wiring 95 faces the outer well region 91 on the outer peripheral surface 9, with the main surface insulating film 16 in between. The sidewall wiring 95 may also face the outer contact region 92, with the main surface insulating film 16 in between. In this embodiment, the sidewall wiring 95 is formed at a distance from the field region 93 toward the active surface 8 in a plan view.
　サイドウォール配線９５は、第１～第４接続面１０Ａ～１０Ｄにおいて主面絶縁膜１６を挟んで第２ウェル領域３６、第３ウェル領域３７、第６ウェル領域７７、第７ウェル領域７８、第８ウェル領域９０およびアウターウェル領域９１に対向している。サイドウォール配線９５は、この形態では、主面絶縁膜１６を挟んでボディ領域１７にも対向している。 The sidewall wiring 95 faces the second well region 36, the third well region 37, the sixth well region 77, the seventh well region 78, the eighth well region 90, and the outer well region 91 at the first to fourth connection surfaces 10A to 10D, with the main surface insulating film 16 in between. In this embodiment, the sidewall wiring 95 also faces the body region 17, with the main surface insulating film 16 in between.
　サイドウォール配線９５は、第１～第４接続面１０Ａ～１０Ｄにおいて第１トレンチソース構造２５の露出部、第２トレンチソース構造３０の露出部、第１ダミートレンチ構造６１の露出部、第２ダミートレンチ構造６２の露出部およびトレンチ終端構造８６の露出部を被覆している。 The sidewall wiring 95 covers the exposed portion of the first trench source structure 25, the exposed portion of the second trench source structure 30, the exposed portion of the first dummy trench structure 61, the exposed portion of the second dummy trench structure 62, and the exposed portion of the trench termination structure 86 at the first to fourth connection surfaces 10A to 10D.
　これにより、サイドウォール配線９５は、第１トレンチソース構造２５、第２トレンチソース構造３０、第１ダミートレンチ構造６１、第２ダミートレンチ構造６２およびトレンチ終端構造８６に電気的に接続されている。つまり、サイドウォール配線９５は、外周面９側から接続対象にソース電位ＶＳを付与する。 As a result, the sidewall wiring 95 is electrically connected to the first trench source structure 25, the second trench source structure 30, the first dummy trench structure 61, the second dummy trench structure 62, and the trench termination structure 86. In other words, the sidewall wiring 95 applies the source potential VS to the connection target from the outer peripheral surface 9 side.
　サイドウォール配線９５は、第１～第４接続面１０Ａ～１０Ｄのうちの少なくとも１つから活性面８の縁部の上に乗り上げたオーバラップ部９６を有している。オーバラップ部９６は、平面視において活性面８を膜状に被覆し、活性面８の縁部に沿って延びる帯状に形成されている。オーバラップ部９６は、この形態では、平面視において活性面８の内方部を取り囲む環状（具体的には四角環状）に形成されている。 The sidewall wiring 95 has an overlapping portion 96 that extends from at least one of the first to fourth connection surfaces 10A to 10D onto the edge of the active surface 8. The overlapping portion 96 covers the active surface 8 in a film-like manner in a plan view, and is formed in a band shape extending along the edge of the active surface 8. In this form, the overlapping portion 96 is formed in a ring shape (specifically, a square ring shape) that surrounds the inner part of the active surface 8 in a plan view.
　オーバラップ部９６は、活性面８の上おいて第１トレンチソース構造２５、第２トレンチソース構造３０、第１ダミートレンチ構造６１、第２ダミートレンチ構造６２およびトレンチ終端構造８６に電気的に接続されている。 The overlap portion 96 is electrically connected to the first trench source structure 25, the second trench source structure 30, the first dummy trench structure 61, the second dummy trench structure 62 and the trench termination structure 86 on the active surface 8.
　サイドウォール配線９５は、この形態では、導電性ポリシリコンを含み、第１ソース埋設電極２８、第２ソース埋設電極３３、第１ダミー埋設電極６５、第２ダミー埋設電極６８および終端埋設電極８９と一体的に形成されている。むろん、サイドウォール配線９５は、第１ソース埋設電極２８、第２ソース埋設電極３３、第１ダミー埋設電極６５、第２ダミー埋設電極６８および終端埋設電極８９とは別体的に形成されていてもよい。 In this embodiment, the sidewall wiring 95 includes conductive polysilicon and is formed integrally with the first source buried electrode 28, the second source buried electrode 33, the first dummy buried electrode 65, the second dummy buried electrode 68, and the termination buried electrode 89. Of course, the sidewall wiring 95 may be formed separately from the first source buried electrode 28, the second source buried electrode 33, the first dummy buried electrode 65, the second dummy buried electrode 68, and the termination buried electrode 89.
　半導体装置１は、主面絶縁膜１６を被覆する層間絶縁膜９９を含む。層間絶縁膜９９は、主面絶縁膜１６を挟んで活性面８、外周面９および第１～第４接続面１０Ａ～１０Ｄを被覆している。層間絶縁膜９９は、活性面８においてトレンチゲート構造２０、第１トレンチソース構造２５、第２トレンチソース構造３０、第１トレンチ抵抗構造４２、第２トレンチ抵抗構造４３、第１ダミートレンチ構造６１、第２ダミートレンチ構造６２およびトレンチ終端構造８６を被覆している。 The semiconductor device 1 includes an interlayer insulating film 99 that covers the main surface insulating film 16. The interlayer insulating film 99 covers the active surface 8, the outer peripheral surface 9, and the first to fourth connection surfaces 10A to 10D with the main surface insulating film 16 in between. The interlayer insulating film 99 covers the trench gate structure 20, the first trench source structure 25, the second trench source structure 30, the first trench resistor structure 42, the second trench resistor structure 43, the first dummy trench structure 61, the second dummy trench structure 62, and the trench termination structure 86 on the active surface 8.
　層間絶縁膜９９は、第１終端領域１５Ａにおいて抵抗膜５０を被覆し、抵抗膜５０を挟んで複数のトレンチ抵抗構造４１を被覆している。層間絶縁膜９９は、外周面９において主面絶縁膜１６を挟んでアウターウェル領域９１、アウターコンタクト領域９２および複数のフィールド領域９３を被覆している。層間絶縁膜９９は、第１～第４接続面１０Ａ～１０Ｄにおいてサイドウォール配線９５を被覆している。 The interlayer insulating film 99 covers the resistive film 50 in the first termination region 15A, and covers the multiple trench resistance structures 41 with the resistive film 50 in between. The interlayer insulating film 99 covers the outer well region 91, the outer contact region 92, and the multiple field regions 93 with the main surface insulating film 16 in between at the outer peripheral surface 9. The interlayer insulating film 99 covers the sidewall wiring 95 at the first to fourth connection surfaces 10A to 10D.
　層間絶縁膜９９は、この形態では、第１～第４側面５Ａ～５Ｄに連なっている。むろん、層間絶縁膜９９の壁部は、外周面９の周縁から内方に間隔を空けて形成され、外周面９の周縁部から第１半導体領域６を露出させていてもよい。層間絶縁膜９９は、酸化シリコン膜、窒化シリコン膜および酸窒化シリコン膜のうちの少なくとも１つを含んでいてもよい。層間絶縁膜９９は、この形態では、酸化シリコン膜を含む。 In this embodiment, the interlayer insulating film 99 is continuous with the first to fourth side surfaces 5A to 5D. Of course, the wall portion of the interlayer insulating film 99 may be formed at a distance inward from the periphery of the outer peripheral surface 9, exposing the first semiconductor region 6 from the periphery of the outer peripheral surface 9. The interlayer insulating film 99 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the interlayer insulating film 99 includes a silicon oxide film.
　図１～図１３を参照して、半導体装置１は、層間絶縁膜９９の上に配置されたゲート電極１００を含む。ゲート電極１００は、ゲート抵抗４０の抵抗値よりも低い抵抗値を有している。具体的には、ゲート電極１００は、トレンチ抵抗構造４１の抵抗値よりも低い抵抗値を有している。また、ゲート電極１００は、抵抗膜５０の抵抗値よりも低い抵抗値を有している。 Referring to Figures 1 to 13, the semiconductor device 1 includes a gate electrode 100 disposed on an interlayer insulating film 99. The gate electrode 100 has a resistance value lower than the resistance value of the gate resistor 40. Specifically, the gate electrode 100 has a resistance value lower than the resistance value of the trench resistor structure 41. The gate electrode 100 also has a resistance value lower than the resistance value of the resistive film 50.
　ゲート電極１００は、抵抗膜５０よりも厚いことが好ましい。ゲート電極１００は、層間絶縁膜９９よりも厚いことが好ましい。ゲート電極１００は、０．５μｍ以上１０μｍ以下の厚さを有していてもよい。ゲート電極１００の厚さは、１μｍ以上５μｍ以下であることが好ましい。 The gate electrode 100 is preferably thicker than the resistive film 50. The gate electrode 100 is preferably thicker than the interlayer insulating film 99. The gate electrode 100 may have a thickness of 0.5 μm or more and 10 μm or less. The thickness of the gate electrode 100 is preferably 1 μm or more and 5 μm or less.
　ゲート電極１００は、Ｔｉ膜、ＴｉＮ膜、Ｗ膜、Ａｌ膜、Ｃｕ膜、Ａｌ合金膜、Ｃｕ合金膜および導電性ポリシリコン膜のうちの少なくとも１種を含んでいてもよい。ゲート電極１００は、純Ｃｕ膜（純度が９９％以上のＣｕ膜）、純Ａｌ膜（純度が９９％以上のＡｌ膜）、ＡｌＣｕ合金膜、ＡｌＳｉ合金膜、および、ＡｌＳｉＣｕ合金膜のうちの少なくとも１つを含んでいてもよい。ゲート電極１００は、この形態では、チップ２側からこの順に積層されたＴｉ膜およびＡｌ合金膜（この形態ではＡｌＳｉＣｕ合金膜）を含む積層構造を有している。ゲート電極１００は、「ゲートメタル」と称されてもよい。 The gate electrode 100 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film. The gate electrode 100 may include at least one of a pure Cu film (Cu film with a purity of 99% or more), a pure Al film (Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this embodiment, the gate electrode 100 has a layered structure including a Ti film and an Al alloy film (an AlSiCu alloy film in this embodiment) layered in this order from the chip 2 side. The gate electrode 100 may be referred to as a "gate metal".
　ゲート電極１００は、この形態では、ゲートパッド１０１、ゲート配線１０２およびゲートサブパッド１０３を含む。ゲートパッド１０１には、外部からゲート電位ＶＧが付与される。ゲートパッド１０１は、この形態では、平面視において第１接続面１０Ａの中央部に沿う領域に配置されている。 In this embodiment, the gate electrode 100 includes a gate pad 101, a gate wiring 102, and a gate subpad 103. A gate potential VG is applied to the gate pad 101 from the outside. In this embodiment, the gate pad 101 is disposed in a region along the center of the first connection surface 10A in a plan view.
　ゲートパッド１０１は、この形態では、活性面８の周縁から間隔を空けて活性面８の内方部の上に配置され、外周面９の上に配置されていない。ゲートパッド１０１は、平面視において活性領域１２および第１終端領域１５Ａに重なる領域に配置されている。ゲートパッド１０１は、活性領域１２において層間絶縁膜９９を挟んで複数のトレンチゲート構造２０および複数の第１トレンチソース構造２５を被覆している。 In this embodiment, the gate pad 101 is disposed on the inner portion of the active surface 8 at a distance from the periphery of the active surface 8, and is not disposed on the outer peripheral surface 9. The gate pad 101 is disposed in a region that overlaps the active region 12 and the first termination region 15A in a plan view. The gate pad 101 covers the multiple trench gate structures 20 and the multiple first trench source structures 25 in the active region 12 with the interlayer insulating film 99 in between.
　ゲートパッド１０１は、平面視においてゲート抵抗４０に重なる領域に配置されている。ゲートパッド１０１は、この形態では、平面視においてダミー構造５５および終端ダミー構造８５から間隔を空けて形成されている。むろん、ゲートパッド１０１は、平面視においてダミー構造５５および終端ダミー構造８５のいずれか一方または双方に重なる領域に配置されていてもよい。 The gate pad 101 is disposed in a region that overlaps the gate resistor 40 in a planar view. In this embodiment, the gate pad 101 is formed at a distance from the dummy structure 55 and the termination dummy structure 85 in a planar view. Of course, the gate pad 101 may be disposed in a region that overlaps with either or both of the dummy structure 55 and the termination dummy structure 85 in a planar view.
　ゲートパッド１０１は、第１終端領域１５Ａにおいて層間絶縁膜９９を貫通してゲート抵抗４０に電気的に接続されている。具体的には、ゲートパッド１０１は、層間絶縁膜９９を貫通して抵抗膜５０に接続されている。ゲートパッド１０１は、この形態では、層間絶縁膜９９を貫通して抵抗膜５０の中央部に接続されている。 The gate pad 101 is electrically connected to the gate resistor 40 through the interlayer insulating film 99 in the first termination region 15A. Specifically, the gate pad 101 is connected to the resistive film 50 through the interlayer insulating film 99. In this embodiment, the gate pad 101 is connected to the center of the resistive film 50 through the interlayer insulating film 99.
　ゲートパッド１０１は、抵抗膜５０を挟んで１つまたは複数（この形態では複数）のトレンチ抵抗構造４１に対向している。ゲートパッド１０１は、この形態では、抵抗膜５０を挟んで複数の第１トレンチ抵抗構造４２および複数の第２トレンチ抵抗構造４３に対向している。 The gate pad 101 faces one or more (in this embodiment, multiple) trench resistance structures 41 across the resistive film 50. In this embodiment, the gate pad 101 faces multiple first trench resistance structures 42 and multiple second trench resistance structures 43 across the resistive film 50.
　ゲートパッド１０１は、この形態では、パッド本体部１０４および引き出し部１０５を含む。パッド本体部１０４は、外部からゲート電位ＶＧが付与される部分である。パッド本体部１０４は、この形態では、層間絶縁膜９９のうち活性領域１２を被覆する部分の上に配置され、平面視において第２方向Ｙにゲート抵抗４０に対向している。 In this embodiment, the gate pad 101 includes a pad body 104 and an extraction portion 105. The pad body 104 is a portion to which a gate potential VG is applied from the outside. In this embodiment, the pad body 104 is disposed on a portion of the interlayer insulating film 99 that covers the active region 12, and faces the gate resistor 40 in the second direction Y in a plan view.
　パッド本体部１０４は、層間絶縁膜９９を挟んで複数のトレンチゲート構造２０および複数の第１トレンチソース構造２５を被覆している。パッド本体部１０４は、この形態では、第１方向Ｘに関してゲート抵抗４０（トレンチゲート構造２０）よりも幅広に形成されている。 The pad body 104 covers the multiple trench gate structures 20 and the multiple first trench source structures 25 with the interlayer insulating film 99 in between. In this embodiment, the pad body 104 is formed to be wider than the gate resistor 40 (trench gate structure 20) in the first direction X.
　パッド本体部１０４は、この形態では、平面視において四角形状に形成されている。パッド本体部１０４は、第１主面３の平面積の２５％以下の平面積を有していることが好ましい。パッド本体部１０４の平面積は、第１主面３の平面積の１０％以下であることが好ましい。 In this embodiment, the pad main body 104 is formed in a rectangular shape in a plan view. It is preferable that the pad main body 104 has a plan area that is 25% or less of the plan area of the first main surface 3. It is preferable that the plan area of the pad main body 104 is 10% or less of the plan area of the first main surface 3.
　引き出し部１０５は、パッド本体部１０４をゲート抵抗４０に電気的に接続する部分である。引き出し部１０５は、パッド本体部１０４から層間絶縁膜９９のうちゲート抵抗４０を被覆する部分の上に帯状に引き出されている。引き出し部１０５は、この形態では、第１方向Ｘに関してパッド本体部１０４よりも幅狭に形成されている。具体的には、引き出し部１０５は、第１方向Ｘに関してゲート抵抗４０（トレンチゲート構造２０）よりも幅狭に形成されている。 The draw-out portion 105 is a portion that electrically connects the pad body portion 104 to the gate resistor 40. The draw-out portion 105 is drawn out in a strip shape from the pad body portion 104 onto a portion of the interlayer insulating film 99 that covers the gate resistor 40. In this embodiment, the draw-out portion 105 is formed narrower than the pad body portion 104 in the first direction X. Specifically, the draw-out portion 105 is formed narrower than the gate resistor 40 (trench gate structure 20) in the first direction X.
　引き出し部１０５は、層間絶縁膜９９に形成された第１抵抗開口１０６を介してゲート抵抗４０に接続されている。具体的には、引き出し部１０５は、第１抵抗開口１０６内において抵抗膜５０に接続されている。つまり、引き出し部１０５は、抵抗膜５０を介して複数のトレンチ抵抗構造４１に電気的に接続されている。 The lead-out portion 105 is connected to the gate resistor 40 via a first resistor opening 106 formed in the interlayer insulating film 99. Specifically, the lead-out portion 105 is connected to the resistive film 50 within the first resistor opening 106. In other words, the lead-out portion 105 is electrically connected to the multiple trench resistor structures 41 via the resistive film 50.
　これにより、パッド本体部１０４は、引き出し部１０５を介して複数のトレンチ抵抗構造４１および抵抗膜５０に電気的に接続されている。引き出し部１０５は、抵抗膜５０を挟んで１つまたは複数（この形態では複数）のトレンチ抵抗構造４１に対向している。引き出し部１０５は、この形態では、抵抗膜５０を挟んで複数の第１トレンチ抵抗構造４２および複数の第２トレンチ抵抗構造４３に対向している。 As a result, the pad main body 104 is electrically connected to the multiple trench resistance structures 41 and the resistive film 50 via the lead-out portion 105. The lead-out portion 105 faces one or multiple (multiple in this embodiment) trench resistance structures 41 across the resistive film 50. In this embodiment, the lead-out portion 105 faces multiple first trench resistance structures 42 and multiple second trench resistance structures 43 across the resistive film 50.
　ゲート配線１０２は、ゲートパッド１０１に付与されたゲート電位ＶＧを複数のトレンチゲート構造２０に伝達するように第１終端領域１５Ａから活性領域１２に向けて選択的に引き回されている。ゲート配線１０２は、この形態では、活性面８の周縁から間隔を空けて活性面８の内方部の上に配置され、外周面９の上に配置されていない。 The gate wiring 102 is selectively routed from the first termination region 15A toward the active region 12 so as to transmit the gate potential VG applied to the gate pad 101 to the multiple trench gate structures 20. In this embodiment, the gate wiring 102 is disposed on the inner portion of the active surface 8 at a distance from the periphery of the active surface 8, and is not disposed on the outer periphery 9.
　ゲート配線１０２は、この形態では、第１終端領域１５Ａにおいてゲートパッド１０１から間隔を空けて層間絶縁膜９９の上に配置されている。ゲート配線１０２は、ゲートパッド１０１とは異なる位置で層間絶縁膜９９を貫通してゲート抵抗４０に電気的に接続されている。具体的には、ゲート配線１０２は、層間絶縁膜９９を貫通して抵抗膜５０に接続されている。これにより、ゲート配線１０２は、複数のトレンチ抵抗構造４１および抵抗膜５０を介してゲートパッド１０１に電気的に接続されている。 In this embodiment, the gate wiring 102 is disposed on the interlayer insulating film 99 at a distance from the gate pad 101 in the first termination region 15A. The gate wiring 102 penetrates the interlayer insulating film 99 at a position different from the gate pad 101 and is electrically connected to the gate resistor 40. Specifically, the gate wiring 102 penetrates the interlayer insulating film 99 and is connected to the resistive film 50. As a result, the gate wiring 102 is electrically connected to the gate pad 101 via the multiple trench resistor structures 41 and the resistive film 50.
　ゲート配線１０２は、抵抗膜５０を挟んで１つまたは複数（この形態では複数）のトレンチ抵抗構造４１に対向している。ゲート配線１０２は、この形態では、抵抗膜５０を挟んで複数の第１トレンチ抵抗構造４２および複数の第２トレンチ抵抗構造４３に対向している。ゲート配線１０２は、活性領域１２において複数のトレンチゲート構造２０に交差（具体的には直交）するようにライン状に延び、層間絶縁膜９９を貫通して複数のトレンチゲート構造２０に電気的に接続されている。 The gate wiring 102 faces one or more (multiple in this embodiment) trench resistance structures 41 across the resistive film 50. In this embodiment, the gate wiring 102 faces a plurality of first trench resistance structures 42 and a plurality of second trench resistance structures 43 across the resistive film 50. The gate wiring 102 extends in a line shape so as to intersect (specifically, perpendicular to) the multiple trench gate structures 20 in the active region 12, and is electrically connected to the multiple trench gate structures 20 by penetrating the interlayer insulating film 99.
　ゲート配線１０２は、この形態では、第１ゲート配線１０２Ａ、第２ゲート配線１０２Ｂおよび第３ゲート配線１０２Ｃを含む。第１ゲート配線１０２Ａは、ゲートパッド１０１に対して第３接続面１０Ｃ側の領域に配置され、第１接続面１０Ａおよび第３接続面１０Ｃに沿ってライン状に延びている。第１ゲート配線１０２Ａは、第１終端領域１５Ａにおいてゲート抵抗４０を介してゲートパッド１０１に電気的に接続され、活性領域１２において複数のトレンチゲート構造２０に電気的に接続されている。 In this embodiment, the gate wiring 102 includes a first gate wiring 102A, a second gate wiring 102B, and a third gate wiring 102C. The first gate wiring 102A is disposed in a region on the third connection surface 10C side of the gate pad 101, and extends in a line along the first connection surface 10A and the third connection surface 10C. The first gate wiring 102A is electrically connected to the gate pad 101 via a gate resistor 40 in the first termination region 15A, and is electrically connected to a plurality of trench gate structures 20 in the active region 12.
　具体的には、第１ゲート配線１０２Ａは、第１終端領域１５Ａにおいてゲート抵抗４０およびダミー構造５５（第１ダミー構造５６）を被覆するように第１方向Ｘにライン状に延びている。第１ゲート配線１０２Ａは、ゲートパッド１０１から間隔を空けて層間絶縁膜９９のうちゲート抵抗４０を被覆する部分の上に配置されている。 Specifically, the first gate wiring 102A extends in a line in the first direction X so as to cover the gate resistor 40 and the dummy structure 55 (first dummy structure 56) in the first termination region 15A. The first gate wiring 102A is disposed on a portion of the interlayer insulating film 99 that covers the gate resistor 40, spaced apart from the gate pad 101.
　第１ゲート配線１０２Ａは、第１抵抗開口１０６から間隔を空けて層間絶縁膜９９に形成された第２抵抗開口１０７を介してゲート抵抗４０に接続されている。第１ゲート配線１０２Ａは、ゲートパッド１０１の接続位置から間隔を空けてゲート抵抗４０の一端部側（第３接続面１０Ｃ側）の領域に接続されている。 The first gate wiring 102A is connected to the gate resistor 40 via a second resistor opening 107 formed in the interlayer insulating film 99 at a distance from the first resistor opening 106. The first gate wiring 102A is connected to a region on one end side (the third connection surface 10C side) of the gate resistor 40 at a distance from the connection position of the gate pad 101.
　第１ゲート配線１０２Ａは、第２抵抗開口１０７内において抵抗膜５０に接続されている。つまり、第１ゲート配線１０２Ａは、抵抗膜５０を介して複数のトレンチ抵抗構造４１に電気的に接続されている。第１ゲート配線１０２Ａは、抵抗膜５０を挟んで１つまたは複数（この形態では複数）のトレンチ抵抗構造４１に対向している。第１ゲート配線１０２Ａは、この形態では、抵抗膜５０を挟んで複数の第１トレンチ抵抗構造４２および複数の第２トレンチ抵抗構造４３に対向している。 The first gate wiring 102A is connected to the resistive film 50 within the second resistive opening 107. That is, the first gate wiring 102A is electrically connected to the multiple trench resistance structures 41 via the resistive film 50. The first gate wiring 102A faces one or multiple (multiple in this embodiment) trench resistance structures 41 across the resistive film 50. In this embodiment, the first gate wiring 102A faces multiple first trench resistance structures 42 and multiple second trench resistance structures 43 across the resistive film 50.
　第１ゲート配線１０２Ａは、活性領域１２において複数のトレンチゲート構造２０に交差（具体的には直交）するように第２方向Ｙにライン状に延びている。第１ゲート配線１０２Ａは、層間絶縁膜９９に形成された複数のゲート開口１０８を介して複数のゲート接続電極膜３９に電気的に接続されている。これにより、第１ゲート配線１０２Ａは、複数のゲート接続電極膜３９を介して複数のトレンチゲート構造２０に電気的に接続されている。第１ゲート配線１０２Ａのうち、活性領域１２において第２方向Ｙにライン状に延びている部分は、本開示における「周縁ゲート配線」の一例である。 The first gate wiring 102A extends in a line in the second direction Y so as to intersect (specifically, perpendicularly) with the multiple trench gate structures 20 in the active region 12. The first gate wiring 102A is electrically connected to the multiple gate connection electrode films 39 via the multiple gate openings 108 formed in the interlayer insulating film 99. As a result, the first gate wiring 102A is electrically connected to the multiple trench gate structures 20 via the multiple gate connection electrode films 39. The portion of the first gate wiring 102A that extends in a line in the second direction Y in the active region 12 is an example of a "peripheral gate wiring" in this disclosure.
　ゲート接続電極膜３９に対する第１ゲート配線１０２Ａの接続高さ位置は、抵抗膜５０に対する第１ゲート配線１０２Ａの接続高さ位置とほぼ等しくてもよい。むろん、ゲート接続電極膜３９に対する第１ゲート配線１０２Ａの接続高さ位置は、抵抗膜５０に対する第２ゲート配線１０２Ｂの接続高さ位置よりも活性面８側に位置していてもよい。また、ゲート接続電極膜３９に対する第１ゲート配線１０２Ａの接続高さ位置は、抵抗膜５０に対する第２ゲート配線１０２Ｂの接続高さ位置よりも上方に位置していてもよい。 The connection height position of the first gate wiring 102A to the gate connection electrode film 39 may be approximately equal to the connection height position of the first gate wiring 102A to the resistive film 50. Of course, the connection height position of the first gate wiring 102A to the gate connection electrode film 39 may be located closer to the active surface 8 than the connection height position of the second gate wiring 102B to the resistive film 50. Also, the connection height position of the first gate wiring 102A to the gate connection electrode film 39 may be located higher than the connection height position of the second gate wiring 102B to the resistive film 50.
　第２ゲート配線１０２Ｂは、ゲートパッド１０１に対して第４接続面１０Ｄ側の領域に配置され、第１接続面１０Ａおよび第４接続面１０Ｄに沿ってライン状に延びている。第２ゲート配線１０２Ｂは、第１終端領域１５Ａにおいてゲート抵抗４０を介してゲートパッド１０１に電気的に接続され、活性領域１２において複数のトレンチゲート構造２０に電気的に接続されている。第２ゲート配線１０２Ｂは、この形態では、第１ゲート配線１０２Ａに電気的に接続された複数のトレンチゲート構造２０に電気的に接続されている。 The second gate wiring 102B is disposed in a region on the fourth connection surface 10D side of the gate pad 101, and extends in a line along the first connection surface 10A and the fourth connection surface 10D. The second gate wiring 102B is electrically connected to the gate pad 101 via the gate resistor 40 in the first termination region 15A, and is electrically connected to a plurality of trench gate structures 20 in the active region 12. In this embodiment, the second gate wiring 102B is electrically connected to a plurality of trench gate structures 20 electrically connected to the first gate wiring 102A.
　具体的には、第２ゲート配線１０２Ｂは、第１終端領域１５Ａにおいてゲート抵抗４０およびダミー構造５５（第２ダミー構造５７）を被覆するように第１方向Ｘにライン状に延びている。第２ゲート配線１０２Ｂは、ゲートパッド１０１から間隔を空けて層間絶縁膜９９のうちゲート抵抗４０を被覆する部分の上に配置されている。 Specifically, the second gate wiring 102B extends in a line in the first direction X so as to cover the gate resistor 40 and the dummy structure 55 (second dummy structure 57) in the first termination region 15A. The second gate wiring 102B is disposed on a portion of the interlayer insulating film 99 that covers the gate resistor 40, spaced apart from the gate pad 101.
　第２ゲート配線１０２Ｂは、第１抵抗開口１０６および第２抵抗開口１０７から間隔を空けて層間絶縁膜９９に形成された第３抵抗開口１０９を介してゲート抵抗４０に接続されている。第２ゲート配線１０２Ｂは、ゲートパッド１０１の接続位置から間隔を空けてゲート抵抗４０の他端部側（第４接続面１０Ｄ側）の領域に接続されている。 The second gate wiring 102B is connected to the gate resistor 40 via a third resistor opening 109 formed in the interlayer insulating film 99 at a distance from the first resistor opening 106 and the second resistor opening 107. The second gate wiring 102B is connected to a region on the other end side (the fourth connection surface 10D side) of the gate resistor 40 at a distance from the connection position of the gate pad 101.
　第２ゲート配線１０２Ｂは、第３抵抗開口１０９内において抵抗膜５０に接続されている。つまり、第２ゲート配線１０２Ｂは、抵抗膜５０を介して複数のトレンチ抵抗構造４１に電気的に接続されている。第２ゲート配線１０２Ｂは、抵抗膜５０を挟んで１つまたは複数（この形態では複数）のトレンチ抵抗構造４１に対向している。第２ゲート配線１０２Ｂは、この形態では、抵抗膜５０を挟んで複数の第１トレンチ抵抗構造４２および複数の第２トレンチ抵抗構造４３に対向している。 The second gate wiring 102B is connected to the resistive film 50 within the third resistance opening 109. That is, the second gate wiring 102B is electrically connected to the multiple trench resistance structures 41 via the resistive film 50. The second gate wiring 102B faces one or multiple (multiple in this embodiment) trench resistance structures 41 across the resistive film 50. In this embodiment, the second gate wiring 102B faces multiple first trench resistance structures 42 and multiple second trench resistance structures 43 across the resistive film 50.
　第２ゲート配線１０２Ｂは、活性領域１２において複数のトレンチゲート構造２０に交差（具体的には直交）するように第２方向Ｙにライン状に延びている。第２ゲート配線１０２Ｂは、層間絶縁膜９９に形成された複数のゲート開口１０８を介して複数のゲート接続電極膜３９に電気的に接続されている。これにより、第２ゲート配線１０２Ｂは、複数のゲート接続電極膜３９を介して複数のトレンチゲート構造２０に電気的に接続されている。 The second gate wiring 102B extends in a line in the second direction Y so as to intersect (specifically, perpendicular to) the multiple trench gate structures 20 in the active region 12. The second gate wiring 102B is electrically connected to the multiple gate connection electrode films 39 via the multiple gate openings 108 formed in the interlayer insulating film 99. As a result, the second gate wiring 102B is electrically connected to the multiple trench gate structures 20 via the multiple gate connection electrode films 39.
　ゲート接続電極膜３９に対する第２ゲート配線１０２Ｂの接続高さ位置は、抵抗膜５０に対する第２ゲート配線１０２Ｂの接続高さ位置とほぼ等しくてもよい。むろん、ゲート接続電極膜３９に対する第２ゲート配線１０２Ｂの接続高さ位置は、抵抗膜５０に対する第２ゲート配線１０２Ｂの接続高さ位置よりも活性面８側に位置していてもよい。また、ゲート接続電極膜３９に対する第２ゲート配線１０２Ｂの接続高さ位置は、抵抗膜５０に対する第２ゲート配線１０２Ｂの接続高さ位置よりも上方に位置していてもよい。 The connection height position of the second gate wiring 102B to the gate connection electrode film 39 may be approximately equal to the connection height position of the second gate wiring 102B to the resistive film 50. Of course, the connection height position of the second gate wiring 102B to the gate connection electrode film 39 may be located closer to the active surface 8 than the connection height position of the second gate wiring 102B to the resistive film 50. Also, the connection height position of the second gate wiring 102B to the gate connection electrode film 39 may be located higher than the connection height position of the second gate wiring 102B to the resistive film 50.
　第３ゲート配線１０２Ｃは、ゲートパッド１０１に対して第２接続面１０Ｂ側の領域に配置され、ゲートパッド１０１および第２接続面１０Ｂの間の領域を第２方向Ｙに沿ってライン状に延びている。第３ゲート配線１０２Ｃは、この形態では、第１終端領域１５Ａにおいて第１ゲート配線１０２Ａおよび第２ゲート配線１０２Ｂに接続され、活性領域１２において複数のトレンチゲート構造２０に電気的に接続されている。 The third gate wiring 102C is disposed in a region on the second connection surface 10B side of the gate pad 101, and extends in a line shape along the second direction Y in the region between the gate pad 101 and the second connection surface 10B. In this embodiment, the third gate wiring 102C is connected to the first gate wiring 102A and the second gate wiring 102B in the first termination region 15A, and is electrically connected to a plurality of trench gate structures 20 in the active region 12.
　つまり、第３ゲート配線１０２Ｃは、第１ゲート配線１０２Ａを介してゲート抵抗４０に電気的に接続され、第２ゲート配線１０２Ｂを介してゲート抵抗４０に電気的に接続されている。第１ゲート配線１０２Ａのうちゲート抵抗４０に接続された部分および第２ゲート配線１０２Ｂのうちゲート抵抗４０に接続された部分は、第３ゲート配線１０２Ｃの一部とみなされてもよい。第３ゲート配線１０２Ｃは、この形態では、活性領域１２において第１ゲート配線１０２Ａおよび第２ゲート配線１０２Ｂに電気的に接続された複数のトレンチゲート構造２０に電気的に接続されている。 In other words, the third gate wiring 102C is electrically connected to the gate resistor 40 via the first gate wiring 102A, and is electrically connected to the gate resistor 40 via the second gate wiring 102B. The portion of the first gate wiring 102A connected to the gate resistor 40 and the portion of the second gate wiring 102B connected to the gate resistor 40 may be considered as part of the third gate wiring 102C. In this embodiment, the third gate wiring 102C is electrically connected to a plurality of trench gate structures 20 electrically connected to the first gate wiring 102A and the second gate wiring 102B in the active region 12.
　第３ゲート配線１０２Ｃは、ライン部１１０、第１分岐部１１１および第２分岐部１１２を含む。ライン部１１０は、ゲートパッド１０１および第２接続面１０Ｂの間の領域を第２方向Ｙに沿ってライン状に延びている。ライン部１１０は、ゲートパッド１０１側の第１端部および第２接続面１０Ｂ側の第２端部を有している。第１端部は、ゲートパッド１０１から第２接続面１０Ｂ側に間隔を空けて形成されている。第２端部は、第２接続面１０Ｂからゲートパッド１０１側に間隔を空けて形成されている。ライン部１１０は、本開示における「中央ゲート配線」の一例である。 The third gate wiring 102C includes a line portion 110, a first branch portion 111, and a second branch portion 112. The line portion 110 extends in a line shape along the second direction Y in the region between the gate pad 101 and the second connection surface 10B. The line portion 110 has a first end portion on the gate pad 101 side and a second end portion on the second connection surface 10B side. The first end portion is formed at a distance from the gate pad 101 to the second connection surface 10B side. The second end portion is formed at a distance from the second connection surface 10B to the gate pad 101 side. The line portion 110 is an example of a "central gate wiring" in this disclosure.
　ライン部１１０は、層間絶縁膜９９に形成された複数のゲート開口１０８を介して複数のトレンチゲート構造２０に電気的に接続されている。複数のトレンチゲート構造２０の内方部を被覆する複数のゲート接続電極膜３９が形成されていてもよい。この場合、ライン部１１０は、複数のゲート接続電極膜３９を介して複数のトレンチゲート構造２０に電気的に接続される。 The line portion 110 is electrically connected to the multiple trench gate structures 20 via multiple gate openings 108 formed in the interlayer insulating film 99. Multiple gate connection electrode films 39 may be formed to cover the inner portions of the multiple trench gate structures 20. In this case, the line portion 110 is electrically connected to the multiple trench gate structures 20 via the multiple gate connection electrode films 39.
　この場合、ゲート接続電極膜３９に対するライン部１１０の接続高さ位置は、抵抗膜５０に対する第１ゲート配線１０２Ａ（第２ゲート配線１０２Ｂ）の接続高さ位置とほぼ等しくてもよい。むろん、ゲート接続電極膜３９に対するライン部１１０の接続高さ位置は、抵抗膜５０に対する第２ゲート配線１０２Ｂの接続高さ位置よりも活性面８側に位置していてもよい。また、ゲート接続電極膜３９に対するライン部１１０の接続高さ位置は、抵抗膜５０に対する第２ゲート配線１０２Ｂの接続高さ位置よりも上方に位置していてもよい。 In this case, the connection height position of the line portion 110 to the gate connection electrode film 39 may be approximately equal to the connection height position of the first gate wiring 102A (second gate wiring 102B) to the resistive film 50. Of course, the connection height position of the line portion 110 to the gate connection electrode film 39 may be located closer to the active surface 8 than the connection height position of the second gate wiring 102B to the resistive film 50. Also, the connection height position of the line portion 110 to the gate connection electrode film 39 may be located higher than the connection height position of the second gate wiring 102B to the resistive film 50.
　第１分岐部１１１は、ライン部１１０および第１ゲート配線１０２Ａを接続している。第１分岐部１１１は、ライン部１１０の第１端部から一方側（第３接続面１０Ｃ側）に引き出され、ゲートパッド１０１に沿って帯状に延びている。第１分岐部１１１は、第１ゲート配線１０２Ａのうちダミー構造５５（第１ダミー構造５６）を被覆する部分に接続されている。 The first branch portion 111 connects the line portion 110 and the first gate wiring 102A. The first branch portion 111 is pulled out from the first end of the line portion 110 to one side (the third connection surface 10C side) and extends in a strip shape along the gate pad 101. The first branch portion 111 is connected to a portion of the first gate wiring 102A that covers the dummy structure 55 (first dummy structure 56).
　むろん、第１分岐部１１１は、第１ゲート配線１０２Ａのうちゲート抵抗４０を被覆する部分に接続されていてもよい。第１分岐部１１１は、第２方向Ｙに延びる部分において、層間絶縁膜９９に形成された複数のゲート開口１０８を介して複数のトレンチゲート構造２０に電気的に接続されている。第１分岐部１１１は、複数のゲート接続電極膜３９を介して複数のトレンチゲート構造２０に電気的に接続されてもよい。 Of course, the first branch portion 111 may be connected to a portion of the first gate wiring 102A that covers the gate resistor 40. In a portion extending in the second direction Y, the first branch portion 111 is electrically connected to a plurality of trench gate structures 20 via a plurality of gate openings 108 formed in the interlayer insulating film 99. The first branch portion 111 may be electrically connected to a plurality of trench gate structures 20 via a plurality of gate connection electrode films 39.
　第２分岐部１１２は、ライン部１１０および第２ゲート配線１０２Ｂを接続している。第２分岐部１１２は、ライン部１１０の第１端部から他方側（第４接続面１０Ｄ側）に引き出され、ゲートパッド１０１の周縁に沿って帯状に延びている。第２分岐部１１２は、第１方向Ｘにゲートパッド１０１を挟んで第１分岐部１１１に対向している。第２分岐部１１２は、第２ゲート配線１０２Ｂのうちダミー構造５５（第２ダミー構造５７）を被覆する部分に接続されている。 The second branch portion 112 connects the line portion 110 and the second gate wiring 102B. The second branch portion 112 is pulled out from the first end of the line portion 110 to the other side (the fourth connection surface 10D side) and extends in a band shape along the periphery of the gate pad 101. The second branch portion 112 faces the first branch portion 111 across the gate pad 101 in the first direction X. The second branch portion 112 is connected to a portion of the second gate wiring 102B that covers the dummy structure 55 (second dummy structure 57).
　むろん、第２分岐部１１２は、第２ゲート配線１０２Ｂのうちゲート抵抗４０を被覆する部分に接続されていてもよい。第２分岐部１１２は、第２方向Ｙに延びる部分において、層間絶縁膜９９に形成された複数のゲート開口１０８を介して複数のトレンチゲート構造２０に電気的に接続されている。第２分岐部１１２は、複数のゲート接続電極膜３９を介して複数のトレンチゲート構造２０に電気的に接続されてもよい。 Of course, the second branch portion 112 may be connected to a portion of the second gate wiring 102B that covers the gate resistor 40. In a portion extending in the second direction Y, the second branch portion 112 is electrically connected to a plurality of trench gate structures 20 via a plurality of gate openings 108 formed in the interlayer insulating film 99. The second branch portion 112 may be electrically connected to a plurality of trench gate structures 20 via a plurality of gate connection electrode films 39.
　ゲートサブパッド１０３は、ゲート抵抗４０を介してゲートパッド１０１に電気的に接続されるように層間絶縁膜９９の上に配置されている。ゲートサブパッド１０３は、この形態では、ゲートパッド１０１から第３接続面１０Ｃ側に間隔を空けて配置され、第１方向Ｘにゲートパッド１０１に対向している。 The gate subpad 103 is disposed on the interlayer insulating film 99 so as to be electrically connected to the gate pad 101 via the gate resistor 40. In this embodiment, the gate subpad 103 is disposed at a distance from the gate pad 101 toward the third connection surface 10C, and faces the gate pad 101 in the first direction X.
　ゲートサブパッド１０３は、平面視において第１終端領域１５Ａから間隔を空けて層間絶縁膜９９のうち活性領域１２を被覆する部分の上に配置されている。ゲートサブパッド１０３は、平面視において第２方向Ｙにダミー構造５５（第１ダミー構造５６）に対向している。 The gate subpad 103 is disposed on a portion of the interlayer insulating film 99 that covers the active region 12, spaced apart from the first termination region 15A in a plan view. The gate subpad 103 faces the dummy structure 55 (first dummy structure 56) in the second direction Y in a plan view.
　ゲートサブパッド１０３は、ゲートパッド１０１よりも幅狭に形成され、ゲート配線１０２よりも幅広に形成されている。ゲートサブパッド１０３は、層間絶縁膜９９を挟んで複数のトレンチゲート構造２０および複数の第１トレンチソース構造２５に対向している。ゲートサブパッド１０３は、この形態では、ゲート配線１０２に電気的に接続されている。ゲートサブパッド１０３は、この形態では、第３ゲート配線１０２Ｃ（第１分岐部１１１）に接続されている。ゲートサブパッド１０３は、第１～第３ゲート配線１０２Ａ～１０２Ｃの少なくとも１つに接続されていればよく、ゲートサブパッド１０３の配置箇所は任意である。 The gate subpad 103 is formed narrower than the gate pad 101 and wider than the gate wiring 102. The gate subpad 103 faces the multiple trench gate structures 20 and the multiple first trench source structures 25 across the interlayer insulating film 99. In this embodiment, the gate subpad 103 is electrically connected to the gate wiring 102. In this embodiment, the gate subpad 103 is connected to the third gate wiring 102C (first branch portion 111). The gate subpad 103 only needs to be connected to at least one of the first to third gate wirings 102A to 102C, and the location of the gate subpad 103 is arbitrary.
　以下、図１３に加えて図２７を参照して、ゲート電極１００およびゲート抵抗４０の接続形態が説明される。図２７は、ゲート電極１００およびゲート抵抗４０の接続形態を示す電気回路図である。図２７では、トレンチゲート構造２０がＭＩＳＦＥＴを示す回路記号によって示されている。 Below, the connection form of the gate electrode 100 and the gate resistor 40 will be described with reference to FIG. 27 in addition to FIG. 13. FIG. 27 is an electrical circuit diagram showing the connection form of the gate electrode 100 and the gate resistor 40. In FIG. 27, the trench gate structure 20 is shown by a circuit symbol indicating a MISFET.
　図１３および図２７を参照して、ゲート配線１０２は、ゲート抵抗４０を介してゲートパッド１０１に電気的に接続されている。ゲート抵抗４０は、この形態では、第１抵抗部Ｒ１および第２抵抗部Ｒ２によって構成された抵抗並列回路１１３を含む。第１抵抗部Ｒ１は、ゲート抵抗４０のうちゲートパッド１０１の接続部および第１ゲート配線１０２Ａの接続部の間に位置する部分によって形成されている。一方、第２抵抗部Ｒ２は、ゲート抵抗４０のうちゲートパッド１０１の接続部および第２ゲート配線１０２Ｂの接続部の間に位置する部分によって形成されている。 Referring to Figures 13 and 27, the gate wiring 102 is electrically connected to the gate pad 101 via the gate resistor 40. In this embodiment, the gate resistor 40 includes a resistive parallel circuit 113 composed of a first resistor portion R1 and a second resistor portion R2. The first resistor portion R1 is formed by a portion of the gate resistor 40 located between the connection portion of the gate pad 101 and the connection portion of the first gate wiring 102A. On the other hand, the second resistor portion R2 is formed by a portion of the gate resistor 40 located between the connection portion of the gate pad 101 and the connection portion of the second gate wiring 102B.
　つまり、第１ゲート配線１０２Ａは第１抵抗部Ｒ１を介してゲートパッド１０１に電気的に接続され、第２ゲート配線１０２Ｂは第２抵抗部Ｒ２を介してゲートパッド１０１に電気的に接続されている。第１抵抗部Ｒ１の抵抗値は、ゲートパッド１０１の接続部および第１ゲート配線１０２Ａの接続部の間の距離を増減させることにより調節される。 In other words, the first gate wiring 102A is electrically connected to the gate pad 101 via the first resistance portion R1, and the second gate wiring 102B is electrically connected to the gate pad 101 via the second resistance portion R2. The resistance value of the first resistance portion R1 is adjusted by increasing or decreasing the distance between the connection portion of the gate pad 101 and the connection portion of the first gate wiring 102A.
　第２抵抗部Ｒ２の抵抗値は、ゲートパッド１０１の接続部および第２ゲート配線１０２Ｂの接続部の間の距離を増減させることにより調節される。第２抵抗部Ｒ２の抵抗値は、第１抵抗部Ｒ１の抵抗値以上であってもよいし、第１抵抗部Ｒ１の抵抗値未満であってもよいし、第１抵抗部Ｒ１の抵抗値とほぼ等しくてもよい。 The resistance value of the second resistor R2 is adjusted by increasing or decreasing the distance between the connection part of the gate pad 101 and the connection part of the second gate wiring 102B. The resistance value of the second resistor R2 may be equal to or greater than the resistance value of the first resistor R1, may be less than the resistance value of the first resistor R1, or may be approximately equal to the resistance value of the first resistor R1.
　第２ゲート配線１０２Ｂは、この形態では、第１ゲート配線１０２Ａに電気的に接続されたトレンチゲート構造２０に電気的に接続されている。したがって、第２抵抗部Ｒ２が第１抵抗部Ｒ１に対して並列接続され、これによって抵抗並列回路１１３が形成される。この形態では、第３ゲート配線１０２Ｃが、第１ゲート配線１０２Ａおよび第２ゲート配線１０２Ｂに電気的に接続されたトレンチゲート構造２０に電気的に接続されている。 In this embodiment, the second gate wiring 102B is electrically connected to the trench gate structure 20 that is electrically connected to the first gate wiring 102A. Therefore, the second resistance portion R2 is connected in parallel to the first resistance portion R1, thereby forming a resistive parallel circuit 113. In this embodiment, the third gate wiring 102C is electrically connected to the trench gate structure 20 that is electrically connected to the first gate wiring 102A and the second gate wiring 102B.
　したがって、第１～第３ゲート配線１０２Ａ～１０２Ｃを含む１つのゲート配線１０２が、抵抗並列回路１１３およびトレンチゲート構造２０に電気的に接続されている。ゲート抵抗４０の抵抗値（つまり、ゲートパッド１０１およびゲート配線１０２の間の抵抗値）は、ゲートパッド１０１およびゲートサブパッド１０３の間の抵抗値を測定することによって間接的に測定される。 Therefore, one gate wiring 102 including the first to third gate wirings 102A to 102C is electrically connected to the resistive parallel circuit 113 and the trench gate structure 20. The resistance value of the gate resistor 40 (i.e., the resistance value between the gate pad 101 and the gate wiring 102) is indirectly measured by measuring the resistance value between the gate pad 101 and the gate subpad 103.
　ゲート抵抗４０は、スイッチング動作時におけるスイッチング速度を遅延させて、サージ電流を抑制する。つまり、ゲート抵抗４０は、サージ電流に起因するノイズを抑制する。ゲート抵抗４０は、第１主面３（活性面８）に形成されているため、半導体装置１に外付け接続されない。したがって、ゲート抵抗４０が第１主面３に組み込まれることによって、回路基板に実装される部品点数が削減される。 The gate resistor 40 suppresses surge currents by slowing down the switching speed during switching operations. In other words, the gate resistor 40 suppresses noise caused by surge currents. Because the gate resistor 40 is formed on the first main surface 3 (active surface 8), it is not externally connected to the semiconductor device 1. Therefore, by incorporating the gate resistor 40 into the first main surface 3, the number of components mounted on the circuit board is reduced.
　ゲート抵抗４０はチップ２の厚さ方向に組み込まれたトレンチ抵抗構造４１を含むため、第１主面３に対するゲート抵抗４０の専有面積は限定的になる。したがって、ゲート抵抗４０の導入に起因する活性領域１２の面積の縮小は抑制される。特に、ゲート抵抗４０は終端領域１５に配置されているため、活性領域１２の面積の縮小が適切に抑制される。 Since the gate resistor 40 includes a trench resistor structure 41 embedded in the thickness direction of the chip 2, the area occupied by the gate resistor 40 relative to the first main surface 3 is limited. Therefore, the reduction in the area of the active region 12 caused by the introduction of the gate resistor 40 is suppressed. In particular, since the gate resistor 40 is disposed in the termination region 15, the reduction in the area of the active region 12 is appropriately suppressed.
　ゲート抵抗４０は、この形態では、活性領域１２側の構成と同様の構成を有している。したがって、活性領域１２に対するゲート抵抗４０の電気的な影響が抑制され、ゲート抵抗４０に対する活性領域１２の電気的な影響が抑制される。これにより、活性領域１２側の電気的特性の変動が抑制され、ゲート抵抗４０側の電気的特性の変動が抑制される。 In this embodiment, the gate resistor 40 has a configuration similar to that of the active region 12. Therefore, the electrical influence of the gate resistor 40 on the active region 12 is suppressed, and the electrical influence of the active region 12 on the gate resistor 40 is suppressed. This suppresses fluctuations in the electrical characteristics on the active region 12 side, and suppresses fluctuations in the electrical characteristics on the gate resistor 40 side.
　ゲート抵抗４０は、必ずしも第１抵抗部Ｒ１および第２抵抗部Ｒ２を含む抵抗並列回路１１３を有している必要はない。したがって、ゲート抵抗４０は、第１抵抗部Ｒ１または第２抵抗部Ｒ２のみによって構成されていてもよい。このような形態は、ゲート抵抗４０に対するゲート配線１０２の接続形態を変更することによって達成される。 The gate resistor 40 does not necessarily have to have a resistive parallel circuit 113 including the first resistive portion R1 and the second resistive portion R2. Therefore, the gate resistor 40 may be composed of only the first resistive portion R1 or the second resistive portion R2. Such a configuration is achieved by changing the connection configuration of the gate wiring 102 to the gate resistor 40.
　たとえば、ゲート抵抗４０が第１抵抗部Ｒ１のみからなる場合には、ゲート配線１０２（第２ゲート配線１０２Ｂ）をゲート抵抗４０から電気的に切り離せばよい。また、ゲート抵抗４０が第２抵抗部Ｒ２のみからなる場合には、ゲート配線１０２（第１ゲート配線１０２Ａ）をゲート抵抗４０から電気的に切り離せばよい。ゲート配線１０２は、第１～第３ゲート配線１０２Ａ～１０２Ｃの全てを同時に含む必要はなく、第１～第３ゲート配線１０２Ａ～１０２Ｃのうちの少なくとも１つを含んでいればよい。 For example, if the gate resistor 40 consists only of the first resistance portion R1, the gate wiring 102 (second gate wiring 102B) can be electrically disconnected from the gate resistor 40. Also, if the gate resistor 40 consists only of the second resistance portion R2, the gate wiring 102 (first gate wiring 102A) can be electrically disconnected from the gate resistor 40. The gate wiring 102 does not need to include all of the first to third gate wirings 102A to 102C at the same time, but only needs to include at least one of the first to third gate wirings 102A to 102C.
　図１～図１３を参照して、半導体装置１は、ゲート電極１００から間隔を空けて層間絶縁膜９９の上に配置されたソース電極１２０を含む。ソース電極１２０は、ゲート抵抗４０の抵抗値よりも低い抵抗値を有している。ソース電極１２０は、抵抗膜５０よりも厚いことが好ましい。ソース電極１２０は、層間絶縁膜９９よりも厚いことが好ましい。ソース電極１２０は、０．５μｍ以上１０μｍ以下の厚さを有していてもよい。ソース電極１２０の厚さは、１μｍ以上５μｍ以下であることが好ましい。ソース電極１２０の厚さは、ゲート電極１００の厚さとほぼ等しいことが好ましい。 Referring to Figures 1 to 13, the semiconductor device 1 includes a source electrode 120 disposed on an interlayer insulating film 99 at a distance from the gate electrode 100. The source electrode 120 has a resistance value lower than that of the gate resistor 40. The source electrode 120 is preferably thicker than the resistive film 50. The source electrode 120 is preferably thicker than the interlayer insulating film 99. The source electrode 120 may have a thickness of 0.5 μm or more and 10 μm or less. The thickness of the source electrode 120 is preferably 1 μm or more and 5 μm or less. The thickness of the source electrode 120 is preferably approximately equal to the thickness of the gate electrode 100.
　ソース電極１２０は、Ｔｉ膜、ＴｉＮ膜、Ｗ膜、Ａｌ膜、Ｃｕ膜、Ａｌ合金膜、Ｃｕ合金膜および導電性ポリシリコン膜のうちの少なくとも１種を含んでいてもよい。ソース電極１２０は、純Ｃｕ膜（純度が９９％以上のＣｕ膜）、純Ａｌ膜（純度が９９％以上のＡｌ膜）、ＡｌＣｕ合金膜、ＡｌＳｉ合金膜、および、ＡｌＳｉＣｕ合金膜のうちの少なくとも１つを含んでいてもよい。ソース電極１２０は、この形態では、チップ２側からこの順に積層されたＴｉ膜およびＡｌ合金膜（この形態ではＡｌＳｉＣｕ合金膜）を含む積層構造を有している。ソース電極１２０は、「ソースメタル」と称されてもよい。 The source electrode 120 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film. The source electrode 120 may include at least one of a pure Cu film (Cu film with a purity of 99% or more), a pure Al film (Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this embodiment, the source electrode 120 has a layered structure including a Ti film and an Al alloy film (AlSiCu alloy film in this embodiment) layered in this order from the chip 2 side. The source electrode 120 may be referred to as a "source metal".
　ソース電極１２０は、この形態では、第１ソースパッド１２１、第２ソースパッド１２２、第１ソースサブパッド１２３、第２ソースサブパッド１２４およびソース配線１２５を含む。第１ソースパッド１２１には、外部からメインソース用のソース電位ＶＳが付与される。第１ソースパッド１２１は、層間絶縁膜９９のうち活性領域１２を被覆する部分の上において、第１ゲート配線１０２Ａおよび第３ゲート配線１０２Ｃの間の領域に配置されている。 In this embodiment, the source electrode 120 includes a first source pad 121, a second source pad 122, a first source sub-pad 123, a second source sub-pad 124, and a source wiring 125. A source potential VS for the main source is applied to the first source pad 121 from the outside. The first source pad 121 is disposed in the region between the first gate wiring 102A and the third gate wiring 102C on the portion of the interlayer insulating film 99 that covers the active region 12.
　第１ソースパッド１２１は、この形態では、平面視において周縁領域１４および終端領域１５から間隔を空けて活性領域１２を被覆している。むろん、第１ソースパッド１２１は、平面視において周縁領域１４および終端領域１５のいずれか一方または双方に重なる領域に配置されていてもよい。 In this embodiment, the first source pad 121 covers the active region 12 at a distance from the peripheral region 14 and the termination region 15 in a plan view. Of course, the first source pad 121 may be disposed in a region that overlaps with either or both of the peripheral region 14 and the termination region 15 in a plan view.
　第１ソースパッド１２１は、層間絶縁膜９９を挟んで複数のトレンチゲート構造２０に対向している。第１ソースパッド１２１は、層間絶縁膜９９に形成された複数のソース開口１２６を介して複数の第１トレンチソース構造２５、ソース領域１８および複数の第１コンタクト領域３８に電気的に接続されている。第１ソースパッド１２１は、ゲートパッド１０１の平面積よりも大きい平面積を有していることが好ましい。 The first source pad 121 faces the multiple trench gate structures 20 across the interlayer insulating film 99. The first source pad 121 is electrically connected to the multiple first trench source structures 25, the source region 18, and the multiple first contact regions 38 via multiple source openings 126 formed in the interlayer insulating film 99. The first source pad 121 preferably has a planar area larger than the planar area of the gate pad 101.
　第２ソースパッド１２２には、外部からメインソース用のソース電位ＶＳが付与される。第２ソースパッド１２２は、層間絶縁膜９９のうち活性領域１２を被覆する部分の上において、第２ゲート配線１０２Ｂおよび第３ゲート配線１０２Ｃの間の領域に配置されている。 The second source pad 122 is supplied with a source potential VS for the main source from the outside. The second source pad 122 is disposed in the region between the second gate wiring 102B and the third gate wiring 102C on the portion of the interlayer insulating film 99 that covers the active region 12.
　第２ソースパッド１２２は、この形態では、平面視において周縁領域１４および終端領域１５から間隔を空けて活性領域１２を被覆している。むろん、第２ソースパッド１２２は、平面視において周縁領域１４および終端領域１５のいずれか一方または双方に重なる領域に配置されていてもよい。第２ソースパッド１２２は、層間絶縁膜９９を挟んで複数のトレンチゲート構造２０に対向している。 In this embodiment, the second source pad 122 covers the active region 12 at a distance from the peripheral region 14 and the termination region 15 in a plan view. Of course, the second source pad 122 may be disposed in a region that overlaps with either or both of the peripheral region 14 and the termination region 15 in a plan view. The second source pad 122 faces the multiple trench gate structures 20 with the interlayer insulating film 99 interposed therebetween.
　第２ソースパッド１２２は、層間絶縁膜９９に形成された複数のソース開口１２６を介して複数の第１トレンチソース構造２５、ソース領域１８および複数の第１コンタクト領域３８に電気的に接続されている。第２ソースパッド１２２は、ゲートパッド１０１の平面積よりも大きい平面積を有していることが好ましい。 The second source pad 122 is electrically connected to the first trench source structures 25, the source region 18, and the first contact regions 38 through a plurality of source openings 126 formed in the interlayer insulating film 99. The second source pad 122 preferably has a planar area larger than the planar area of the gate pad 101.
　第１ソースサブパッド１２３には、外部からソースセンス用のソース電位ＶＳが付与される。第１ソースサブパッド１２３は、この形態では、層間絶縁膜９９のうち活性領域１２を被覆する部分の上において、ゲートパッド１０１および第１ゲート配線１０２Ａ（第３接続面１０Ｃ）の間の領域に配置されている。 The first source subpad 123 is supplied with a source potential VS for source sensing from the outside. In this embodiment, the first source subpad 123 is disposed in the region between the gate pad 101 and the first gate wiring 102A (third connection surface 10C) on the portion of the interlayer insulating film 99 that covers the active region 12.
　第１ソースサブパッド１２３は、第１ソースパッド１２１の平面積未満の平面積を有し、第１ソースパッド１２１と一体的に形成されている。第１ソースサブパッド１２３の平面積は、ゲートサブパッド１０３の平面積よりも大きいことが好ましい。第１ソースサブパッド１２３の平面積は、ゲートパッド１０１の平面積よりも大きいことが特に好ましい。 The first source subpad 123 has a planar area less than the planar area of the first source pad 121 and is formed integrally with the first source pad 121. It is preferable that the planar area of the first source subpad 123 is greater than the planar area of the gate subpad 103. It is particularly preferable that the planar area of the first source subpad 123 is greater than the planar area of the gate pad 101.
　第１ソースサブパッド１２３は、平面視において周縁領域１４および終端領域１５から間隔を空けて活性領域１２を被覆している。むろん、第１ソースサブパッド１２３は、平面視において周縁領域１４および終端領域１５のいずれか一方または双方に重なる領域に配置されていてもよい。 The first source subpad 123 covers the active region 12 at a distance from the peripheral region 14 and the termination region 15 in a plan view. Of course, the first source subpad 123 may be disposed in a region that overlaps with either or both of the peripheral region 14 and the termination region 15 in a plan view.
　第１ソースサブパッド１２３は、層間絶縁膜９９を挟んで複数のトレンチゲート構造２０に対向している。第１ソースサブパッド１２３は、層間絶縁膜９９に形成された複数のソース開口１２６を介して複数の第１トレンチソース構造２５、ソース領域１８および複数の第１コンタクト領域３８に電気的に接続されている。 The first source subpad 123 faces the multiple trench gate structures 20 across the interlayer insulating film 99. The first source subpad 123 is electrically connected to the multiple first trench source structures 25, the source region 18, and the multiple first contact regions 38 via multiple source openings 126 formed in the interlayer insulating film 99.
　第２ソースサブパッド１２４には、外部からソースセンス用のソース電位ＶＳが付与される。第２ソースサブパッド１２４は、この形態では、層間絶縁膜９９のうち活性領域１２を被覆する部分の上において、ゲートパッド１０１および第２ゲート配線１０２Ｂ（第４接続面１０Ｄ）の間の領域に配置されている。 The second source subpad 124 is supplied with a source potential VS for source sensing from the outside. In this embodiment, the second source subpad 124 is disposed in the region between the gate pad 101 and the second gate wiring 102B (fourth connection surface 10D) on the portion of the interlayer insulating film 99 that covers the active region 12.
　第２ソースサブパッド１２４は、この形態では、第２ソースパッド１２２の平面積未満の平面積を有し、第２ソースパッド１２２と一体的に形成されている。第２ソースサブパッド１２４の平面積は、ゲートサブパッド１０３の平面積よりも大きいことが好ましい。第２ソースサブパッド１２４の平面積は、ゲートパッド１０１の平面積よりも大きいことが特に好ましい。 In this embodiment, the second source subpad 124 has a plan area less than the plan area of the second source pad 122 and is formed integrally with the second source pad 122. It is preferable that the plan area of the second source subpad 124 is greater than the plan area of the gate subpad 103. It is particularly preferable that the plan area of the second source subpad 124 is greater than the plan area of the gate pad 101.
　第２ソースサブパッド１２４は、平面視において周縁領域１４および終端領域１５から間隔を空けて活性領域１２を被覆している。むろん、第２ソースサブパッド１２４は、平面視において周縁領域１４および終端領域１５のいずれか一方または双方に重なる領域に配置されていてもよい。第２ソースサブパッド１２４は、層間絶縁膜９９を挟んで複数のトレンチゲート構造２０に対向している。第２ソースサブパッド１２４は、層間絶縁膜９９に形成された複数のソース開口１２６を介して複数の第１トレンチソース構造２５、ソース領域１８および複数の第１コンタクト領域３８に電気的に接続されている。 The second source subpad 124 covers the active region 12 at a distance from the peripheral region 14 and the termination region 15 in a plan view. Of course, the second source subpad 124 may be disposed in a region overlapping either or both of the peripheral region 14 and the termination region 15 in a plan view. The second source subpad 124 faces the multiple trench gate structures 20 with the interlayer insulating film 99 in between. The second source subpad 124 is electrically connected to the multiple first trench source structures 25, the source region 18, and the multiple first contact regions 38 via the multiple source openings 126 formed in the interlayer insulating film 99.
　第１ソースパッド１２１、第２ソースパッド１２２、第１ソースサブパッド１２３、第２ソースサブパッド１２４の総平面積は、第１主面３の平面積の５０％以上９０％以下であることが好ましい。総平面積は、第１主面３の平面積の７５％以上であることが特に好ましい。 The total planar area of the first source pad 121, the second source pad 122, the first source sub-pad 123, and the second source sub-pad 124 is preferably 50% or more and 90% or less of the planar area of the first main surface 3. It is particularly preferable that the total planar area is 75% or more of the planar area of the first main surface 3.
　ソース配線１２５は、第１ソースパッド１２１および第２ソースパッド１２２に付与されたソース電位ＶＳを他の領域に伝達する。ソース配線１２５は、この形態では、ゲート配線１０２よりも外周領域１３側に位置するように第１ソースパッド１２１および第２ソースパッド１２２から引き出されている。 The source wiring 125 transmits the source potential VS applied to the first source pad 121 and the second source pad 122 to other regions. In this embodiment, the source wiring 125 is drawn out from the first source pad 121 and the second source pad 122 so as to be located closer to the outer periphery region 13 than the gate wiring 102.
　ソース配線１２５は、活性面８側から第１～第４接続面１０Ａ～１０Ｄを通過して外周面９側に引き出されている。ソース配線１２５は、第１～第４接続面１０Ａ～１０Ｄに沿って延びる帯状に形成されている。つまり、ソース配線１２５は、層間絶縁膜９９を挟んでサイドウォール配線９５に対向している。ソース配線１２５は、この形態では、第１～第４接続面１０Ａ～１０Ｄに沿って延びる環状（具体的には四角環状）に形成され、ゲート配線１０２を取り囲んでいる。 The source wiring 125 is drawn out from the active surface 8 side to the outer peripheral surface 9 side, passing through the first to fourth connection surfaces 10A to 10D. The source wiring 125 is formed in a strip shape extending along the first to fourth connection surfaces 10A to 10D. In other words, the source wiring 125 faces the sidewall wiring 95 with the interlayer insulating film 99 in between. In this embodiment, the source wiring 125 is formed in a ring shape (specifically, a square ring shape) extending along the first to fourth connection surfaces 10A to 10D, and surrounds the gate wiring 102.
　ソース配線１２５は、層間絶縁膜９９に形成されたアウター開口１２７を介してサイドウォール配線９５およびアウターコンタクト領域９２に電気的に接続されている。アウター開口１２７は、サイドウォール配線９５およびアウターコンタクト領域９２に沿って延びる帯状または環状に形成されている。ソース配線１２５に付与されたソース電位ＶＳは、サイドウォール配線９５を介して第１トレンチソース構造２５、第２トレンチソース構造３０、第１ダミートレンチ構造６１、第２ダミートレンチ構造６２およびトレンチ終端構造８６に伝達される。 The source wiring 125 is electrically connected to the sidewall wiring 95 and the outer contact region 92 via an outer opening 127 formed in the interlayer insulating film 99. The outer opening 127 is formed in a strip or ring shape extending along the sidewall wiring 95 and the outer contact region 92. The source potential VS applied to the source wiring 125 is transmitted to the first trench source structure 25, the second trench source structure 30, the first dummy trench structure 61, the second dummy trench structure 62, and the trench termination structure 86 via the sidewall wiring 95.
　ソース配線１２５のうち第１側面５Ａに沿って延びた直線部分は、本開示における「第１ソース配線」の一例である。ソース配線１２５のうち第１側面５Ａに沿って延びた直線部分がアウター開口１２７を介して電気的に接続されているアウターコンタクト領域９２は、本開示における「第１アウターコンタクト領域」の一例である。 The straight portion of the source wiring 125 that extends along the first side surface 5A is an example of a "first source wiring" in this disclosure. The outer contact region 92 to which the straight portion of the source wiring 125 that extends along the first side surface 5A is electrically connected via the outer opening 127 is an example of a "first outer contact region" in this disclosure.
　ソース配線１２５のうち第３側面５Ｃに沿って延びた直線部分および第４側面５Ｄに沿って延びた直線部分は、本開示における「第２ソース配線」の一例である。ソース配線１２５のうち第３側面５Ｃに沿って延びた直線部分および第４側面５Ｄに沿って延びた直線部分がアウター開口１２７を介して電気的に接続されているアウターコンタクト領域９２は、本開示における「第２アウターコンタクト領域」の一例である。 The straight portion of the source wiring 125 extending along the third side surface 5C and the straight portion extending along the fourth side surface 5D are an example of a "second source wiring" in this disclosure. The outer contact region 92 to which the straight portion of the source wiring 125 extending along the third side surface 5C and the straight portion extending along the fourth side surface 5D are electrically connected via the outer opening 127 is an example of a "second outer contact region" in this disclosure.
　半導体装置１は、第１主面３の上でゲート電極１００、ソース電極１２０および層間絶縁膜９９を選択的に被覆するアッパー絶縁膜１３０を含む。アッパー絶縁膜１３０は、ゲートパッド１０１の内方部を露出させるゲートパッド開口１３１およびゲートサブパッド１０３の内方部を露出させるゲートサブパッド開口１３２を含む。 The semiconductor device 1 includes an upper insulating film 130 that selectively covers the gate electrode 100, the source electrode 120, and the interlayer insulating film 99 on the first main surface 3. The upper insulating film 130 includes a gate pad opening 131 that exposes the inner portion of the gate pad 101, and a gate subpad opening 132 that exposes the inner portion of the gate subpad 103.
　アッパー絶縁膜１３０は、ゲートパッド１０１の周縁部、ゲートサブパッド１０３の周縁部およびゲート配線１０２の全域を被覆している。ゲートパッド開口１３１は、平面視において四角形状に形成されている。ゲートサブパッド開口１３２は、平面視において四角形状に形成されている。ゲートサブパッド開口１３２は、ゲートパッド開口１３１の平面積よりも小さい平面積を有している。 The upper insulating film 130 covers the periphery of the gate pad 101, the periphery of the gate subpad 103, and the entire gate wiring 102. The gate pad opening 131 is formed in a rectangular shape in a plan view. The gate subpad opening 132 is formed in a rectangular shape in a plan view. The gate subpad opening 132 has a plan area smaller than the plan area of the gate pad opening 131.
　アッパー絶縁膜１３０は、第１ソースパッド１２１の内方部を露出させる第１ソースパッド開口１３３、第２ソースパッド１２２の内方部を露出させる第２ソースパッド開口１３４、第１ソースサブパッド１２３の内方部を露出させる第１ソースサブパッド開口１３５、および、第２ソースサブパッド１２４の内方部を露出させる第２ソースサブパッド開口１３６を含む。アッパー絶縁膜１３０は、第１ソースパッド１２１の周縁部、第２ソースパッド１２２の周縁部、第１ソースサブパッド１２３の周縁部、第２ソースサブパッド１２４の周縁部およびソース配線１２５の全域を被覆している。 The upper insulating film 130 includes a first source pad opening 133 exposing the inner portion of the first source pad 121, a second source pad opening 134 exposing the inner portion of the second source pad 122, a first source subpad opening 135 exposing the inner portion of the first source subpad 123, and a second source subpad opening 136 exposing the inner portion of the second source subpad 124. The upper insulating film 130 covers the periphery of the first source pad 121, the periphery of the second source pad 122, the periphery of the first source subpad 123, the periphery of the second source subpad 124, and the entire area of the source wiring 125.
　第１ソースパッド開口１３３は、平面視において四角形状に形成されている。第１ソースパッド開口１３３は、ゲートサブパッド開口１３２の平面積よりも大きい平面積を有している。第１ソースパッド開口１３３の平面積は、ゲートパッド開口１３１の平面積よりも大きいことが好ましい。 The first source pad opening 133 is formed in a rectangular shape in a plan view. The first source pad opening 133 has a plan area larger than the plan area of the gate subpad opening 132. It is preferable that the plan area of the first source pad opening 133 is larger than the plan area of the gate pad opening 131.
　第２ソースパッド開口１３４は、平面視において四角形状に形成されている。第２ソースパッド開口１３４は、ゲートサブパッド開口１３２の平面積よりも大きい平面積を有している。第２ソースパッド開口１３４の平面積は、ゲートパッド開口１３１の平面積よりも大きいことが好ましい。第２ソースパッド開口１３４の平面積は、第１ソースパッド開口１３３の平面積とほぼ等しいことが好ましい。 The second source pad opening 134 is formed in a rectangular shape in a plan view. The second source pad opening 134 has a plan area larger than the plan area of the gate subpad opening 132. It is preferable that the plan area of the second source pad opening 134 is larger than the plan area of the gate pad opening 131. It is preferable that the plan area of the second source pad opening 134 is approximately equal to the plan area of the first source pad opening 133.
　第１ソースサブパッド開口１３５は、平面視において四角形状に形成されている。第１ソースサブパッド開口１３５は、第１ソースパッド開口１３３の平面積よりも小さい平面積を有している。第１ソースサブパッド開口１３５の平面積は、ゲートサブパッド開口１３２の平面積よりも大きいことが好ましい。第１ソースサブパッド開口１３５の平面積は、この形態では、ゲートパッド開口１３１の平面積よりも大きい。むろん、第１ソースサブパッド開口１３５の平面積は、ゲートパッド開口１３１の平面積未満であってもよい。 The first source subpad opening 135 is formed in a rectangular shape in a plan view. The first source subpad opening 135 has a plan area smaller than the plan area of the first source pad opening 133. The plan area of the first source subpad opening 135 is preferably larger than the plan area of the gate subpad opening 132. In this embodiment, the plan area of the first source subpad opening 135 is larger than the plan area of the gate pad opening 131. Of course, the plan area of the first source subpad opening 135 may be smaller than the plan area of the gate pad opening 131.
　第２ソースサブパッド開口１３６は、平面視において四角形状に形成されている。第２ソースサブパッド開口１３６は、第２ソースパッド開口１３４の平面積よりも小さい平面積を有している。第２ソースサブパッド開口１３６の平面積は、ゲートサブパッド開口１３２の平面積よりも大きいことが好ましい。 The second source subpad opening 136 is formed in a rectangular shape in a plan view. The second source subpad opening 136 has a plan area smaller than the plan area of the second source pad opening 134. It is preferable that the plan area of the second source subpad opening 136 is larger than the plan area of the gate subpad opening 132.
　第２ソースサブパッド開口１３６の平面積は、この形態では、ゲートパッド開口１３１の平面積よりも大きい。むろん、第２ソースサブパッド開口１３６の平面積は、ゲートパッド開口１３１の平面積未満であってもよい。第２ソースサブパッド開口１３６の平面積は、第１ソースサブパッド開口１３５の平面積とほぼ等しいことが好ましい。 In this embodiment, the plane area of the second source subpad opening 136 is larger than the plane area of the gate pad opening 131. Of course, the plane area of the second source subpad opening 136 may be less than the plane area of the gate pad opening 131. It is preferable that the plane area of the second source subpad opening 136 is approximately equal to the plane area of the first source subpad opening 135.
　アッパー絶縁膜１３０は、チップ２の周縁（第１～第４側面５Ａ～５Ｄ）から内方に間隔を空けて形成され、チップ２の周縁との間でダイシングストリート１３７を区画している。ダイシングストリート１３７は、平面視においてチップ２の周縁に沿って延びる帯状に形成されている。ダイシングストリート１３７は、この形態では、平面視において活性面８を取り囲む環状（具体的には四角環状）に形成されている。ダイシングストリート１３７は、この形態では、層間絶縁膜９９を露出させている。 The upper insulating film 130 is formed at a distance inward from the periphery of the chip 2 (first to fourth side surfaces 5A to 5D), and defines a dicing street 137 between the upper insulating film 130 and the periphery of the chip 2. The dicing street 137 is formed in a band shape extending along the periphery of the chip 2 in a plan view. In this embodiment, the dicing street 137 is formed in a ring shape (specifically, a square ring) surrounding the active surface 8 in a plan view. In this embodiment, the dicing street 137 exposes the interlayer insulating film 99.
　むろん、主面絶縁膜１６および層間絶縁膜９９が外周面９を露出させている場合、ダイシングストリート１３７は、外周面９を露出させていてもよい。ダイシングストリート１３７は、１μｍ以上２００μｍ以下の幅を有していてもよい。ダイシングストリート１３７の幅は、ダイシングストリート１３７の延在方向に直交する方向の幅である。ダイシングストリート１３７の幅は、５μｍ以上５０μｍ以下であることが好ましい。 Of course, if the main surface insulating film 16 and the interlayer insulating film 99 expose the outer peripheral surface 9, the dicing street 137 may also expose the outer peripheral surface 9. The dicing street 137 may have a width of 1 μm or more and 200 μm or less. The width of the dicing street 137 is the width in a direction perpendicular to the extension direction of the dicing street 137. The width of the dicing street 137 is preferably 5 μm or more and 50 μm or less.
　アッパー絶縁膜１３０は、ゲート電極１００の厚さおよびソース電極１２０の厚さを超える厚さを有していることが好ましい。アッパー絶縁膜１３０の厚さは、チップ２の厚さ未満であることが好ましい。アッパー絶縁膜１３０の厚さは、３μｍ以上３５μｍ以下であってもよい。アッパー絶縁膜１３０の厚さは、２５μｍ以下であることが好ましい。 The upper insulating film 130 preferably has a thickness that exceeds the thickness of the gate electrode 100 and the thickness of the source electrode 120. The thickness of the upper insulating film 130 is preferably less than the thickness of the chip 2. The thickness of the upper insulating film 130 may be 3 μm or more and 35 μm or less. The thickness of the upper insulating film 130 is preferably 25 μm or less.
　アッパー絶縁膜１３０は、この形態では、チップ２側からこの順に積層された無機絶縁膜１４０および有機絶縁膜１４１を含む積層構造を有している。アッパー絶縁膜１３０は、無機絶縁膜１４０および有機絶縁膜１４１のうちの少なくとも１つを含んでいればよく、必ずしも無機絶縁膜１４０および有機絶縁膜１４１を同時に含む必要はない。 In this embodiment, the upper insulating film 130 has a layered structure including an inorganic insulating film 140 and an organic insulating film 141, which are layered in this order from the chip 2 side. The upper insulating film 130 only needs to include at least one of the inorganic insulating film 140 and the organic insulating film 141, and does not necessarily need to include both the inorganic insulating film 140 and the organic insulating film 141 at the same time.
　無機絶縁膜１４０は、ゲート電極１００、ソース電極１２０および層間絶縁膜９９を選択的に被覆し、ゲートパッド開口１３１の一部、ゲートサブパッド開口１３２の一部、第１ソースパッド開口１３３の一部、第２ソースパッド開口１３４の一部、第１ソースサブパッド開口１３５の一部、第２ソースサブパッド開口１３６の一部およびダイシングストリート１３７の一部を区画している。 The inorganic insulating film 140 selectively covers the gate electrode 100, the source electrode 120 and the interlayer insulating film 99, and defines a portion of the gate pad opening 131, a portion of the gate subpad opening 132, a portion of the first source pad opening 133, a portion of the second source pad opening 134, a portion of the first source subpad opening 135, a portion of the second source subpad opening 136 and a portion of the dicing street 137.
　無機絶縁膜１４０は、酸化シリコン膜、窒化シリコン膜および酸窒化シリコン膜のうちの少なくとも１つを含んでいてもよい。無機絶縁膜１４０は、層間絶縁膜９９とは異なる絶縁材料を含むことが好ましい。無機絶縁膜１４０は、窒化シリコン膜を含むことが好ましい。無機絶縁膜１４０は、層間絶縁膜９９の厚さ未満の厚さを有していることが好ましい。無機絶縁膜１４０の厚さは、０．１μｍ以上５μｍ以下であってもよい。 The inorganic insulating film 140 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is preferable that the inorganic insulating film 140 includes an insulating material different from that of the interlayer insulating film 99. It is preferable that the inorganic insulating film 140 includes a silicon nitride film. It is preferable that the inorganic insulating film 140 has a thickness less than that of the interlayer insulating film 99. The thickness of the inorganic insulating film 140 may be 0.1 μm or more and 5 μm or less.
　有機絶縁膜１４１は、無機絶縁膜１４０を選択的に被覆し、ゲートパッド開口１３１の一部、ゲートサブパッド開口１３２の一部、第１ソースパッド開口１３３の一部、第２ソースパッド開口１３４の一部、第１ソースサブパッド開口１３５の一部、第２ソースサブパッド開口１３６の一部およびダイシングストリート１３７の一部を区画している。 The organic insulating film 141 selectively covers the inorganic insulating film 140 and defines a portion of the gate pad opening 131, a portion of the gate subpad opening 132, a portion of the first source pad opening 133, a portion of the second source pad opening 134, a portion of the first source subpad opening 135, a portion of the second source subpad opening 136, and a portion of the dicing street 137.
　有機絶縁膜１４１は、ゲートパッド開口１３１の壁面において無機絶縁膜１４０を露出させていてもよい。有機絶縁膜１４１は、ゲートサブパッド開口１３２の壁面において無機絶縁膜１４０を露出させていてもよい。有機絶縁膜１４１は、第１ソースパッド開口１３３の壁面において無機絶縁膜１４０を露出させていてもよい。有機絶縁膜１４１は、第２ソースパッド開口１３４の壁面において無機絶縁膜１４０を露出させていてもよい。 The organic insulating film 141 may expose the inorganic insulating film 140 on the wall surface of the gate pad opening 131. The organic insulating film 141 may expose the inorganic insulating film 140 on the wall surface of the gate subpad opening 132. The organic insulating film 141 may expose the inorganic insulating film 140 on the wall surface of the first source pad opening 133. The organic insulating film 141 may expose the inorganic insulating film 140 on the wall surface of the second source pad opening 134.
　有機絶縁膜１４１は、第１ソースサブパッド開口１３５の壁面において無機絶縁膜１４０を露出させていてもよい。有機絶縁膜１４１は、第２ソースサブパッド開口１３６の壁面において無機絶縁膜１４０を露出させていてもよい。有機絶縁膜１４１は、ダイシングストリート１３７の壁面において無機絶縁膜１４０を露出させていてもよい。むろん、有機絶縁膜１４１は、無機絶縁膜１４０を露出させないように無機絶縁膜１４０の全域を被覆していてもよい。 The organic insulating film 141 may expose the inorganic insulating film 140 on the wall surface of the first source subpad opening 135. The organic insulating film 141 may expose the inorganic insulating film 140 on the wall surface of the second source subpad opening 136. The organic insulating film 141 may expose the inorganic insulating film 140 on the wall surface of the dicing street 137. Of course, the organic insulating film 141 may cover the entire inorganic insulating film 140 so that the inorganic insulating film 140 is not exposed.
　有機絶縁膜１４１は、熱硬化性樹脂以外の樹脂膜からなることが好ましい。有機絶縁膜１４１は、透光性樹脂または透明樹脂からなっていてもよい。有機絶縁膜１４１は、ネガティブタイプまたはポジティブタイプの感光性樹脂膜からなっていてもよい。有機絶縁膜１４１は、ポリイミド膜、ポリアミド膜またはポリベンゾオキサゾール膜からなることが好ましい。有機絶縁膜１４１は、この形態では、ポリベンゾオキサゾール膜を含む。 The organic insulating film 141 is preferably made of a resin film other than a thermosetting resin. The organic insulating film 141 may be made of a translucent resin or a transparent resin. The organic insulating film 141 may be made of a negative type or positive type photosensitive resin film. The organic insulating film 141 is preferably made of a polyimide film, a polyamide film, or a polybenzoxazole film. In this embodiment, the organic insulating film 141 includes a polybenzoxazole film.
　有機絶縁膜１４１は、無機絶縁膜１４０の厚さを超える厚さを有していることが好ましい。有機絶縁膜１４１の厚さは、層間絶縁膜９９の厚さを超えていることが好ましい。有機絶縁膜１４１の厚さは、ゲート電極１００の厚さおよびソース電極１２０の厚さを超えていることが特に好ましい。有機絶縁膜１４１の厚さは、３μｍ以上３０μｍ以下であってもよい。有機絶縁膜１４１の厚さは、２０μｍ以下であることが好ましい。 The organic insulating film 141 preferably has a thickness that exceeds the thickness of the inorganic insulating film 140. The thickness of the organic insulating film 141 preferably exceeds the thickness of the interlayer insulating film 99. It is particularly preferable that the thickness of the organic insulating film 141 exceeds the thickness of the gate electrode 100 and the thickness of the source electrode 120. The thickness of the organic insulating film 141 may be 3 μm or more and 30 μm or less. The thickness of the organic insulating film 141 is preferably 20 μm or less.
　半導体装置１は、第２主面４を被覆するドレイン電極１５０を含む。ドレイン電極１５０は、第２主面４から露出した第２半導体領域７とオーミック接触を形成している。ドレイン電極１５０は、チップ２の周縁（第１～第４側面５Ａ～５Ｄ）に連なるように第２主面４の全域を被覆していてもよい。ソース電極１２０およびドレイン電極１５０の間（第１主面３および第２主面４の間）に印加可能なブレークダウン電圧は、５００Ｖ以上３０００Ｖ以下であってもよい。 The semiconductor device 1 includes a drain electrode 150 covering the second main surface 4. The drain electrode 150 forms an ohmic contact with the second semiconductor region 7 exposed from the second main surface 4. The drain electrode 150 may cover the entire second main surface 4 so as to be continuous with the periphery of the chip 2 (first to fourth side surfaces 5A to 5D). The breakdown voltage that can be applied between the source electrode 120 and the drain electrode 150 (between the first main surface 3 and the second main surface 4) may be 500V or more and 3000V or less.
　この半導体装置１では、図１７および図１８に示すように、抵抗膜５０は、主面絶縁膜１６上に形成されている部分５０ａ、言い換えれば、主面絶縁膜１６を覆っている部分５０ａを含んでいる。また、図９に示すように、ゲート接続電極膜３９は、主面絶縁膜１６上に形成されている部分３９ｂ、言い換えれば、主面絶縁膜１６を覆っている部分３９ｂを含んでいる。抵抗膜５０およびゲート接続電極膜３９は、ゲート電極１００に電気的に接続されている。 In this semiconductor device 1, as shown in Figures 17 and 18, the resistive film 50 includes a portion 50a formed on the main surface insulating film 16, in other words, a portion 50a covering the main surface insulating film 16. Also, as shown in Figure 9, the gate connection electrode film 39 includes a portion 39b formed on the main surface insulating film 16, in other words, a portion 39b covering the main surface insulating film 16. The resistive film 50 and the gate connection electrode film 39 are electrically connected to the gate electrode 100.
　以下において、抵抗膜５０における主面絶縁膜１６上に形成されている部分５０ａおよびゲート接続電極膜３９における主面絶縁膜１６上に形成されている部分３９ｂのように、主面絶縁膜１６上に形成されかつゲート電極１００に電気的に接続されている導電性膜を、ゲート接続導電膜５０ａ，３９ｂということにする。ゲート接続導電膜５０ａ，３９ｂは、本開示の「ゲート接続導電膜」の一例である。 Hereinafter, conductive films formed on the main surface insulating film 16 and electrically connected to the gate electrode 100, such as the portion 50a of the resistive film 50 formed on the main surface insulating film 16 and the portion 39b of the gate connection electrode film 39 formed on the main surface insulating film 16, will be referred to as gate connection conductive films 50a and 39b. The gate connection conductive films 50a and 39b are examples of the "gate connection conductive film" of this disclosure.
　また、以下において、ｐ型のボディ領域１７、第１ウェル領域３５、第２ウェル領域３６、第３ウェル領域３７、第４ウェル領域７５、第５ウェル領域７６、第６ウェル領域７７およびアウターウェル領域９１のように、第１半導体領域６の表層部に形成されたｐ型領域を、総称して「ｐ型領域」ということにする。「ｐ型領域」は、本開示の「第１領域」の一例である。 Furthermore, in the following, p-type regions formed in the surface layer of the first semiconductor region 6, such as the p-type body region 17, the first well region 35, the second well region 36, the third well region 37, the fourth well region 75, the fifth well region 76, the sixth well region 77, and the outer well region 91, will be collectively referred to as the "p-type region." The "p-type region" is an example of the "first region" of this disclosure.
　また、以下において、第１コンタクト領域３８およびアウターコンタクト領域９２のように、「ｐ型領域」の表層部に形成されかつソース電極１２０に電気的に接続されるｐ型のコンタクト領域を、総称してｐ型コンタクト領域３８，９２ということにする。ｐ型コンタクト領域３８，９２は、本開示の「コンタクト領域」の一例である。 Furthermore, in the following description, p-type contact regions that are formed on the surface layer of the "p-type region" and electrically connected to the source electrode 120, such as the first contact region 38 and the outer contact region 92, will be collectively referred to as p- type contact regions 38, 92. The p- type contact regions 38, 92 are an example of a "contact region" in this disclosure.
　また、以下において、ソース開口１２６またはアウター開口１２７を介してｐ型コンタクト領域３８，９２にソース電極１２０が接合されている領域を、総称して「ソース／コンタクト接合領域」ということにする。「ソース／コンタクト接合領域」は、ｐ型コンタクト領域３８，９２のうちソース電極１２０が接合されている領域である。 Furthermore, in the following description, the region where the source electrode 120 is bonded to the p- type contact region 38, 92 via the source opening 126 or the outer opening 127 will be collectively referred to as the "source/contact junction region." The "source/contact junction region" is the region of the p- type contact region 38, 92 where the source electrode 120 is bonded.
　半導体装置（ＭＩＳＦＥＴ）１のスイッチング時には、ソース電極１２０とドレイン電極１５０との間に比較的大きな電圧ＶＤＳ／ｄｔが印加される。そうすると、ソース電極１２０とドレイン電極１５０との間に、空乏層容量Ｃに起因する充電電流ｉｃ（＝Ｃ＊ＶＤＳ／ｄｔ）が流れる。この充電電流ｉｃは、例えば、「ソース／コンタクト接合領域」から、その近傍にあるゲート接続導電膜５０ａ，３９ｂの下方の「ｐ型領域」を当該ゲート接続導電膜５０ａ，３９ｂに沿って流れた後、ドレイン電極１５０に流れる。このような充電電流ｉｃが流れると、「ｐ型領域」の抵抗成分によって電圧降下が発生し、この電圧降下によって、「ｐ型領域」とゲート接続導電膜５０ａ，３９ｂとの間に電位差が発生する。「ｐ型領域」とゲート接続導電膜５０ａ，３９ｂとの間の電位差により、それらの間に介在する主面絶縁膜１６に電界が印加される。この電界により、主面絶縁膜１６が損傷し、リーク電流が増加するおそれがある。 When the semiconductor device (MISFET) 1 is switched, a relatively large voltage V DS /dt is applied between the source electrode 120 and the drain electrode 150. Then, a charging current ic (=C*V DS /dt) caused by the depletion layer capacitance C flows between the source electrode 120 and the drain electrode 150. This charging current ic flows, for example, from the "source/contact junction region" through the "p-type region" below the gate connection conductive films 50a and 39b in the vicinity of the "source/contact junction region" along the gate connection conductive films 50a and 39b, and then flows to the drain electrode 150. When such a charging current ic flows, a voltage drop occurs due to the resistance component of the "p-type region", and this voltage drop generates a potential difference between the "p-type region" and the gate connection conductive films 50a and 39b. Due to the potential difference between the "p-type region" and the gate connection conductive films 50a and 39b, an electric field is applied to the main surface insulating film 16 interposed therebetween. This electric field may damage the main surface insulating film 16, increasing the leakage current.
　「ｐ型領域」とゲート接続導電膜５０ａ，３９ｂとの間の電位差を小さくするためには、「ｐ型領域」内を充電電流ｉｃが流れる距離を短くすればよい。つまり、ゲート接続導電膜５０ａ，３９ｂの下面の各位置とそれに最も近い「ソース／コンタクト接合領域」との距離の最大値を小さくすればよい。 In order to reduce the potential difference between the "p-type region" and the gate connection conductive film 50a, 39b, the distance through which the charging current ic flows within the "p-type region" should be shortened. In other words, the maximum distance between each position on the underside of the gate connection conductive film 50a, 39b and the "source/contact junction region" closest to it should be reduced.
　この形態では、ゲート接続導電膜５０ａ，３９ｂの下面の各位置とそれに最も近い「ソース／コンタクト接合領域」との距離の最大値が９０μｍ以下となるように、ゲート接続導電膜５０ａ，３９ｂ、「ソース／コンタクト接合領域」等のレイアウトが設計されている。 In this embodiment, the layout of the gate connection conductive films 50a, 39b, the "source/contact junction region", etc. is designed so that the maximum distance between each position on the underside of the gate connection conductive films 50a, 39b and the "source/contact junction region" closest to it is 90 μm or less.
　なお、ゲート接続導電膜５０ａ，３９ｂの下面の各位置とそれに最も近い「ソース／コンタクト接合領域」との距離の最大値が８０μｍ以下となるように、ゲート接続導電膜５０ａ，３９ｂ、「ソース／コンタクト接合領域」等のレイアウトを設計することが好ましい。さらに、ゲート接続導電膜５０ａ，３９ｂの下面の各位置とそれに最も近い「ソース／コンタクト接合領域」との距離の最大値が７０μｍ以下となるように、ゲート接続導電膜５０ａ，３９ｂ、「ソース／コンタクト接合領域」等のレイアウトを設計することがより好ましい。 It is preferable to design the layout of the gate connection conductive films 50a, 39b, the "source/contact junction region", etc. so that the maximum distance between each position on the underside of the gate connection conductive films 50a, 39b and the "source/contact junction region" closest to it is 80 μm or less. Furthermore, it is even more preferable to design the layout of the gate connection conductive films 50a, 39b, the "source/contact junction region", etc. so that the maximum distance between each position on the underside of the gate connection conductive films 50a, 39b and the "source/contact junction region" closest to it is 70 μm or less.
　この形態では、半導体装置１において、ゲート接続導電膜５０ａ，３９ｂの下面内の位置とそれに最も近い「ソース／コンタクト接合領域」との距離が最も大きくなるレイアウトは、図１３に示す領域Ｅ１内に存在する。 In this embodiment, the layout in which the distance between the position on the underside of the gate connection conductive films 50a, 39b and the "source/contact junction region" closest to it is greatest in the semiconductor device 1 is present in the region E1 shown in FIG. 13.
　図１３に示す領域Ｅ１のレイアウトの詳細は、前述の図１４、図１７および図２６の他、図２９に示されている。図２９は、図１３のXXIX-XXIX線に沿う断面図である。 Details of the layout of region E1 shown in FIG. 13 are shown in FIG. 29 in addition to the aforementioned FIG. 14, FIG. 17, and FIG. 26. FIG. 29 is a cross-sectional view taken along line XXIX-XXIX in FIG. 13.
　図１４および図１７を参照して、ゲート抵抗４０は、抵抗膜５０を含んでいる。したがって、ゲート抵抗４０は、主面絶縁膜１６上に形成されたゲート接続導電膜５０ａを含んでいる。 Referring to FIG. 14 and FIG. 17, the gate resistor 40 includes a resistive film 50. Therefore, the gate resistor 40 includes a gate connection conductive film 50a formed on the main surface insulating film 16.
　図２９を参照して、ゲート接続導電膜５０ａの下面の各位置のうち、半導体装置１内の全ての「ソース／コンタクト接合領域」それぞれからその位置までの距離の最小値が最大となる位置を第１位置Ｐ１とする。この形態では、抵抗膜５０（ゲート接続導電膜５０ａ）の下面における活性領域１２側（パッド本体部１０４側）に最も近い位置が第１位置Ｐ１である。 Referring to FIG. 29, among the positions on the underside of the gate connection conductive film 50a, the position where the minimum distance from each of all the "source/contact junction regions" in the semiconductor device 1 to that position is the largest is defined as the first position P1. In this embodiment, the position on the underside of the resistive film 50 (gate connection conductive film 50a) closest to the active region 12 side (pad body portion 104 side) is the first position P1.
　ソース配線１２５は、ゲート抵抗４０に対して活性領域１２とは反対側の領域において、トレンチ抵抗構造４１（第１側面５Ａ）に沿って延びた直線部分（以下、「第１ソース配線１２５」という。）を含む。 The source wiring 125 includes a straight portion (hereinafter referred to as the "first source wiring 125") that extends along the trench resistor structure 41 (first side surface 5A) in the region opposite the active region 12 with respect to the gate resistor 40.
　「第１ソース配線１２５」が接続されているアウターコンタクト領域９２のうち、「第１ソース配線１２５」が接合されている領域を、「第１ソース配線１２５」が接合されているソース／コンタクト接合領域９２Ａということにする。言い換えれば、「第１ソース配線１２５」が接合されているソース／コンタクト接合領域９２Ａは、アウターコンタクト領域９２のうち「第１ソース配線１２５」が接合されている領域である。 The region of the outer contact region 92 to which the "first source wiring 125" is connected and to which the "first source wiring 125" is bonded is referred to as the source/contact junction region 92A to which the "first source wiring 125" is bonded. In other words, the source/contact junction region 92A to which the "first source wiring 125" is bonded is the region of the outer contact region 92 to which the "first source wiring 125" is bonded.
　図２９に示すように、「第１ソース配線１２５」が接合されているソース／コンタクト接合領域９２Ａは、半導体装置１内の全ての「ソース／コンタクト接合領域」のうち第１位置Ｐ１までの距離が最も小さくなるソース／コンタクト接合領域９２Ａを含んでいる。この形態では、「第１ソース配線１２５」が接合されているソース／コンタクト接合領域９２Ａのうち第１位置Ｐ１に最も近いソース／コンタクト接合領域９２Ａと、第１位置Ｐ１との間の距離Ｍ１は、６８μｍ程度であり、７０μｍ以下である。つまり、この形態では、ゲート接続導電膜５０ａ，３９ｂの下面の各位置とそれに最も近い「ソース／コンタクト接合領域」との距離の最大値は、７０μｍ以下である。 As shown in FIG. 29, the source/contact junction region 92A to which the "first source wiring 125" is bonded includes the source/contact junction region 92A having the shortest distance to the first position P1 among all the "source/contact junction regions" in the semiconductor device 1. In this embodiment, the distance M1 between the source/contact junction region 92A closest to the first position P1 among the source/contact junction regions 92A to which the "first source wiring 125" is bonded and the first position P1 is about 68 μm, which is less than 70 μm. In other words, in this embodiment, the maximum distance between each position on the lower surface of the gate connection conductive films 50a, 39b and the "source/contact junction region" closest to it is less than 70 μm.
　ゲート接続電極膜３９に含まれているゲート接続導電膜３９ｂの下面内の位置とそれに最も近い「ソース／コンタクト接合領域」との距離が最大値または最大値に近い値となるレイアウトは、例えば、図３に示す領域Ｅ２内および図１３に示す領域Ｅ３内に存在する。 Layouts in which the distance between a position on the underside of the gate connection conductive film 39b included in the gate connection electrode film 39 and the closest "source/contact junction region" is at or near the maximum value exist, for example, in region E2 shown in FIG. 3 and region E3 shown in FIG. 13.
　図３に示す領域Ｅ２内のレイアウトの詳細は、前述の図６、図９、図１０および図１１に示されている。図１１は、図６に示すXI-XI線に沿う断面図である。 Details of the layout within region E2 shown in FIG. 3 are shown in the above-mentioned FIGS. 6, 9, 10, and 11. FIG. 11 is a cross-sectional view taken along line XI-XI shown in FIG. 6.
　図６および図１１を参照して、第１ゲート配線１０２Ａは、活性領域１２において第１周縁領域１４Ａに沿って延びた直線部分（以下、「第１周縁ゲート配線１０２Ａ」という。）を有している。「第１周縁ゲート配線１０２Ａ」は、本開示の「周縁ゲート配線」の一例である。 6 and 11, the first gate wiring 102A has a straight portion (hereinafter referred to as the "first peripheral gate wiring 102A") that extends along the first peripheral region 14A in the active region 12. The "first peripheral gate wiring 102A" is an example of the "peripheral gate wiring" of the present disclosure.
　トレンチゲート構造２０の「第１周縁ゲート配線１０２Ａ」側（第１周縁領域１４Ａ側）の端部に、ゲート埋設電極２３および主面絶縁膜１６を被覆しかつ「第１周縁ゲート配線１０２Ａ」に接合されるゲート接続電極膜３９が形成されている。ゲート接続電極膜３９は、主面絶縁膜１６上に形成されたゲート接続導電膜３９ｂ（図９参照）を含んでいる。 A gate connection electrode film 39 is formed on the end of the trench gate structure 20 on the "first peripheral gate wiring 102A" side (first peripheral region 14A side), covering the gate buried electrode 23 and the main surface insulating film 16 and joining to the "first peripheral gate wiring 102A". The gate connection electrode film 39 includes a gate connection conductive film 39b (see FIG. 9) formed on the main surface insulating film 16.
　ソース配線１２５は、「第１周縁ゲート配線１０２Ａ」に対して活性領域１２とは反対側の領域において、「第１周縁ゲート配線１０２Ａ」（第３側面５Ｃ）に沿って延びた直線部分（以下、「第２ソース配線１２５」という。）を含む。「第２ソース配線１２５」は、本開示における「第２ソース配線」の一例である。 The source wiring 125 includes a straight portion (hereinafter referred to as the "second source wiring 125") that extends along the "first peripheral gate wiring 102A" (third side surface 5C) in the region opposite the active region 12 with respect to the "first peripheral gate wiring 102A." The "second source wiring 125" is an example of the "second source wiring" in this disclosure.
　「第１周縁ゲート配線１０２Ａ」に接合されるゲート接続電極膜３９に含まれるゲート接続導電膜３９ｂの下面の各位置のうち、半導体装置１内の全ての「ソース／コンタクト接合領域」それぞれからその位置までの距離の最小値が最大となる位置を第２位置Ｐ２とする。この形態では、第２位置Ｐ２は、「第１周縁ゲート配線１０２Ａ」に接合されるゲート接続電極膜３９における第１方向Ｘの長さ中央位置である。 Among the positions on the underside of the gate connection conductive film 39b included in the gate connection electrode film 39 joined to the "first peripheral gate wiring 102A", the position where the minimum value of the distance from each of all the "source/contact junction regions" in the semiconductor device 1 to that position is the largest is defined as the second position P2. In this embodiment, the second position P2 is the central position of the length in the first direction X of the gate connection electrode film 39 joined to the "first peripheral gate wiring 102A".
　図１１を参照して、「第２ソース配線１２５」が接続されているアウターコンタクト領域９２のうち、「第２ソース配線１２５」が接合されている領域を、「第２ソース配線１２５」が接合されているソース／コンタクト接合領域９２Ｂということにする。言い換えれば、「第２ソース配線１２５」が接合されているソース／コンタクト接合領域９２Ｂは、アウターコンタクト領域９２のうち、「第２ソース配線１２５」が接合されている領域である。 Referring to FIG. 11, the region of the outer contact region 92 to which the "second source wiring 125" is connected, to which the "second source wiring 125" is bonded, is referred to as the source/contact junction region 92B to which the "second source wiring 125" is bonded. In other words, the source/contact junction region 92B to which the "second source wiring 125" is bonded is the region of the outer contact region 92 to which the "second source wiring 125" is bonded.
　図１１に示すように、「第２ソース配線１２５」が接合されているソース／コンタクト接合領域９２Ｂは、半導体装置１内の全ての「ソース／コンタクト接合領域」のうち第２位置Ｐ２までの距離が最も小さくなるソース／コンタクト接合領域９２Ｂを含んでいる。この形態では、「第２ソース配線１２５」が接合されているソース／コンタクト接合領域９２Ｂのうち第２位置Ｐ２に最も近いソース／コンタクト接合領域９２Ｂと、第２位置Ｐ２との距離Ｍ２は、２９μｍ程度である。 As shown in FIG. 11, the source/contact junction region 92B to which the "second source wiring 125" is bonded includes the source/contact junction region 92B having the shortest distance to the second position P2 among all the "source/contact junction regions" in the semiconductor device 1. In this embodiment, the distance M2 between the source/contact junction region 92B closest to the second position P2 among the source/contact junction regions 92B to which the "second source wiring 125" is bonded and the second position P2 is approximately 29 μm.
　なお、第２周縁領域１４Ｂ側には、半導体装置１の第１方向Ｘの中心を通り第２方向Ｙに延びた直線に対して、領域Ｅ２内のレイアウトと線対称の関係にあるレイアウトが存在する。具体的には、第２ゲート配線１０２Ｂは、活性領域１２において第２周縁領域１４Ｂに沿って延びた直線部分（以下、「第２周縁ゲート配線１０２Ｂ」という。）を有している。「第２周縁ゲート配線１０２Ｂ」は、本開示の「周縁ゲート配線」の一例である。 Incidentally, on the second peripheral region 14B side, there is a layout that is in a linear symmetrical relationship with the layout in region E2 with respect to a straight line that passes through the center of the semiconductor device 1 in the first direction X and extends in the second direction Y. Specifically, the second gate wiring 102B has a straight line portion (hereinafter referred to as the "second peripheral gate wiring 102B") that extends along the second peripheral region 14B in the active region 12. The "second peripheral gate wiring 102B" is an example of the "peripheral gate wiring" of the present disclosure.
　トレンチゲート構造２０の「第２周縁ゲート配線１０２Ｂ」側（第２周縁領域１４Ｂ側）の端部に、ゲート埋設電極２３および主面絶縁膜１６を被覆しかつ「第２周縁ゲート配線１０２Ｂ」に接合されるゲート接続電極膜３９が形成されている。図示されていないが、「第２周縁ゲート配線１０２Ｂ」に接合されるゲート接続電極膜３９は、「第１周縁ゲート配線１０２Ａ」に接合されるゲート接続電極膜３９と同様に、主面絶縁膜１６上に形成されたゲート接続導電膜３９ｂを含んでいる。 A gate connection electrode film 39 is formed on the end of the trench gate structure 20 on the "second peripheral gate wiring 102B" side (second peripheral region 14B side), covering the gate buried electrode 23 and the main surface insulating film 16 and being joined to the "second peripheral gate wiring 102B". Although not shown, the gate connection electrode film 39 joined to the "second peripheral gate wiring 102B" includes a gate connection conductive film 39b formed on the main surface insulating film 16, similar to the gate connection electrode film 39 joined to the "first peripheral gate wiring 102A".
　ソース配線１２５は、「第２周縁ゲート配線１０２Ｂ」に対して活性領域１２とは反対側の領域において、「第２周縁ゲート配線１０２Ｂ」（第４側面５Ｄ）に沿って延びた直線部分（以下、「第３ソース配線１２５」という。）を含む。「第３ソース配線１２５」は、本開示における「第２ソース配線」の一例である。 The source wiring 125 includes a straight portion (hereinafter referred to as the "third source wiring 125") that extends along the "second peripheral gate wiring 102B" (fourth side surface 5D) in the region opposite the active region 12 relative to the "second peripheral gate wiring 102B." The "third source wiring 125" is an example of the "second source wiring" in this disclosure.
　「第２周縁ゲート配線１０２Ｂ」に接合されるゲート接続電極膜３９に含まれるゲート接続導電膜３９ｂの下面の各位置のうち、半導体装置１内の全ての「ソース／コンタクト接合領域」それぞれからその位置までの距離の最小値が最大となる位置を第４位置とする。この形態では、第４位置は、「第２周縁ゲート配線１０２Ｂ」に接合されるゲート接続電極膜３９における第１方向Ｘの長さ中央位置である。 Among the positions on the underside of the gate connection conductive film 39b included in the gate connection electrode film 39 joined to the "second peripheral gate wiring 102B", the position where the minimum value of the distance from each of all the "source/contact junction regions" in the semiconductor device 1 to that position is the largest is defined as the fourth position. In this embodiment, the fourth position is the center position of the length in the first direction X of the gate connection electrode film 39 joined to the "second peripheral gate wiring 102B".
　「第３ソース配線１２５」が接合されているアウターコンタクト領域９２のうち、「第３ソース配線１２５」が接合されている領域を、「第３ソース配線１２５」が接合されている「ソース／コンタクト接合領域」ということにする。言い換えれば、「第３ソース配線１２５」が接合されている「ソース／コンタクト接合領域」は、アウターコンタクト領域９２のうち、「第３ソース配線１２５」が接合されている領域である。 The region of the outer contact region 92 to which the "third source wiring 125" is bonded is referred to as the "source/contact junction region" to which the "third source wiring 125" is bonded. In other words, the "source/contact junction region" to which the "third source wiring 125" is bonded is the region of the outer contact region 92 to which the "third source wiring 125" is bonded.
　「第３ソース配線１２５」が接合されている「ソース／コンタクト接合領域」は、半導体装置１内の全ての「ソース／コンタクト接合領域」のうち第４位置までの距離が最も小さくなる「ソース／コンタクト接合領域」を含んでいる。この形態では、「第３ソース配線１２５」が接合されている「ソース／コンタクト接合領域」のうち第４位置に最も近い「ソース／コンタクト接合領域」と、第４位置との距離は、２９μｍ程度である。 The "source/contact junction region" to which the "third source wiring 125" is bonded includes the "source/contact junction region" that has the shortest distance to the fourth position among all the "source/contact junction regions" in the semiconductor device 1. In this embodiment, the distance between the fourth position and the "source/contact junction region" closest to the fourth position among the "source/contact junction regions" to which the "third source wiring 125" is bonded is approximately 29 μm.
　図１３に示す領域Ｅ３内のレイアウトの詳細は、図３０および図３１に示されている。図３０は、図１３の領域Ｅ３の一部を拡大して示す拡大平面図である。図３１は、図３０のXXXI-XXXI線に沿う断面図である。 Details of the layout within region E3 shown in FIG. 13 are shown in FIG. 30 and FIG. 31. FIG. 30 is an enlarged plan view showing a portion of region E3 in FIG. 13. FIG. 31 is a cross-sectional view taken along line XXXI-XXXI in FIG. 30.
　図３０および図３１を参照して、第３ゲート配線１０２Ｃは、活性領域１２において両側の周縁領域１４Ａ，１４Ｂの間の中央領域に沿って延びたライン部１１０を含んでいる。ライン部１１０は、本開示の「中央ゲート配線」の一例である。 30 and 31, the third gate wiring 102C includes a line portion 110 that extends along the central region between the peripheral regions 14A and 14B on both sides of the active region 12. The line portion 110 is an example of the "central gate wiring" of the present disclosure.
　トレンチゲート構造２０におけるライン部１１０に対向する部分に、ゲート埋設電極２３および主面絶縁膜１６を被覆しかつライン部１１０に接合されるゲート接続電極膜３９が形成されている。ゲート接続電極膜３９は、主面絶縁膜１６上に形成されたゲート接続導電膜３９ｂを含んでいる。 A gate connection electrode film 39 is formed in the portion of the trench gate structure 20 facing the line portion 110, covering the gate buried electrode 23 and the main surface insulating film 16 and being joined to the line portion 110. The gate connection electrode film 39 includes a gate connection conductive film 39b formed on the main surface insulating film 16.
　ソース電極１２０は、活性領域１２において、ライン部１１０の両側にライン部１１０から間隔を空けて配置された第１ソースパッド１２１および第２ソースパッド１２２を含む。第１ソースパッド１２１および第２ソースパッド１２２は、本開示における「ソースパッド部」の一例である。第１ソースパッド１２１および第２ソースパッド１２２は、ソース開口１２６を介して、第１トレンチソース構造２５、ソース領域１８および第１コンタクト領域３８に電気的に接続されている。 The source electrode 120 includes a first source pad 121 and a second source pad 122 arranged on both sides of the line portion 110 at a distance from the line portion 110 in the active region 12. The first source pad 121 and the second source pad 122 are an example of a "source pad portion" in this disclosure. The first source pad 121 and the second source pad 122 are electrically connected to the first trench source structure 25, the source region 18, and the first contact region 38 via the source opening 126.
　ライン部１１０に接合されるゲート接続電極膜３９に含まれるゲート接続導電膜３９ｂの下面の各位置のうち、半導体装置１内の全ての「ソース／コンタクト接合領域」それぞれからその位置までの距離の最小値が最大となる位置を第３位置Ｐ３とする。この形態では、第３位置Ｐ３は、ライン部１１０に接合されるゲート接続電極膜３９における第１方向Ｘの長さ中央位置である。 Among the positions on the underside of the gate connection conductive film 39b included in the gate connection electrode film 39 joined to the line portion 110, the position where the minimum value of the distance from each of all the "source/contact junction regions" in the semiconductor device 1 to that position is the largest is defined as the third position P3. In this embodiment, the third position P3 is the center position of the length in the first direction X of the gate connection electrode film 39 joined to the line portion 110.
　第１ソースパッド１２１が接合されている第１コンタクト領域３８のうち第１ソースパッド１２１が接合されている領域を、第１ソースパッド１２１が接合されているソース／コンタクト接合領域３８Ａということにする。言い換えれば、第１ソースパッド１２１が接合されているソース／コンタクト接合領域３８Ａは、第１コンタクト領域３８のうち、第１ソースパッド１２１が接合されている領域である。 The region of the first contact region 38 to which the first source pad 121 is bonded is referred to as the source/contact junction region 38A to which the first source pad 121 is bonded. In other words, the source/contact junction region 38A to which the first source pad 121 is bonded is the region of the first contact region 38 to which the first source pad 121 is bonded.
　第２ソースパッド１２２が接合されている第１コンタクト領域３８のうち第２ソースパッド１２２が接合されている領域を、第２ソースパッド１２２が接合されているソース／コンタクト接合領域３８Ａということにする。言い換えれば、第２ソースパッド１２２が接合されているソース／コンタクト接合領域３８Ａは、第１コンタクト領域３８のうち、第２ソースパッド１２２が接合されている領域である。 The region of the first contact region 38 to which the second source pad 122 is bonded is referred to as the source/contact junction region 38A to which the second source pad 122 is bonded. In other words, the source/contact junction region 38A to which the second source pad 122 is bonded is the region of the first contact region 38 to which the second source pad 122 is bonded.
　第１ソースパッド１２１および第２ソースパッド１２２のうち少なくとも一方（この形態では第１ソースパッド１２１および第２ソースパッド１２２の両方）が接合されているソース／コンタクト接合領域３８Ａは、半導体装置１内の全ての「ソース／コンタクト接合領域」のうち第３位置Ｐ３までの距離が最も小さくなるソース／コンタクト接合領域３８Ａを含んでいる。 The source/contact junction region 38A to which at least one of the first source pad 121 and the second source pad 122 (in this embodiment, both the first source pad 121 and the second source pad 122) is bonded includes the source/contact junction region 38A that has the shortest distance to the third position P3 among all the "source/contact junction regions" in the semiconductor device 1.
　図３１には、第１ソースパッド１２１が接合されているソース／コンタクト接合領域３８Ａのうち、第３位置Ｐ３までの距離が最も小さくなるソース／コンタクト接合領域３８Ａが図示されている。一方、第２ソースパッド１２２が接合されているソース／コンタクト接合領域３８Ａのうち、第３位置Ｐ３までの距離が最も小さくなるソース／コンタクト接合領域３８Ａは図示されていない。 FIG. 31 illustrates the source/contact junction region 38A to which the first source pad 121 is bonded, which has the shortest distance to the third position P3. On the other hand, the source/contact junction region 38A to which the second source pad 122 is bonded, which has the shortest distance to the third position P3, is not illustrated.
　この形態では、第１ソースパッド１２１が接合されるソース／コンタクト接合領域３８Ａのうち第３位置Ｐ３に最も近いソース／コンタクト接合領域３８Ａと、第３位置Ｐ３との距離Ｍ３は、３２μｍ程度である。また、第２ソースパッド１２２が接合されるソース／コンタクト接合領域３８Ａのうち第３位置Ｐ３に最も近いソース／コンタクト接合領域３８Ａと、第３位置Ｐ３との距離は、３２μｍ程度である。 In this embodiment, the distance M3 between the source/contact junction region 38A closest to the third position P3 among the source/contact junction regions 38A to which the first source pad 121 is bonded and the third position P3 is approximately 32 μm. Also, the distance between the source/contact junction region 38A closest to the third position P3 among the source/contact junction regions 38A to which the second source pad 122 is bonded and the third position P3 is approximately 32 μm.
　この半導体装置１では、ゲート接続導電膜５０ａ，３８ｂの下面の各位置とそれに最も近いソース／コンタクト接合領域３８Ａ，９２Ａ，９２Ｂとの距離の最大値が９０μｍ以下となるように、ゲート接続導電膜５０ａ，３８ｂおよびソース／コンタクト接合領域３８Ａ，９２Ａ，９２Ｂのレイアウトが設計されている。これにより、ＭＩＳＦＥＴのスイッチング時に発生する電圧ＶＤＳ／ｄｔに起因する主面絶縁膜１６の損傷を抑制できるので、リーク電流の増加を抑制できる。 In this semiconductor device 1, the layout of the gate connection conductive films 50a, 38b and the source/ contact junction regions 38A, 92A, 92B is designed so that the maximum distance between each position on the underside of the gate connection conductive films 50a, 38b and the nearest source/ contact junction regions 38A, 92A, 92B is 90 μm or less. This makes it possible to suppress damage to the main surface insulating film 16 caused by the voltage V DS /dt generated during switching of the MISFET, and therefore to suppress an increase in leakage current.
　半導体装置１は、チップ２、ゲート抵抗４０、ゲートパッド１０１およびゲート配線１０２を含む。チップ２は、第１主面３を有している。ゲート抵抗４０は、第１主面３に形成されたトレンチ抵抗構造４１を含む。ゲートパッド１０１は、トレンチ抵抗構造４１よりも低い抵抗値を有し、トレンチ抵抗構造４１に電気的に接続されるように第１主面３の上に配置されている。ゲート配線１０２は、トレンチ抵抗構造４１よりも低い抵抗値を有し、トレンチ抵抗構造４１を介してゲートパッド１０１に電気的に接続されるように第１主面３の上に配置されている。 The semiconductor device 1 includes a chip 2, a gate resistor 40, a gate pad 101, and a gate wiring 102. The chip 2 has a first main surface 3. The gate resistor 40 includes a trench resistor structure 41 formed on the first main surface 3. The gate pad 101 has a lower resistance value than the trench resistor structure 41, and is disposed on the first main surface 3 so as to be electrically connected to the trench resistor structure 41. The gate wiring 102 has a lower resistance value than the trench resistor structure 41, and is disposed on the first main surface 3 so as to be electrically connected to the gate pad 101 via the trench resistor structure 41.
　この構造によれば、ゲートパッド１０１およびゲート配線１０２の間の領域においてトレンチ抵抗構造４１がチップ２内に組み込まれているため、第１主面３に対するゲート抵抗４０の専有面積を制限できる。ゲート抵抗４０の抵抗値は、トレンチ抵抗構造４１の深さや長さを調整することによって調節される。したがって、第１主面３に対するゲート抵抗４０の専有面積の増加を抑制できる。よって、ゲート抵抗４０を備えた構成において、小型化に寄与する新規なレイアウトを有する半導体装置１を提供できる。 With this structure, the trench resistance structure 41 is incorporated in the chip 2 in the region between the gate pad 101 and the gate wiring 102, so that the area occupied by the gate resistance 40 on the first main surface 3 can be limited. The resistance value of the gate resistance 40 is adjusted by adjusting the depth and length of the trench resistance structure 41. Therefore, an increase in the area occupied by the gate resistance 40 on the first main surface 3 can be suppressed. Therefore, in a configuration including the gate resistance 40, a semiconductor device 1 can be provided that has a novel layout that contributes to miniaturization.
　このような構造において、ゲートパッド１０１は、トレンチ抵抗構造４１の直上に位置する部分を有していることが好ましい。この構造によれば、ゲートパッド１０１の直下の領域にゲート抵抗４０が配置されるため、第１主面３に対するゲート抵抗４０の専有面積の増加を抑制できる。また、ゲート配線１０２は、トレンチ抵抗構造４１の直上に位置する部分を有していることが好ましい。この構造によれば、ゲート配線１０２の直下の領域にゲート抵抗４０が配置されるため、第１主面３に対するゲート抵抗４０の専有面積の増加を抑制できる。 In such a structure, it is preferable that the gate pad 101 has a portion located directly above the trench resistance structure 41. With this structure, the gate resistor 40 is disposed in a region directly below the gate pad 101, so that an increase in the area occupied by the gate resistor 40 with respect to the first main surface 3 can be suppressed. It is also preferable that the gate wiring 102 has a portion located directly above the trench resistance structure 41. With this structure, it is preferable that the gate resistor 40 is disposed in a region directly below the gate wiring 102, so that an increase in the area occupied by the gate resistor 40 with respect to the first main surface 3 can be suppressed.
　トレンチ抵抗構造４１は、チャネルの制御に寄与しないことが好ましい。この構造によれば、トレンチ抵抗構造４１に起因する誤動作を適切に抑制できる。ゲート抵抗４０は、トレンチ抵抗構造４１を被覆する抵抗膜５０を含むことが好ましい。この構造によれば、トレンチ抵抗構造４１および抵抗膜５０の双方を利用してゲート抵抗４０の抵抗値を調節できる。 It is preferable that the trench resistance structure 41 does not contribute to channel control. With this structure, malfunctions caused by the trench resistance structure 41 can be appropriately suppressed. It is preferable that the gate resistance 40 includes a resistive film 50 that covers the trench resistance structure 41. With this structure, the resistance value of the gate resistance 40 can be adjusted by utilizing both the trench resistance structure 41 and the resistive film 50.
　この場合、ゲートパッド１０１は、抵抗膜５０を介してトレンチ抵抗構造４１に電気的に接続されることが好ましい。この構造によれば、抵抗膜５０によってゲートパッド１０１をトレンチ抵抗構造４１に適切に電気的に接続させることができる。ゲートパッド１０１は、抵抗膜５０を挟んでトレンチ抵抗構造４１に対向する部分を有していることが好ましい。 In this case, it is preferable that the gate pad 101 is electrically connected to the trench resistance structure 41 via the resistive film 50. With this structure, the gate pad 101 can be appropriately electrically connected to the trench resistance structure 41 by the resistive film 50. It is preferable that the gate pad 101 has a portion that faces the trench resistance structure 41 with the resistive film 50 in between.
　ゲート配線１０２は、抵抗膜５０を介してトレンチ抵抗構造４１に電気的に接続されることが好ましい。この構造によれば、抵抗膜５０によってゲート配線１０２をトレンチ抵抗構造４１に適切に電気的に接続させることができる。この場合、ゲート配線１０２は、抵抗膜５０を挟んでトレンチ抵抗構造４１に対向する部分を有していることが好ましい。 The gate wiring 102 is preferably electrically connected to the trench resistance structure 41 via the resistive film 50. With this structure, the resistive film 50 can properly electrically connect the gate wiring 102 to the trench resistance structure 41. In this case, it is preferable that the gate wiring 102 has a portion that faces the trench resistance structure 41 across the resistive film 50.
　抵抗膜５０は、第１主面３を被覆する部分、および、トレンチ抵抗構造４１を被覆する部分を有していてもよい。この構造によれば、第１主面３上の領域およびトレンチ抵抗構造４１上の領域を利用して抵抗膜５０の抵抗値を調節できる。また、抵抗膜５０に対するゲートパッド１０１のアライメント誤差に起因する影響、および、ゲート配線１０２のアライメント誤差に起因する影響を低減できる。この場合、ゲートパッド１０１は、抵抗膜５０を挟んで第１主面３に対向する部分を有していてもよい。また、ゲート配線１０２は、抵抗膜５０を挟んで第１主面３に対向する部分を有していてもよい。 The resistive film 50 may have a portion covering the first main surface 3 and a portion covering the trench resistance structure 41. With this structure, the resistance value of the resistive film 50 can be adjusted by utilizing the region on the first main surface 3 and the region on the trench resistance structure 41. Also, the influence caused by the alignment error of the gate pad 101 with respect to the resistive film 50 and the influence caused by the alignment error of the gate wiring 102 can be reduced. In this case, the gate pad 101 may have a portion facing the first main surface 3 across the resistive film 50. Also, the gate wiring 102 may have a portion facing the first main surface 3 across the resistive film 50.
　半導体装置１は、抵抗膜５０を被覆する層間絶縁膜９９を含んでいてもよい。この場合、ゲートパッド１０１は、層間絶縁膜９９を貫通して抵抗膜５０に接続されることが好ましい。また、ゲート配線１０２は、層間絶縁膜９９を貫通して抵抗膜５０に接続されることが好ましい。 The semiconductor device 1 may include an interlayer insulating film 99 that covers the resistive film 50. In this case, it is preferable that the gate pad 101 penetrates the interlayer insulating film 99 and is connected to the resistive film 50. It is also preferable that the gate wiring 102 penetrates the interlayer insulating film 99 and is connected to the resistive film 50.
　複数のトレンチ抵抗構造４１が、第１主面３に形成されていることが好ましい。この構造によれば、複数のトレンチ抵抗構造４１を利用してゲート抵抗４０の抵抗値を調節できる。複数のトレンチ抵抗構造４１は、第１トレンチ抵抗構造４２、および、第１トレンチ抵抗構造４２よりも深い第２トレンチ抵抗構造４３を含むことが好ましい。 A plurality of trench resistance structures 41 are preferably formed on the first main surface 3. With this structure, the resistance value of the gate resistor 40 can be adjusted using the plurality of trench resistance structures 41. The plurality of trench resistance structures 41 preferably include a first trench resistance structure 42 and a second trench resistance structure 43 that is deeper than the first trench resistance structure 42.
　この構造によれば、互いに異なる深さを有する第１トレンチ抵抗構造４２および第２トレンチ４７構造を利用してゲート抵抗４０の抵抗値を調節できる。特に、第２トレンチ抵抗構造４３によればチップ２の厚さ方向にゲート抵抗４０の高抵抗化を図ることができる。したがって、たとえば、抵抗膜５０が設けられる場合には、抵抗膜５０の膜厚を削減することもできる。 With this structure, the resistance value of the gate resistor 40 can be adjusted by utilizing the first trench resistor structure 42 and the second trench 47 structure, which have different depths. In particular, the second trench resistor structure 43 can increase the resistance of the gate resistor 40 in the thickness direction of the chip 2. Therefore, for example, when a resistive film 50 is provided, the film thickness of the resistive film 50 can also be reduced.
　半導体装置１は、活性領域１２、外周領域１３および終端領域１５を含むことが好ましい。活性領域１２は、第１主面３の内方部に設けられる。外周領域１３は、第１主面３の周縁部に設けられる。終端領域１５は、活性領域１２および外周領域１３の間に設けられる。このようなレイアウトにおいて、トレンチ抵抗構造４１は、終端領域１５に形成されることが好ましい。このレイアウトによれば、ゲート抵抗４０の導入に伴う活性領域１２の面積の縮小を適切に抑制できる。 The semiconductor device 1 preferably includes an active region 12, a peripheral region 13, and a termination region 15. The active region 12 is provided in an inner portion of the first main surface 3. The peripheral region 13 is provided in a peripheral portion of the first main surface 3. The termination region 15 is provided between the active region 12 and the peripheral region 13. In such a layout, the trench resistor structure 41 is preferably formed in the termination region 15. With this layout, it is possible to appropriately suppress the reduction in the area of the active region 12 that accompanies the introduction of the gate resistor 40.
　この場合、ゲートパッド１０１は、終端領域１５においてトレンチ抵抗構造４１に電気的に接続されることが好ましい。また、ゲート配線１０２は、終端領域１５においてトレンチ抵抗構造４１を介してゲートパッド１０１に電気的に接続されることが好ましい。 In this case, it is preferable that the gate pad 101 is electrically connected to the trench resistance structure 41 in the termination region 15. It is also preferable that the gate wiring 102 is electrically connected to the gate pad 101 via the trench resistance structure 41 in the termination region 15.
　半導体装置１は、活性領域１２において第１主面３に形成されたトレンチゲート構造２０を含むことが好ましい。この場合、ゲート配線１０２は、活性領域１２においてトレンチゲート構造２０に電気的に接続されることが好ましい。この構造によれば、ゲートパッド１０１およびトレンチゲート構造２０の間にゲート抵抗４０（トレンチ抵抗構造４１）を電気的に介在させることができる。 The semiconductor device 1 preferably includes a trench gate structure 20 formed on the first main surface 3 in the active region 12. In this case, the gate wiring 102 is preferably electrically connected to the trench gate structure 20 in the active region 12. With this structure, a gate resistor 40 (trench resistor structure 41) can be electrically interposed between the gate pad 101 and the trench gate structure 20.
　半導体装置１は、活性領域１２においてトレンチゲート構造２０に隣り合うように第１主面３に形成され、ソース電位ＶＳが付与される第１トレンチソース構造２５を含んでいてもよい。この場合、第１トレンチソース構造２５は、トレンチゲート構造２０よりも深く形成されていてもよい。このような構造において、複数のトレンチ抵抗構造４１は、トレンチゲート構造２０に対応して比較的浅く形成された第１トレンチ抵抗構造４２、および、第１トレンチソース構造２５に対応して比較的深く形成された第２トレンチ抵抗構造４３を含むことが好ましい。 The semiconductor device 1 may include a first trench source structure 25 formed on the first main surface 3 adjacent to the trench gate structure 20 in the active region 12 and to which a source potential VS is applied. In this case, the first trench source structure 25 may be formed deeper than the trench gate structure 20. In such a structure, the multiple trench resistance structures 41 preferably include a first trench resistance structure 42 formed relatively shallow in correspondence with the trench gate structure 20, and a second trench resistance structure 43 formed relatively deep in correspondence with the first trench source structure 25.
　この構造によれば、活性領域１２および終端領域１５の間で対応する構造が形成されるため、活性領域１２および終端領域１５の間で電界の偏りを抑制できる。したがって、活性領域１２に対するゲート抵抗４０の電気的な影響が抑制され、ゲート抵抗４０に対する活性領域１２の電気的な影響が抑制される。この場合、第１トレンチ抵抗構造４２は、トレンチゲート構造２０とほぼ等しい深さを有していることが好ましい。また、第２トレンチ抵抗構造４３は、第１トレンチソース構造２５とほぼ等しい深さを有していることが好ましい。 With this structure, a corresponding structure is formed between the active region 12 and the termination region 15, so that the bias of the electric field between the active region 12 and the termination region 15 can be suppressed. Therefore, the electrical influence of the gate resistor 40 on the active region 12 is suppressed, and the electrical influence of the active region 12 on the gate resistor 40 is suppressed. In this case, it is preferable that the first trench resistor structure 42 has a depth approximately equal to that of the trench gate structure 20. Also, it is preferable that the second trench resistor structure 43 has a depth approximately equal to that of the first trench source structure 25.
　半導体装置１は、終端領域１５においてトレンチ抵抗構造４１に隣り合うように第１主面３に形成され、ダミートレンチ構造６０をさらに含むことが好ましい。ダミートレンチ構造６０は、チャネルの制御に寄与しないことが好ましい。この構造によれば、トレンチ抵抗構造４１に起因する誤動作を適切に抑制できる。 The semiconductor device 1 preferably further includes a dummy trench structure 60 formed on the first main surface 3 so as to be adjacent to the trench resistance structure 41 in the termination region 15. The dummy trench structure 60 preferably does not contribute to channel control. With this structure, malfunctions caused by the trench resistance structure 41 can be appropriately suppressed.
　ダミートレンチ構造６０には、ソース電位ＶＳが付与されることが好ましい。この構造によれば、トレンチ抵抗構造４１の近傍の領域における電界をダミートレンチ構造６０によって緩和できる。この場合、複数のダミートレンチ構造６０が第１主面３に形成されていることが好ましい。この構造によれば、終端領域１５においてトレンチ抵抗構造４１の近傍の電界を複数のダミートレンチ構造６０によって緩和できる。 It is preferable that a source potential VS is applied to the dummy trench structure 60. With this structure, the electric field in the region near the trench resistance structure 41 can be alleviated by the dummy trench structure 60. In this case, it is preferable that a plurality of dummy trench structures 60 are formed on the first main surface 3. With this structure, the electric field in the region near the trench resistance structure 41 in the termination region 15 can be alleviated by the plurality of dummy trench structures 60.
　複数のダミートレンチ構造６０は、第１ダミートレンチ構造６１、および、第１ダミートレンチ構造６１よりも深い第２ダミートレンチ構造６２を含むことが好ましい。この構造によれば、トレンチ抵抗構造４１の近傍の電界を第１ダミートレンチ構造６１および第２ダミートレンチ構造６２によって緩和できる。 The multiple dummy trench structures 60 preferably include a first dummy trench structure 61 and a second dummy trench structure 62 that is deeper than the first dummy trench structure 61. With this structure, the electric field near the trench resistor structure 41 can be alleviated by the first dummy trench structure 61 and the second dummy trench structure 62.
　このような構造は、活性領域１２においてトレンチゲート構造２０よりも深い第１トレンチソース構造２５が形成されている場合に特に有効である。また、このような構造は、終端領域１５において第１トレンチ抵抗構造４２よりも深い第２トレンチ抵抗構造４３が形成されている場合に特に有効である。 This structure is particularly effective when a first trench source structure 25 that is deeper than the trench gate structure 20 is formed in the active region 12. This structure is also particularly effective when a second trench resistor structure 43 that is deeper than the first trench resistor structure 42 is formed in the termination region 15.
　半導体装置１は、第１主面３の内方部に形成された活性面８、活性面８からチップ２の厚さ方向に窪むように第１主面３の周縁部に形成された外周面９、ならびに、活性面８および外周面９を接続する第１～第４接続面１０Ａ～１０Ｄによって第１主面３に区画された活性台地１１を含んでいてもよい。この場合、活性領域１２は活性面８に設けられ、外周領域１３は外周面９に設けられ、終端領域１５は、活性面８に設けられる。 The semiconductor device 1 may include an active surface 8 formed on the inner side of the first main surface 3, an outer peripheral surface 9 formed on the periphery of the first main surface 3 so as to be recessed from the active surface 8 in the thickness direction of the chip 2, and an active plateau 11 defined on the first main surface 3 by first to fourth connection surfaces 10A to 10D connecting the active surface 8 and the outer peripheral surface 9. In this case, the active region 12 is provided on the active surface 8, the outer peripheral region 13 is provided on the outer peripheral surface 9, and the termination region 15 is provided on the active surface 8.
　半導体装置１は、第１主面３の表層部に形成されたｎ型の第１半導体領域６を含むことが好ましい。この場合、トレンチ抵抗構造４１は、第１半導体領域６内に位置するように第１主面３に形成される。 The semiconductor device 1 preferably includes an n-type first semiconductor region 6 formed in a surface layer of the first main surface 3. In this case, the trench resistor structure 41 is formed in the first main surface 3 so as to be located within the first semiconductor region 6.
　このような構造において、半導体装置１は、第１半導体領域６とｐｎ接合部を形成するように第１半導体領域６内においてトレンチ抵抗構造４１に沿う領域に形成されたｐ型の第４ウェル領域７５（第５ウェル領域７６）を含むことが好ましい。この構造によれば、第４ウェル領域７５（第５ウェル領域７６）を起点に拡がる空乏層によって耐圧（たとえばブレークダウン電圧）を向上できる。 In such a structure, the semiconductor device 1 preferably includes a p-type fourth well region 75 (fifth well region 76) formed in a region along the trench resistor structure 41 in the first semiconductor region 6 so as to form a pn junction with the first semiconductor region 6. With this structure, the breakdown voltage (e.g., breakdown voltage) can be improved by the depletion layer that spreads from the fourth well region 75 (fifth well region 76).
　半導体装置１は、トレンチ抵抗構造４１よりも低い抵抗値を有し、トレンチ抵抗構造４１を介してゲートパッド１０１に電気的に接続されるように第１主面３の上に配置されたゲートサブパッド１０３を含んでいてもよい。 The semiconductor device 1 may include a gate subpad 103 arranged on the first main surface 3 so as to have a lower resistance value than the trench resistor structure 41 and to be electrically connected to the gate pad 101 via the trench resistor structure 41.
　この構造によれば、ゲートパッド１０１およびゲートサブパッド１０３の間の抵抗値を測定することによって、ゲートパッド１０１およびゲート配線１０２の間の抵抗値を間接的に測定できる。ゲートサブパッド１０３は、ゲートパッド１０１よりも幅狭に形成され、ゲート配線１０２よりも幅広に形成されていることが好ましい。ゲートサブパッド１０３は、ゲート配線１０２に接続されていてもよい。 With this structure, the resistance between the gate pad 101 and the gate wiring 102 can be indirectly measured by measuring the resistance between the gate pad 101 and the gate subpad 103. It is preferable that the gate subpad 103 is formed narrower than the gate pad 101 and wider than the gate wiring 102. The gate subpad 103 may be connected to the gate wiring 102.
　半導体装置１は、外周領域１３において第１主面３の表層部に形成されたｐ型のアウターウェル領域９１を含んでいてもよい。この構造によれば、アウターウェル領域９１によって外周領域１３の電界を緩和できる。半導体装置１は、外周領域１３において第１主面３の表層部に形成された少なくとも１つのｐ型のフィールド領域９３を含んでいてもよい。この構造によれば、フィールド領域９３によって外周領域１３の電界を緩和できる。 The semiconductor device 1 may include a p-type outer well region 91 formed in the surface layer of the first main surface 3 in the peripheral region 13. With this structure, the outer well region 91 can reduce the electric field in the peripheral region 13. The semiconductor device 1 may include at least one p-type field region 93 formed in the surface layer of the first main surface 3 in the peripheral region 13. With this structure, the field region 93 can reduce the electric field in the peripheral region 13.
　別視点において、半導体装置１は、チップ２、第１トレンチ抵抗構造４２（第１溝構造）、第１ダミートレンチ構造６１（第２溝構造）、第２トレンチ抵抗構造４３（第３溝構造）、第２ダミートレンチ構造６２（第４溝構造）、第１メサ部７１および第２メサ部７２を含む。チップ２は、第１主面３を有している。第１トレンチ抵抗構造４２は、第１主面３に形成されている。第１ダミートレンチ構造６１は、第１方向Ｘに第１トレンチ抵抗構造４２に隣り合うように第１主面３に形成されている。 From another perspective, the semiconductor device 1 includes a chip 2, a first trench resistance structure 42 (first groove structure), a first dummy trench structure 61 (second groove structure), a second trench resistance structure 43 (third groove structure), a second dummy trench structure 62 (fourth groove structure), a first mesa portion 71 and a second mesa portion 72. The chip 2 has a first main surface 3. The first trench resistance structure 42 is formed on the first main surface 3. The first dummy trench structure 61 is formed on the first main surface 3 so as to be adjacent to the first trench resistance structure 42 in the first direction X.
　第２トレンチ抵抗構造４３は、第１方向Ｘに直交する第２方向Ｙに第１トレンチ抵抗構造４２に隣り合うように第１主面３に形成されている。第２ダミートレンチ構造６２は、第１方向Ｘに第２トレンチ抵抗構造４３に隣り合うように第１主面３に形成されている。第１メサ部７１は、第１トレンチ抵抗構造４２および第１ダミートレンチ構造６１の間の領域に区画されている。第２メサ部７２は、第２トレンチ抵抗構造４３および第２ダミートレンチ構造６２の間の領域において第１メサ部７１に対して第１方向Ｘにずれて区画されている。 The second trench resistance structure 43 is formed on the first main surface 3 so as to be adjacent to the first trench resistance structure 42 in a second direction Y perpendicular to the first direction X. The second dummy trench structure 62 is formed on the first main surface 3 so as to be adjacent to the second trench resistance structure 43 in the first direction X. The first mesa portion 71 is defined in the region between the first trench resistance structure 42 and the first dummy trench structure 61. The second mesa portion 72 is defined in the region between the second trench resistance structure 43 and the second dummy trench structure 62, shifted in the first direction X with respect to the first mesa portion 71.
　この構造によれば、第２メサ部７２に生じる電界が第１メサ部７１に生じる電界に干渉することを抑制できる。これにより、第１メサ部７１に対する電界集中および第２メサ部７２に対する電界集中を抑制できる。よって、耐圧（たとえばブレークダウン電圧）を向上できる新規なレイアウトを有する半導体装置１を提供できる。 This structure makes it possible to prevent the electric field generated in the second mesa portion 72 from interfering with the electric field generated in the first mesa portion 71. This makes it possible to prevent electric field concentration in the first mesa portion 71 and electric field concentration in the second mesa portion 72. This makes it possible to provide a semiconductor device 1 having a novel layout that can improve the withstand voltage (e.g., breakdown voltage).
　このような構造は、第１ダミートレンチ構造６１および第１トレンチ抵抗構造４２の間の電位差に起因する電界が第１メサ部７１に生じ、第２ダミートレンチ構造６２および第２トレンチ抵抗構造４３の間の電位差に起因する電界が第２メサ部７２に生じる場合において特に有効である。したがって、第１ダミートレンチ構造６１には第１トレンチ抵抗構造４２とは異なる電位が印加され、第２ダミートレンチ構造６２には第２トレンチ抵抗構造４３とは異なる電位が印加されてもよい。 Such a structure is particularly effective in the case where an electric field caused by a potential difference between the first dummy trench structure 61 and the first trench resistance structure 42 occurs in the first mesa portion 71, and an electric field caused by a potential difference between the second dummy trench structure 62 and the second trench resistance structure 43 occurs in the second mesa portion 72. Therefore, a potential different from that applied to the first dummy trench structure 61 and that applied to the first trench resistance structure 42 may be applied to the second dummy trench structure 62 and that applied to the second trench resistance structure 43.
　第１トレンチ抵抗構造４２および第２トレンチ抵抗構造４３には第１電位が印加され、第１ダミートレンチ構造６１および第２ダミートレンチ構造６２には第１電位とは異なる第２電位が印加されてもよい。第１電位はゲート電位ＶＧであってもよく、第２電位はソース電位ＶＳであってもよい。 A first potential may be applied to the first trench resistance structure 42 and the second trench resistance structure 43, and a second potential different from the first potential may be applied to the first dummy trench structure 61 and the second dummy trench structure 62. The first potential may be a gate potential VG, and the second potential may be a source potential VS.
　第２ダミートレンチ構造６２は、第２方向Ｙに第１ダミートレンチ構造６１に隣り合うように第１主面３に形成されていることが好ましい。第２トレンチ抵抗構造４３は、第１トレンチ抵抗構造４２よりも深く形成されていてもよい。この場合、第２ダミートレンチ構造６２は、第１ダミートレンチ構造６１よりも深く形成されていることが好ましい。 The second dummy trench structure 62 is preferably formed on the first main surface 3 so as to be adjacent to the first dummy trench structure 61 in the second direction Y. The second trench resistance structure 43 may be formed deeper than the first trench resistance structure 42. In this case, the second dummy trench structure 62 is preferably formed deeper than the first dummy trench structure 61.
　この構造によれば、第１トレンチ抵抗構造４２および第２トレンチ抵抗構造４３の間の深度の違いに起因した電界の偏りを緩和できる。この場合、第１ダミートレンチ構造６１は、第１トレンチ抵抗構造４２とほぼ等しい深さで形成されていることが好ましい。また、第２ダミートレンチ構造６２は、第２トレンチ抵抗構造４３とほぼ等しい深さで形成されていることが好ましい。 This structure can alleviate the bias in the electric field caused by the difference in depth between the first trench resistance structure 42 and the second trench resistance structure 43. In this case, it is preferable that the first dummy trench structure 61 is formed to a depth approximately equal to that of the first trench resistance structure 42. It is also preferable that the second dummy trench structure 62 is formed to a depth approximately equal to that of the second trench resistance structure 43.
　半導体装置１は、第１トレンチ抵抗構造４２および第２トレンチ抵抗構造４３の間に区画されたメインメサ部７０を含む。この場合、第１メサ部７１および第２メサ部７２は、メインメサ部７０に接続される。第１メサ部７１の第１方向Ｘの幅は、メインメサ部７０の第２方向Ｙの幅の０．５倍以上２倍以下であることが好ましい。また、第２メサ部７２の第１方向Ｘの幅は、メインメサ部７０の第２方向Ｙの幅の０．５倍以上２倍以下であることが好ましい。 The semiconductor device 1 includes a main mesa portion 70 defined between the first trench resistor structure 42 and the second trench resistor structure 43. In this case, the first mesa portion 71 and the second mesa portion 72 are connected to the main mesa portion 70. It is preferable that the width in the first direction X of the first mesa portion 71 is 0.5 to 2 times the width in the second direction Y of the main mesa portion 70. It is also preferable that the width in the first direction X of the second mesa portion 72 is 0.5 to 2 times the width in the second direction Y of the main mesa portion 70.
　第１トレンチ抵抗構造４２は、第１方向Ｘに帯状に延びていることが好ましい。第２トレンチ抵抗構造４３は、第１方向Ｘに帯状に延びていることが好ましい。第１ダミートレンチ構造６１は、第１方向Ｘに帯状に延びていることが好ましい。第２ダミートレンチ構造６２は、第１方向Ｘに帯状に延びていることが好ましい。 The first trench resistor structure 42 preferably extends in a strip shape in the first direction X. The second trench resistor structure 43 preferably extends in a strip shape in the first direction X. The first dummy trench structure 61 preferably extends in a strip shape in the first direction X. The second dummy trench structure 62 preferably extends in a strip shape in the first direction X.
　半導体装置１は、第１主面３の内方部に形成された活性面８、活性面８からチップ２の厚さ方向に窪むように第１主面３の周縁部に形成された外周面９、ならびに、活性面８および外周面９を接続する第１～第４接続面１０Ａ～１０Ｄによって第１主面３に区画された活性台地１１を含んでいてもよい。この場合、第１トレンチ抵抗構造４２、第２トレンチ抵抗構造４３、第１ダミートレンチ構造６１および第２ダミートレンチ構造６２は、活性面８に形成されていることが好ましい。 The semiconductor device 1 may include an active surface 8 formed on the inner portion of the first main surface 3, an outer peripheral surface 9 formed on the periphery of the first main surface 3 so as to be recessed from the active surface 8 in the thickness direction of the chip 2, and an active plateau 11 defined on the first main surface 3 by first to fourth connection surfaces 10A to 10D connecting the active surface 8 and the outer peripheral surface 9. In this case, the first trench resistor structure 42, the second trench resistor structure 43, the first dummy trench structure 61, and the second dummy trench structure 62 are preferably formed on the active surface 8.
　第１トレンチ抵抗構造４２および第２トレンチ抵抗構造４３は、第１～第４接続面１０Ａ～１０Ｄから間隔を空けて活性面８に形成されていることが好ましい。第１ダミートレンチ構造６１は、第３接続面１０Ｃ（第４接続面１０Ｄ）から露出するように活性面８に形成されていてもよい。また、第２ダミートレンチ構造６２は、第３接続面１０Ｃ（第４接続面１０Ｄ）から露出するように活性面８に形成されていてもよい。 The first trench resistor structure 42 and the second trench resistor structure 43 are preferably formed on the active surface 8 at a distance from the first to fourth connection surfaces 10A to 10D. The first dummy trench structure 61 may be formed on the active surface 8 so as to be exposed from the third connection surface 10C (fourth connection surface 10D). The second dummy trench structure 62 may be formed on the active surface 8 so as to be exposed from the third connection surface 10C (fourth connection surface 10D).
　半導体装置１は、第１～第４接続面１０Ａ～１０Ｄの少なくとも１つを被覆するように外周面９の上に配置されたサイドウォール構造を含んでいてもよい。この場合、サイドウォール構造は、第１ダミートレンチ構造６１および第２ダミートレンチ構造６２に電気的に接続されたサイドウォール配線９５からなることが好ましい。この構造によれば、サイドウォール配線９５によって、第１トレンチ抵抗構造４２および第２トレンチ抵抗構造４３に対する電位とは異なる電位を外周面９側から第１ダミートレンチ構造６１および第２ダミートレンチ構造６２に付与できる。 The semiconductor device 1 may include a sidewall structure disposed on the outer peripheral surface 9 so as to cover at least one of the first to fourth connection surfaces 10A to 10D. In this case, the sidewall structure preferably comprises a sidewall wiring 95 electrically connected to the first dummy trench structure 61 and the second dummy trench structure 62. With this structure, the sidewall wiring 95 can apply a potential different from the potentials applied to the first trench resistance structure 42 and the second trench resistance structure 43 to the first dummy trench structure 61 and the second dummy trench structure 62 from the outer peripheral surface 9 side.
　半導体装置１は、第１主面３の表層部に形成されたｎ型の第１半導体領域６を含んでいてもよい。半導体装置１は、第１半導体領域６の表層部に形成されたｐ型のボディ領域１７を含んでいてもよい。この場合、第１トレンチ抵抗構造４２、第２トレンチ抵抗構造４３、第１ダミートレンチ構造６１および第２ダミートレンチ構造６２は、第１半導体領域６に至るようにボディ領域１７を貫通していることが好ましい。 The semiconductor device 1 may include an n-type first semiconductor region 6 formed in a surface layer portion of the first main surface 3. The semiconductor device 1 may include a p-type body region 17 formed in a surface layer portion of the first semiconductor region 6. In this case, it is preferable that the first trench resistance structure 42, the second trench resistance structure 43, the first dummy trench structure 61, and the second dummy trench structure 62 penetrate the body region 17 to reach the first semiconductor region 6.
　第１トレンチ抵抗構造４２および第２トレンチ抵抗構造４３は、チャネルの制御に寄与しないことが好ましい。この構造によれば、この構造によれば、第１トレンチ抵抗構造４２および第２トレンチ抵抗構造４３に起因する誤動作を適切に抑制できる。第１ダミートレンチ構造６１および第２ダミートレンチ構造６２は、チャネルの制御に寄与しないことが好ましい。この構造によれば、この構造によれば、第１ダミートレンチ構造６１および第２ダミートレンチ構造６２に起因する誤動作を適切に抑制できる。 It is preferable that the first trench resistance structure 42 and the second trench resistance structure 43 do not contribute to channel control. According to this structure, malfunctions caused by the first trench resistance structure 42 and the second trench resistance structure 43 can be appropriately suppressed. It is preferable that the first dummy trench structure 61 and the second dummy trench structure 62 do not contribute to channel control. According to this structure, it is possible to appropriately suppress malfunctions caused by the first dummy trench structure 61 and the second dummy trench structure 62.
　半導体装置１は、第１半導体領域６内において第２トレンチ抵抗構造４３に沿う領域に形成されたｐ型の第２コンタクト領域７９を含んでいてもよい。この場合、第２コンタクト領域７９は、第２メサ部７２から間隔を空けて第２トレンチ抵抗構造４３に沿う領域に形成されていることが好ましい。 The semiconductor device 1 may include a p-type second contact region 79 formed in a region along the second trench resistance structure 43 in the first semiconductor region 6. In this case, the second contact region 79 is preferably formed in a region along the second trench resistance structure 43 and spaced apart from the second mesa portion 72.
　第２コンタクト領域７９は、第１メサ部７１に対して第１方向Ｘにずれて形成されていることが特に好ましい。この場合、第２コンタクト領域７９は、第２方向Ｙに第１メサ部７１に対向しないことが好ましい。この構造によれば、第１メサ部７１に係る電界および第２メサ部７２に係る電界を適切に緩和できる。 It is particularly preferable that the second contact region 79 is formed offset in the first direction X with respect to the first mesa portion 71. In this case, it is preferable that the second contact region 79 does not face the first mesa portion 71 in the second direction Y. With this structure, the electric field associated with the first mesa portion 71 and the electric field associated with the second mesa portion 72 can be appropriately alleviated.
　半導体装置１は、第１半導体領域６内において第２ダミートレンチ構造６２に沿う領域に形成されたｐ型の第３コンタクト領域８０を含んでいてもよい。この場合、第３コンタクト領域８０は、第２メサ部７２から間隔を空けて第２ダミートレンチ構造６２に沿う領域に形成されていることが好ましい。第３コンタクト領域８０は、第１メサ部７１に対して第１方向Ｘにずれて形成されていることが特に好ましい。この場合、第３コンタクト領域８０は、第２方向Ｙに第１メサ部７１に対向しないことが好ましい。 The semiconductor device 1 may include a p-type third contact region 80 formed in a region along the second dummy trench structure 62 in the first semiconductor region 6. In this case, the third contact region 80 is preferably formed in a region along the second dummy trench structure 62 with a gap therebetween from the second mesa portion 72. It is particularly preferable that the third contact region 80 is formed shifted in the first direction X with respect to the first mesa portion 71. In this case, it is preferable that the third contact region 80 does not face the first mesa portion 71 in the second direction Y.
　チップ２は、ワイドバンドギャップ半導体の単結晶を含むことが好ましい。ワイドバンドギャップ半導体の単結晶は、電気的特性を向上させる上で有効である。また、ワイドバンドギャップ半導体の単結晶によれば、比較的高い硬度によってチップ２の変形を抑制しながら、チップ２の薄化およびチップ２の平面積の増加を達成できる。 The chip 2 preferably includes a single crystal of a wide band gap semiconductor. A single crystal of a wide band gap semiconductor is effective in improving electrical characteristics. Furthermore, the single crystal of a wide band gap semiconductor has a relatively high hardness, which suppresses deformation of the chip 2, while allowing the chip 2 to be thinned and the surface area of the chip 2 to be increased.
　チップ２の薄化およびチップ２の平面積の拡張は、電気的特性を向上させる上でも有効である。たとえば、チップ２は、平面視において１ｍｍ角以上の面積を有する第１主面３を有していてもよい。たとえば、チップ２は、２００μｍ以下の厚さを有していてもよい。チップ２は、断面視において１００μｍ以下の厚さを有していることが好ましい。 Thinning the chip 2 and expanding the planar area of the chip 2 are also effective in improving electrical characteristics. For example, the chip 2 may have a first main surface 3 having an area of 1 mm square or more in a plan view. For example, the chip 2 may have a thickness of 200 μm or less. It is preferable that the chip 2 has a thickness of 100 μm or less in a cross-sectional view.
　前述の実施形態はさらに他の形態で実施できる。前述の各実施形態では、「第１導電型」が「ｎ型」であり、「第２導電型」が「ｐ型」である形態が示された。しかし、前述の各実施形態において、「第１導電型」が「ｐ型」であり、「第２導電型」が「ｎ型」である形態が採用されてもよい。この場合の具体的な構成は、前述の説明および添付図面において、「ｎ型」を「ｐ型」に置き換えると同時に、「ｐ型」を「ｎ型」に置き換えることによって得られる。 The above-described embodiments can be implemented in other forms. In each of the above-described embodiments, a form in which the "first conductivity type" is "n-type" and the "second conductivity type" is "p-type" has been shown. However, each of the above-described embodiments may also adopt a form in which the "first conductivity type" is "p-type" and the "second conductivity type" is "n-type". A specific configuration in this case can be obtained by replacing "n-type" with "p-type" and at the same time replacing "p-type" with "n-type" in the above description and the accompanying drawings.
　前述の実施形態では、ｎ型の第２半導体領域７が示された。しかし、ｐ型の第２半導体領域７が採用されてもよい。この場合、ＭＩＳＦＥＴに代えてＩＧＢＴ（Insulated Gate Bipolar Transistor）が形成される。この場合、前述の説明において、ＭＩＳＦＥＴの「ソース」がＩＧＢＴの「エミッタ」に置き換えられ、ＭＩＳＦＥＴの「ドレイン」がＩＧＢＴの「コレクタ」に置き換えられる。ｐ型の第２半導体領域７はイオン注入法によってチップ２の第２主面４の表層部に導入されたｐ型不純物を含む不純物領域であってもよい。 In the above embodiment, an n-type second semiconductor region 7 is shown. However, a p-type second semiconductor region 7 may be adopted. In this case, an IGBT (Insulated Gate Bipolar Transistor) is formed instead of the MISFET. In this case, in the above explanation, the "source" of the MISFET is replaced with the "emitter" of the IGBT, and the "drain" of the MISFET is replaced with the "collector" of the IGBT. The p-type second semiconductor region 7 may be an impurity region containing p-type impurities introduced into the surface layer of the second main surface 4 of the chip 2 by ion implantation.
　以下、この明細書および図面から抽出される特徴例が示される。以下、括弧内の英数字等は前述の実施形態における対応構成要素等を表すが、各項目（Clause）の範囲を実施形態に限定する趣旨ではない。以下の項目に係る「半導体装置」は、必要に応じて「ワイドバンドギャップ半導体装置」、「ＳｉＣ半導体装置」、「半導体スイッチング装置」、「ＳｉＣ－ＭＩＳＦＥＴ」等に置き換えられてもよい。 Below are examples of features extracted from this specification and drawings. Below, alphanumeric characters in parentheses indicate corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each clause to the embodiments. The "semiconductor device" in the following clauses may be replaced with "wide bandgap semiconductor device," "SiC semiconductor device," "semiconductor switching device," "SiC-MISFET," etc., as necessary.
　［Ａ１］　主面（３）を有し、第１導電型の半導体からなるチップ（２）と、
　前記チップ（２）の前記主面（３）側の表層部に選択的に形成された第２導電型の第１領域（１７，３５，３６，３７，７５，７７，７８，９１）と、
　前記主面（３）に形成されたトレンチゲート構造（２０）と、
　前記主面（３）に形成されたトレンチソース構造（２５，３０）と、
　前記主面（３）上に選択的に形成された絶縁膜（１６）と、
　前記主面（３）上に前記絶縁膜（１６）を覆うように配置された層間絶縁膜（９９）と、
　前記層間絶縁膜（９９）上に配置され、前記トレンチゲート構造（２０）にゲート電位を付与するゲート電極（１００）と、
　前記層間絶縁膜（９９）上に配置され、前記トレンチソース構造（２５，３０）にソース電位を付与するソース電極（１２０）と、
　前記絶縁膜（１６）上に形成され、前記ゲート電極（１００）に電気的に接続されたゲート接続導電膜（５０ａ，３９ｂ）と、
　前記第１領域の表層部に選択的に形成され、前記ソース電極（１２０）が電気的に接続される第２導電型のコンタクト領域（３８，９２）とを含み、
　前記コンタクト領域（３８，９２）のうち前記ソース電極（１２０）が接合されている領域をソース／コンタクト接合領域（３８Ａ，９２Ａ，９２Ｂ）とすると、
　前記ゲート接続導電膜（５０ａ，３９ｂ）の下面の各位置とそれに最も近い前記ソース／コンタクト接合領域（３８Ａ，９２Ａ，９２Ｂ）の距離の最大値が９０μｍ以下である、半導体装置。 [A1] A chip (2) having a main surface (3) and made of a first conductivity type semiconductor;
a first region (17, 35, 36, 37, 75, 77, 78, 91) of a second conductivity type selectively formed in a surface layer portion on the main surface (3) side of the chip (2);
a trench gate structure (20) formed on said main surface (3);
a trench source structure (25, 30) formed in said main surface (3);
An insulating film (16) selectively formed on the main surface (3);
an interlayer insulating film (99) disposed on the main surface (3) so as to cover the insulating film (16);
a gate electrode (100) disposed on the interlayer insulating film (99) and applying a gate potential to the trench gate structure (20);
a source electrode (120) disposed on the interlayer insulating film (99) and applying a source potential to the trench source structure (25, 30);
a gate connection conductive film (50a, 39b) formed on the insulating film (16) and electrically connected to the gate electrode (100);
a contact region (38, 92) of a second conductivity type selectively formed in a surface layer portion of the first region and electrically connected to the source electrode (120);
If the region of the contact region (38, 92) to which the source electrode (120) is joined is defined as a source/contact junction region (38A, 92A, 92B),
The semiconductor device has a maximum distance between each position on the lower surface of the gate connection conductive film (50a, 39b) and the source/contact junction region (38A, 92A, 92B) closest thereto of 90 μm or less.
　［Ａ２］　前記ゲート接続導電膜（５０ａ，３９ｂ）の下面の各位置とそれに最も近い前記ソース／コンタクト接合領域（３８Ａ，９２Ａ，９２Ｂ）の距離の最大値が８０μｍ以下である、Ａ１に記載の半導体装置。 [A2] The semiconductor device described in A1, in which the maximum distance between each position on the underside of the gate connection conductive film (50a, 39b) and the source/contact junction region (38A, 92A, 92B) closest thereto is 80 μm or less.
　［Ａ３］　前記ゲート接続導電膜（５０ａ，３９ｂ）の下面の各位置とそれに最も近い前記ソース／コンタクト接合領域（３８Ａ，９２Ａ，９２Ｂ）の距離の最大値が７０μｍ以下である、Ａ１に記載の半導体装置。 [A3] The semiconductor device described in A1, in which the maximum distance between each position on the underside of the gate connection conductive film (50a, 39b) and the source/contact junction region (38A, 92A, 92B) closest thereto is 70 μm or less.
　［Ａ４］　前記主面（３）に形成されたトレンチ抵抗構造（４１）を含むゲート抵抗（４０）を含み、
　前記ゲート電極（１００）は、前記トレンチ抵抗構造（４１）よりも低い抵抗値を有し、前記トレンチ抵抗構造（４１）に電気的に接続されたゲートパッド（１０１）と、前記トレンチ抵抗構造（４１）よりも低い抵抗値を有し、前記トレンチ抵抗構造（４１）を介して前記ゲートパッド（１０１）に電気的に接続されるゲート配線（１０２）とを含み、
　前記ゲート抵抗（４０）が前記ゲート接続導電膜（５０ａ）を含む、Ａ１～Ａ３のいずれかに記載の半導体装置。 [A4] A gate resistor (40) including a trench resistor structure (41) formed on the main surface (3),
the gate electrode (100) has a resistance value lower than that of the trench resistance structure (41) and includes a gate pad (101) electrically connected to the trench resistance structure (41), and a gate wiring (102) has a resistance value lower than that of the trench resistance structure (41) and is electrically connected to the gate pad (101) via the trench resistance structure (41);
The semiconductor device according to any one of A1 to A3, wherein the gate resistor (40) includes the gate connection conductive film (50a).
　［Ａ５］　前記主面（３）の内方部に設けられた活性領域（１２）と、
　前記主面（３）の周縁部に設けられた外周領域（１３）と、
　前記活性領域（１２）および前記外周領域（１３）の間に設けられた終端領域（１５）とを含み、
　前記トレンチ抵抗構造（４１）は、前記終端領域（１５）において前記主面（３）に形成され、
　前記ゲートパッド（１０１）は、前記終端領域（１５）において前記トレンチ抵抗構造（４１）に電気的に接続され、
　前記ゲート配線（１０２）は、前記終端領域（１５）において前記トレンチ抵抗構造（４１）を介して前記ゲートパッド（１０１）に電気的に接続されている、Ａ４に記載の半導体装置。 [A5] an active region (12) provided in an inner portion of the main surface (3);
An outer peripheral region (13) provided on the peripheral edge of the main surface (3);
a termination region (15) provided between the active region (12) and the peripheral region (13);
the trench resistor structure (41) is formed in the main surface (3) in the termination region (15);
the gate pad (101) is electrically connected to the trench resistor structure (41) in the termination region (15);
The semiconductor device according to A4, wherein the gate wiring (102) is electrically connected to the gate pad (101) via the trench resistor structure (41) in the termination region (15).
　［Ａ６］　前記ゲート抵抗（４０）は、前記終端領域（１５）に配置されており、
　前記ソース電極（１２０）は、前記ゲート抵抗（４０）に対して前記活性領域（１２）とは反対側の領域において、前記トレンチ抵抗構造（４１）に沿って延びた第１ソース配線（１２５）を含み、
　前記ゲート抵抗（４０）に含まれている前記ゲート接続導電膜（５０）の下面の各位置のうち、全ての前記ソース／コンタクト接合領域（３８Ａ，９２Ａ，９２Ｂ）それぞれからその位置までの距離の最小値が最大となる位置を第１位置（Ｐ１）とすると、前記第１ソース配線（１２５）が接合される前記ソース／コンタクト接合領域（９２Ａ）は、前記全ての前記ソース／コンタクト接合領域（３８Ａ，９２Ａ，９２Ｂ）のうち前記第１位置（Ｐ１）までの距離が最も小さくなる前記ソース／コンタクト接合領域（９２Ａ）を含む、Ａ５に記載の半導体装置。 [A6] The gate resistor (40) is disposed in the termination region (15);
The source electrode (120) includes a first source wiring (125) extending along the trench resistor structure (41) in a region opposite the active region (12) with respect to the gate resistor (40);
The semiconductor device according to A5, wherein, among the respective positions on the underside of the gate connection conductive film (50) included in the gate resistor (40), a position at which the minimum value of the distance from each of all of the source/contact junction regions (38A, 92A, 92B) to the position is the largest is defined as a first position (P1), and the source/contact junction region (92A) to which the first source wiring (125) is joined includes the source/contact junction region (92A) at which the distance to the first position (P1) is the smallest among all of the source/contact junction regions (38A, 92A, 92B).
　［Ａ７］　前記コンタクト領域（３８，９２）は、前記第１ソース配線（１２５）が電気的に接続される第１アウターコンタクト領域（９２）を含み、
　前記第１ソース配線（１２５）が接合される前記ソース／コンタクト接合領域（９２Ａ）は、前記第１アウターコンタクト領域（９２）のうち、前記第１ソース配線（１２５）が接合されている領域である、Ａ６に記載の半導体装置。 [A7] The contact region (38, 92) includes a first outer contact region (92) to which the first source wiring (125) is electrically connected,
The semiconductor device according to A6, wherein the source/contact junction region (92A) to which the first source wiring (125) is joined is a region of the first outer contact region (92) to which the first source wiring (125) is joined.
　［Ａ８］　前記トレンチゲート構造（２０）が、前記主面（３）に形成されたゲートトレンチ（２１）と、前記ゲートトレンチ（２１）の壁面に形成され、前記絶縁膜（１６）に接続されたゲート絶縁膜（２２）と、前記ゲート絶縁膜（２２）を挟んで前記ゲートトレンチ（２１）に埋設されたゲート埋設電極（２３）とを含み、
　前記ゲート埋設電極（２３）上には、選択的に前記ゲート埋設電極（２３）および前記絶縁膜（１６）を被覆する複数のゲート接続電極膜（３９）が形成されており、
　前記ゲート接続電極膜（３９）が前記ゲート接続導電膜（３９ｂ）を含む、Ａ１～Ａ７のいずれかに記載の半導体装置。 [A8] The trench gate structure (20) includes a gate trench (21) formed in the main surface (3), a gate insulating film (22) formed on a wall surface of the gate trench (21) and connected to the insulating film (16), and a gate buried electrode (23) buried in the gate trench (21) with the gate insulating film (22) sandwiched therebetween,
A plurality of gate connection electrode films (39) are formed on the gate buried electrode (23) to selectively cover the gate buried electrode (23) and the insulating film (16),
The semiconductor device according to any one of A1 to A7, wherein the gate connection electrode film (39) includes the gate connection conductive film (39b).
　［Ａ９］　前記主面（３）の内方部に設けられた活性領域（１２）と、
　前記主面（３）の周縁部に設けられた外周領域（１３）と、
　前記活性領域（１２）および前記外周領域（１３）の間に設けられた両側の周縁領域（１４）とを含み、
　前記トレンチゲート構造（２０）は、前記活性領域（１２）において前記主面（３）に形成され、
　前記ゲート電極（１００）は、前記活性領域（１２）において前記トレンチゲート構造（２０）に電気的に接続されている、Ａ８に記載の半導体装置。 [A9] an active region (12) provided in an inner portion of the main surface (3);
An outer peripheral region (13) provided on the peripheral edge of the main surface (3);
and a peripheral region (14) on both sides provided between the active region (12) and the outer periphery region (13),
The trench gate structure (20) is formed on the main surface (3) in the active region (12);
The semiconductor device according to A8, wherein the gate electrode (100) is electrically connected to the trench gate structure (20) in the active region (12).
　［Ａ１０］　前記ゲート電極（１００）は、前記活性領域（１２）において、前記両側の周縁領域（１４）のうちの少なくとも一方の周縁領域（１４）に沿って延びた周縁ゲート配線（１０２Ａ，１０２Ｂ）を含み、
　前記トレンチゲート構造（２０）の周縁ゲート配線（１０２Ａ，１０２Ｂ）側の端部に、前記ゲート埋設電極（２３）および前記絶縁膜（１６）を被覆しかつ前記周縁ゲート配線（１０２Ａ，１０２Ｂ）に接合される前記ゲート接続電極膜（３９）が形成されており、
　前記ソース電極（１２０）は、前記周縁ゲート配線（１０２Ａ，１０２Ｂ）に対して前記活性領域（１２）とは反対側の領域において、前記周縁ゲート配線（１０２Ａ，１０２Ｂ）に沿って延びた第２ソース配線（１２５）を含み、
　前記周縁ゲート配線（１０２Ａ，１０２Ｂ）に接合される前記ゲート接続電極膜（３９）に含まれる前記ゲート接続導電膜（３９ｂ）の下面の各位置のうち、全ての前記ソース／コンタクト接合領域（３８Ａ，９２Ａ，９２Ｂ）それぞれからその位置までの距離の最小値が最大となる位置を第２位置（Ｐ２）とすると、前記第２ソース配線（１２５）が接合される前記ソース／コンタクト接合領域（９２Ｂ）は、前記全ての前記ソース／コンタクト接合領域（３８Ａ，９２Ａ，９２Ｂ）のうち前記第２位置（Ｐ２）までの距離が最も小さくなる前記ソース／コンタクト接合領域（９２Ｂ）を含む、Ａ９に記載の半導体装置。 [A10] The gate electrode (100) includes peripheral gate wiring (102A, 102B) extending along at least one of the peripheral regions (14) on both sides in the active region (12),
the gate connection electrode film (39) is formed at an end of the trench gate structure (20) on the peripheral gate wiring (102A, 102B) side, the gate connection electrode film (39) covering the gate buried electrode (23) and the insulating film (16) and being joined to the peripheral gate wiring (102A, 102B);
The source electrode (120) includes a second source wiring (125) extending along the peripheral gate wiring (102A, 102B) in a region opposite to the active region (12) with respect to the peripheral gate wiring (102A, 102B);
The semiconductor device according to A9, wherein, among each position on the underside of the gate connection conductive film (39b) included in the gate connection electrode film (39) joined to the peripheral gate wiring (102A, 102B), a position at which the minimum value of the distance from each of all of the source/contact junction regions (38A, 92A, 92B) to the position is the largest is defined as a second position (P2), and the source/contact junction region (92B) to which the second source wiring (125) is joined includes the source/contact junction region (92B) at which the distance to the second position (P2) is the smallest among all of the source/contact junction regions (38A, 92A, 92B).
　［Ａ１１］　前記コンタクト領域（３８，９２）は、前記第２ソース配線（１２５）が電気的に接続される第２アウターコンタクト領域（９２）を含み、
　前記第２ソース配線（１２５）が接合される前記ソース／コンタクト接合領域（９２Ｂ）は、前記第２アウターコンタクト領域（９２）のうち、前記第２ソース配線（１２５）が接合されている領域である、Ａ１０に記載の半導体装置。 [A11] The contact region (38, 92) includes a second outer contact region (92) to which the second source wiring (125) is electrically connected,
The semiconductor device according to A10, wherein the source/contact junction region (92B) to which the second source wiring (125) is joined is a region of the second outer contact region (92) to which the second source wiring (125) is joined.
　［Ａ１２］
　前記ゲート電極（１００）は、前記活性領域（１２）における前記両側の周縁領域（１４）の間の中央領域に形成され、前記周縁領域（１４）に沿って延びた中央ゲート配線（１０２Ｃ）を含み、
　前記トレンチゲート構造（２０）における前記中央ゲート配線（１０２Ｃ）に対向する部分に、前記ゲート埋設電極（２３）および前記絶縁膜（１６）を被覆しかつ前記中央ゲート配線（１０２Ｃ）に接合される前記ゲート接続電極膜（３９）が形成されており、
　前記ソース電極（１２０）は、前記活性領域（１２）において、前記中央ゲート配線（１０２Ｃ）の両側に前記中央ゲート配線（１０２Ｃ）から間隔を空けて配置された２つのソースパッド部（１２１，１２２）を含み、
　前記中央ゲート配線（１０２Ｃ）に接合される前記ゲート接続電極膜（３９）に含まれる前記ゲート接続導電膜（３９ｂ）の下面の各位置のうち、全ての前記ソース／コンタクト接合領域（３８Ａ，９２Ａ，９２Ｂ）それぞれからその位置までの距離の最小値が最大となる位置を第３位置（Ｐ３）とすると、前記２つのソースパッド部（１２１，１２２）の少なくとも一方が接合される前記ソース／コンタクト接合領域（３８Ａ）は、前記全ての前記ソース／コンタクト接合領域（３８Ａ，９２Ａ，９２Ｂ）のうち前記第３位置（Ｐ３）までの距離が最も小さくなる前記ソース／コンタクト接合領域（３８Ａ）を含む、Ａ９に記載の半導体装置。 [A12]
The gate electrode (100) is formed in a central region between the peripheral regions (14) on both sides of the active region (12) and includes a central gate wiring (102C) extending along the peripheral regions (14);
the gate connection electrode film (39) is formed in a portion of the trench gate structure (20) facing the central gate wiring (102C), the gate connection electrode film (39) covering the gate buried electrode (23) and the insulating film (16) and being joined to the central gate wiring (102C);
The source electrode (120) includes two source pad portions (121, 122) disposed on both sides of the central gate wiring (102C) at a distance from the central gate wiring (102C) in the active region (12);
The semiconductor device according to A9, wherein, among each position on the underside of the gate connection conductive film (39b) included in the gate connection electrode film (39) joined to the central gate wiring (102C), a position at which the minimum value of the distance from each of all of the source/contact junction regions (38A, 92A, 92B) to the position is the largest is defined as a third position (P3), and the source/contact junction region (38A) to which at least one of the two source pad portions (121, 122) is joined includes the source/contact junction region (38A) at which the distance to the third position (P3) is the smallest among all of the source/contact junction regions (38A, 92A, 92B).
　［Ａ１３］　前記コンタクト領域（３８，９２）が、活性領域（１２）において前記トレンチソース構造（２５，３０）に沿う領域に形成された第１コンタクト領域（３８）を含み、
　前記ソースパッド部（１２１，１２２）が接合される前記ソース／コンタクト接合領域（３８Ａ）は、前記第１コンタクト領域（３８）のうち前記ソースパッド部（１２１，１２２）が接合されている領域である、Ａ１２に記載の半導体装置。 [A13] The contact region (38, 92) includes a first contact region (38) formed in a region along the trench source structure (25, 30) in the active region (12);
The semiconductor device according to A12, wherein the source/contact junction region (38A) to which the source pad portion (121, 122) is joined is a region of the first contact region (38) to which the source pad portion (121, 122) is joined.
　［Ａ１４］　前記主面（３）の内方部に形成された第１面部（８）、前記第１面部（８）から前記チップ（２）の厚さ方向に窪むように前記主面（３）の周縁部に形成された第２面部（９）、ならびに、前記第１面部（８）および前記第２面部（９）を接続する接続面部（１０Ａ～１０Ｄ）によって前記主面（３）に区画された活性台地（１１）をさらに含み、
　前記活性領域（１２）は、前記第１面部（８）に設けられ、
　前記外周領域（１３）は、前記第２面部（９）に設けられ、
　前記終端領域（１５）は、前記第１面部（８）に設けられている、Ａ５～Ａ７のいずれかに記載の半導体装置。 [A14] The semiconductor device further includes a first surface portion (8) formed on the inner side of the main surface (3), a second surface portion (9) formed on the periphery of the main surface (3) so as to be recessed from the first surface portion (8) in the thickness direction of the chip (2), and an active plateau (11) defined on the main surface (3) by a connecting surface portion (10A-10D) connecting the first surface portion (8) and the second surface portion (9),
The active region (12) is provided on the first surface portion (8),
The outer circumferential region (13) is provided on the second surface portion (9),
The semiconductor device according to any one of A5 to A7, wherein the termination region (15) is provided on the first surface portion (8).
　［Ａ１５］　前記主面（３）の内方部に形成された第１面部（８）、前記第１面部（８）から前記チップ（２）の厚さ方向に窪むように前記主面（３）の周縁部に形成された第２面部（９）、ならびに、前記第１面部（８）および前記第２面部（９）を接続する接続面部（１０Ａ～１０Ｄ）によって前記主面（３）に区画された活性台地（１１）をさらに含み、
　前記活性領域（１２）は、前記第１面部（８）に設けられ、
　前記外周領域（１３）は、前記第２面部（９）に設けられ、
　前記両側の周縁領域（１４）は、前記第１面部（８）に設けられている、Ａ９～Ａ１３のいずれかに記載の半導体装置。 [A15] The semiconductor device further includes a first surface portion (8) formed on the inner side of the main surface (3), a second surface portion (9) formed on the periphery of the main surface (3) so as to be recessed from the first surface portion (8) in the thickness direction of the chip (2), and an active plateau (11) defined on the main surface (3) by a connecting surface portion (10A-10D) connecting the first surface portion (8) and the second surface portion (9),
The active region (12) is provided on the first surface portion (8),
The outer circumferential region (13) is provided on the second surface portion (9),
The semiconductor device according to any one of A9 to A13, wherein the peripheral regions (14) on both sides are provided on the first surface portion (8).
　［Ａ１６］　前記トレンチ抵抗構造（４１）よりも低い抵抗値を有し、前記トレンチ抵抗構造（４１）を介して前記ゲートパッド（１０１）に電気的に接続されるように前記主面（３）の上に配置されたゲートサブパッド（１０３）をさらに含む、Ａ４～Ａ７のいずれかに記載の半導体装置。 [A16] The semiconductor device according to any one of A4 to A7, further including a gate subpad (103) arranged on the main surface (3) so as to have a resistance value lower than the trench resistor structure (41) and to be electrically connected to the gate pad (101) via the trench resistor structure (41).
　［Ａ１７］　前記ゲートサブパッド（１０３）は、前記ゲートパッド（１０１）よりも幅狭に形成され、前記ゲート配線（１０２）よりも幅広に形成されている、Ａ１６に記載の半導体装置。 [A17] The semiconductor device described in A16, in which the gate subpad (103) is formed narrower than the gate pad (101) and wider than the gate wiring (102).
　以上、実施形態について詳細に説明してきたが、これらは技術的内容を明らかにするために用いられた具体例に過ぎず、本発明はこれらの具体例に限定して解釈されるべきではなく、本発明の範囲は添付の請求の範囲によって限定される。 The above describes the embodiments in detail, but these are merely specific examples used to clarify the technical content, and the present invention should not be interpreted as being limited to these specific examples, and the scope of the present invention is limited by the appended claims.
　この出願は、２０２２年９月２９日に日本国特許庁に提出された特願２０２２－１５７１６３号に対応しており、それらの出願の全開示はここに引用により組み込まれるものとする。 This application corresponds to Patent Application No. 2022-157163 filed with the Japan Patent Office on September 29, 2022, the entire disclosures of which are incorporated herein by reference.
１　　　半導体装置
２　　　チップ
３　　　第１主面
４　　　第２主面
５Ａ～５Ｄ　第１～第４側面
６　　　第１半導体領域
８　　　活性面（第１面部）
９　　　外周面（第２面部）
１０Ａ　第１接続面（接続面部）
１０Ｂ　第２接続面（接続面部）
１０Ｃ　第３接続面（接続面部）
１０Ｄ　第４接続面（接続面部）
１１　　活性台地
１２　　活性領域
１３　　外周領域
１４　　周縁領域
１４Ａ　第１周縁領域
１４Ｂ　第２周縁領域
１５　　終端領域
１５Ａ　第１終端領域
１５Ｂ　第２終端領域
１６　　主面絶縁膜
１７　　ボディ領域
１８　　ソース領域
２０　　トレンチゲート構造
２１　　ゲートトレンチ
２２　　ゲート絶縁膜
２３　　ゲート埋設電極
２５　　第１トレンチソース構造
２６　　第１ソーストレンチ
２７　　第１ソース絶縁膜
２８　　第１ソース埋設電極
３０　　第２トレンチソース構造
３１　　第２ソーストレンチ
３２　　第２ソース絶縁膜
３３　　第２ソース埋設電極
３５　　第１ウェル領域（トレンチゲート構造）
３６　　第２ウェル領域（第１トレンチソース構造）
３７　　第３ウェル領域（第２トレンチソース構造）
３８　　第１コンタクト領域（ｐ＋型）
３８Ａ　ソース／コンタクト接合領域
３９　　ゲート接続電極膜
３９ａ　電極面
３９ｂ　ゲート接続導電膜
４０　　ゲート抵抗
４１　　トレンチ抵抗構造
４２　　第１トレンチ抵抗構造（第１溝構造）
４３　　第２トレンチ抵抗構造（第３溝構造）
４４　　第１トレンチ
４５　　第１絶縁膜
４６　　第１埋設電極
４７　　第２トレンチ
４８　　第２絶縁膜
４９　　第２埋設電極
５０　　抵抗膜
５０ａ　ゲート接続導電膜
５５　　ダミー構造
５６　　第１ダミー構造
５７　　第２ダミー構造
６０　　ダミートレンチ構造
６１　　第１ダミートレンチ構造（第２溝構造）
６２　　第２ダミートレンチ構造（第４溝構造）
６３　　第１ダミートレンチ
６４　　第１ダミー絶縁膜
６５　　第１ダミー埋設電極
６６　　第２ダミートレンチ
６７　　第２ダミー絶縁膜
６８　　第２ダミー埋設電極
７０　　メインメサ部
７１　　第１メサ部
７２　　第２メサ部
７５　　第４ウェル領域
７６　　第５ウェル領域
７７　　第６ウェル領域
７８　　第７ウェル領域
７９　　第２コンタクト領域
８０　　第３コンタクト領域
８５　　終端ダミー構造
８６　　トレンチ終端構造
８７　　終端トレンチ
８８　　終端絶縁膜
８９　　終端埋設電極
９０　　第８ウェル領域
９１　　アウターウェル領域（ｐ型）
９２　　アウターコンタクト領域（ｐ型）
９２Ａ，９２Ｂ　ソース／コンタクト接合領域
９３　　フィールド領域（ｐ型）
９５　　サイドウォール配線
９９　　層間絶縁膜
１００　ゲート電極
１０１　ゲートパッド
１０２　ゲート配線
１０２Ａ　第１ゲート配線
１０２Ｂ　第２ゲート配線
１０２Ｃ　第３ゲート配線
１０３　ゲートサブパッド
１０４　パッド本体部
１０５　引き出し部
１０６　第１抵抗開口
１０７　第２抵抗開口
１０８　ゲート開口
１０９　第３抵抗開口
１１０　ライン部
１１１　第１分岐部
１１２　第２分岐部
１２０　ソース電極
１２１　第１ソースパッド
１２２　第２ソースパッド
１２３　第１ソースサブパッド
１２４　第２ソースサブパッド
１２５　ソース配線
１２６　ソース開口
１２７　アウター開口
１３０　アッパー絶縁膜
１３１　ゲートパッド開口
１３２　ゲートサブパッド開口
１３３　第１ソースパッド開口
１３４　第１ソースサブパッド開口
１３５　第２ソースパッド開口
１３６　第２ソースサブパッド開口
１３７　　ダイシングストリート
１４０　無機絶縁膜
１４１　有機絶縁膜
１５０　ドレイン電極
Ｘ　　　第１方向
Ｙ　　　第２方向 1 Semiconductor device 2 Chip 3 First main surface 4 Second main surfaces 5A to 5D First to fourth side surfaces 6 First semiconductor region 8 Active surface (first surface portion)
9 Outer circumferential surface (second surface)
10A First Connection Surface (Connection Surface Portion)
10B Second connection surface (connection surface portion)
10C third connection surface (connection surface portion)
10D Fourth connection surface (connection surface portion)
11 Active plateau 12 Active region 13 Outer peripheral region 14 Peripheral region 14A First peripheral region 14B Second peripheral region 15 Termination region 15A First termination region 15B Second termination region 16 Main surface insulating film 17 Body region 18 Source region 20 Trench gate structure 21 Gate trench 22 Gate insulating film 23 Gate buried electrode 25 First trench source structure 26 First source trench 27 First source insulating film 28 First source buried electrode 30 Second trench source structure 31 Second source trench 32 Second source insulating film 33 Second source buried electrode 35 First well region (trench gate structure)
36 Second well region (first trench source structure)
37 Third well region (second trench source structure)
38 First contact region (p + type)
38A: source/contact junction region 39: gate connection electrode film 39a: electrode surface 39b: gate connection conductive film 40: gate resistor 41: trench resistor structure 42: first trench resistor structure (first groove structure)
43 Second trench resistor structure (third trench structure)
44 First trench 45 First insulating film 46 First buried electrode 47 Second trench 48 Second insulating film 49 Second buried electrode 50 Resistance film 50a Gate connection conductive film 55 Dummy structure 56 First dummy structure 57 Second dummy structure 60 Dummy trench structure 61 First dummy trench structure (second groove structure)
62 Second dummy trench structure (fourth trench structure)
63 First dummy trench 64 First dummy insulating film 65 First dummy buried electrode 66 Second dummy trench 67 Second dummy insulating film 68 Second dummy buried electrode 70 Main mesa portion 71 First mesa portion 72 Second mesa portion 75 Fourth well region 76 Fifth well region 77 Sixth well region 78 Seventh well region 79 Second contact region 80 Third contact region 85 Termination dummy structure 86 Trench termination structure 87 Termination trench 88 Termination insulating film 89 Termination buried electrode 90 Eighth well region 91 Outer well region (p-type)
92 Outer contact region (p-type)
92A, 92B Source/contact junction region 93 Field region (p-type)
95 Sidewall wiring 99 Interlayer insulating film 100 Gate electrode 101 Gate pad 102 Gate wiring 102A First gate wiring 102B Second gate wiring 102C Third gate wiring 103 Gate subpad 104 Pad main body 105 Lead-out portion 106 First resistor opening 107 Second resistor opening 108 Gate opening 109 Third resistor opening 110 Line portion 111 First branch portion 112 Second branch portion 120 Source electrode 121 First source pad 122 Second source pad 123 First source subpad 124 Second source subpad 125 Source wiring 126 Source opening 127 Outer opening 130 Upper insulating film 131 Gate pad opening 132 Gate subpad opening 133 First source pad opening 134 First source subpad opening 135 Second source pad opening 136 Second source subpad opening 137 Dicing street 140 Inorganic insulating film 141 Organic insulating film 150 Drain electrode X First direction Y Second direction

Claims (17)

  1. 　主面を有し、第１導電型の半導体からなるチップと、
    　前記チップの前記主面側の表層部に選択的に形成された第２導電型の第１領域と、
    　前記主面に形成されたトレンチゲート構造と、
    　前記主面に形成されたトレンチソース構造と、
    　前記主面上に選択的に形成された絶縁膜と、
    　前記主面上に前記絶縁膜を覆うように配置された層間絶縁膜と、
    　前記層間絶縁膜上に配置され、前記トレンチゲート構造にゲート電位を付与するゲート電極と、
    　前記層間絶縁膜上に配置され、前記トレンチソース構造にソース電位を付与するソース電極と、
    　前記絶縁膜上に形成され、前記ゲート電極に電気的に接続されたゲート接続導電膜と、
    　前記第１領域の表層部に選択的に形成され、前記ソース電極が電気的に接続される第２導電型のコンタクト領域とを含み、
    　前記コンタクト領域のうち前記ソース電極が接合されている領域をソース／コンタクト接合領域とすると、
    　前記ゲート接続導電膜の下面の各位置とそれに最も近い前記ソース／コンタクト接合領域の距離の最大値が９０μｍ以下である、半導体装置。     A chip having a main surface and made of a first conductivity type semiconductor;
    a first region of a second conductivity type selectively formed in a surface layer portion on the main surface side of the chip;
    a trench gate structure formed on the main surface;
    a trench source structure formed in the major surface;
    an insulating film selectively formed on the main surface;
    an interlayer insulating film disposed on the main surface so as to cover the insulating film;
    a gate electrode disposed on the interlayer insulating film and configured to apply a gate potential to the trench gate structure;
    a source electrode disposed on the interlayer insulating film and configured to apply a source potential to the trench source structure;
    a gate connection conductive film formed on the insulating film and electrically connected to the gate electrode;
    a contact region of a second conductivity type selectively formed in a surface layer portion of the first region and electrically connected to the source electrode;
    If a region of the contact region to which the source electrode is joined is defined as a source/contact junction region,
    The semiconductor device has a maximum distance between each position on the lower surface of the gate connecting conductive film and the source/contact junction region closest thereto of 90 μm or less.
  2. 　前記ゲート接続導電膜の下面の各位置とそれに最も近い前記ソース／コンタクト接合領域の距離の最大値が８０μｍ以下である、請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the maximum distance between each position on the underside of the gate connection conductive film and the source/contact junction region closest thereto is 80 μm or less.
  3. 　前記ゲート接続導電膜の下面の各位置とそれに最も近い前記ソース／コンタクト接合領域の距離の最大値が７０μｍ以下である、請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the maximum distance between each position on the underside of the gate connection conductive film and the source/contact junction region closest thereto is 70 μm or less.
  4. 　前記主面に形成されたトレンチ抵抗構造を含むゲート抵抗を含み、
    　前記ゲート電極は、前記トレンチ抵抗構造よりも低い抵抗値を有し、前記トレンチ抵抗構造に電気的に接続されたゲートパッドと、前記トレンチ抵抗構造よりも低い抵抗値を有し、前記トレンチ抵抗構造を介して前記ゲートパッドに電気的に接続されるゲート配線とを含み、
    　前記ゲート抵抗が前記ゲート接続導電膜を含む、請求項１～３のいずれか一項に記載の半導体装置。     a gate resistor including a trench resistor structure formed on the major surface;
    the gate electrode includes a gate pad having a resistance value lower than that of the trench resistance structure and electrically connected to the trench resistance structure, and a gate wiring having a resistance value lower than that of the trench resistance structure and electrically connected to the gate pad via the trench resistance structure;
    4. The semiconductor device according to claim 1, wherein the gate resistor includes the gate connection conductive film.
  5. 　前記主面の内方部に設けられた活性領域と、
    　前記主面の周縁部に設けられた外周領域と、
    　前記活性領域および前記外周領域の間に設けられた終端領域とを含み、
    　前記トレンチ抵抗構造は、前記終端領域において前記主面に形成され、
    　前記ゲートパッドは、前記終端領域において前記トレンチ抵抗構造に電気的に接続され、
    　前記ゲート配線は、前記終端領域において前記トレンチ抵抗構造を介して前記ゲートパッドに電気的に接続されている、請求項４に記載の半導体装置。     an active region provided in an inner portion of the main surface;
    an outer peripheral region provided on a peripheral portion of the main surface;
    a termination region disposed between the active region and the periphery region;
    the trench resistor structure is formed in the major surface in the termination region;
    the gate pad is electrically connected to the trench resistor structure in the termination region;
    The semiconductor device according to claim 4 , wherein said gate wiring is electrically connected to said gate pad via said trench resistor structure in said termination region.
  6. 　前記ゲート抵抗は、前記終端領域に配置されており、
    　前記ソース電極は、前記ゲート抵抗に対して前記活性領域とは反対側の領域において、前記トレンチ抵抗構造に沿って延びた第１ソース配線を含み、
    　前記ゲート抵抗に含まれている前記ゲート接続導電膜の下面の各位置のうち、全ての前記ソース／コンタクト接合領域それぞれからその位置までの距離の最小値が最大となる位置を第１位置とすると、前記第１ソース配線が接合される前記ソース／コンタクト接合領域は、前記全ての前記ソース／コンタクト接合領域のうち前記第１位置までの距離が最も小さくなる前記ソース／コンタクト接合領域を含む、請求項５に記載の半導体装置。     the gate resistor is disposed in the termination region;
    the source electrode includes a first source wiring extending along the trench resistor structure in a region opposite to the active region with respect to the gate resistor;
    6. The semiconductor device according to claim 5, wherein, among the positions on the underside of the gate connection conductive film included in the gate resistor, a position at which a minimum value of a distance from each of the source/contact junction regions to the position is maximum is defined as a first position, and the source/contact junction region to which the first source wiring is joined includes the source/contact junction region at which a distance to the first position is smallest among all the source/contact junction regions.
  7. 　前記コンタクト領域は、前記第１ソース配線が電気的に接続される第１アウターコンタクト領域を含み、
    　前記第１ソース配線が接合される前記ソース／コンタクト接合領域は、前記第１アウターコンタクト領域のうち、前記第１ソース配線が接合されている領域である、請求項６に記載の半導体装置。     the contact region includes a first outer contact region to which the first source line is electrically connected;
    7. The semiconductor device according to claim 6, wherein the source/contact junction region to which the first source wiring is joined is a region of the first outer contact region to which the first source wiring is joined.
  8. 　前記トレンチゲート構造が、前記主面に形成されたゲートトレンチと、前記ゲートトレンチの壁面に形成され、前記絶縁膜に接続されたゲート絶縁膜と、前記ゲート絶縁膜を挟んで前記ゲートトレンチに埋設されたゲート埋設電極とを含み、
    　前記ゲート埋設電極上には、選択的に前記ゲート埋設電極および前記絶縁膜を被覆する複数のゲート接続電極膜が形成されており、
    　前記ゲート接続電極膜が前記ゲート接続導電膜を含む、請求項１～３のいずれか一項に記載の半導体装置。     the trench gate structure includes a gate trench formed in the main surface, a gate insulating film formed on a wall surface of the gate trench and connected to the insulating film, and a gate buried electrode buried in the gate trench with the gate insulating film sandwiched therebetween;
    a plurality of gate connection electrode films are formed on the gate buried electrode, the gate connection electrode films selectively covering the gate buried electrode and the insulating film;
    4. The semiconductor device according to claim 1, wherein the gate connection electrode film includes the gate connection conductive film.
  9. 　前記主面の内方部に設けられた活性領域と、
    　前記主面の周縁部に設けられた外周領域と、
    　前記活性領域および前記外周領域の間に設けられた両側の周縁領域とを含み、
    　前記トレンチゲート構造は、前記活性領域において前記主面に形成され、
    　前記ゲート配線は、前記活性領域において前記トレンチゲート構造に電気的に接続されている、請求項８に記載の半導体装置。     an active region provided in an inner portion of the main surface;
    an outer peripheral region provided on a peripheral portion of the main surface;
    and a peripheral region on each side between the active region and the peripheral region,
    the trench gate structure is formed in the major surface in the active region;
    The semiconductor device according to claim 8 , wherein the gate wiring is electrically connected to the trench gate structure in the active region.
  10. 　前記ゲート電極は、前記活性領域において、前記両側の周縁領域のうちの少なくとも一方の周縁領域に沿って延びた周縁ゲート配線を含み、
    　前記トレンチゲート構造の周縁ゲート配線側の端部に、前記ゲート埋設電極および前記絶縁膜を被覆しかつ前記周縁ゲート配線に接合される前記ゲート接続電極膜が形成されており、
    　前記ソース電極は、前記周縁ゲート配線に対して前記活性領域とは反対側の領域において、前記周縁ゲート配線に沿って延びた第２ソース配線を含み、
    　前記周縁ゲート配線に接合される前記ゲート接続電極膜に含まれる前記ゲート接続導電膜の下面の各位置のうち、全ての前記ソース／コンタクト接合領域それぞれからその位置までの距離の最小値が最大となる位置を第２位置とすると、前記第２ソース配線が接合される前記ソース／コンタクト接合領域は、前記全ての前記ソース／コンタクト接合領域のうち前記第２位置までの距離が最も小さくなる前記ソース／コンタクト接合領域を含む、請求項９に記載の半導体装置。     the gate electrode includes a peripheral gate wiring extending along at least one of the peripheral regions on both sides in the active region;
    the gate connection electrode film is formed on an end of the trench gate structure on a peripheral gate wiring side, the gate connection electrode film covering the gate buried electrode and the insulating film and being joined to the peripheral gate wiring;
    the source electrode includes a second source wiring extending along the peripheral gate wiring in a region opposite to the active region with respect to the peripheral gate wiring;
    10. The semiconductor device according to claim 9, wherein, among each position on the underside of the gate connection conductive film included in the gate connection electrode film joined to the peripheral gate wiring, a position at which a minimum value of a distance from each of the source/contact junction regions to the position is maximum is defined as a second position, and the source/contact junction region to which the second source wiring is joined includes the source/contact junction region at which a distance to the second position is smallest among all the source/contact junction regions.
  11. 　前記コンタクト領域は、前記第２ソース配線が電気的に接続される第２アウターコンタクト領域を含み、
    　前記第２ソース配線が接合される前記ソース／コンタクト接合領域は、前記第２アウターコンタクト領域のうち、前記第２ソース配線が接合されている領域である、請求項１０に記載の半導体装置。     the contact region includes a second outer contact region to which the second source line is electrically connected;
    11. The semiconductor device according to claim 10, wherein the source/contact junction region to which the second source wiring is joined is a region of the second outer contact region to which the second source wiring is joined.
  12. 　前記ゲート電極は、前記活性領域における前記両側の周縁領域の間の中央領域に形成され、前記周縁領域に沿って延びた中央ゲート配線を含み、
    　前記トレンチゲート構造における前記中央ゲート配線に対向する部分に、前記ゲート埋設電極および前記絶縁膜を被覆しかつ前記中央ゲート配線に接合される前記ゲート接続電極膜が形成されており、
    　前記ソース電極は、前記活性領域において、前記中央ゲート配線の両側に前記中央ゲート配線から間隔を空けて配置された２つのソースパッド部を含み、
    　前記中央ゲート配線に接合される前記ゲート接続電極膜に含まれる前記ゲート接続導電膜の下面の各位置のうち、全ての前記ソース／コンタクト接合領域それぞれからその位置までの距離の最小値が最大となる位置を第３位置とすると、前記２つのソースパッド部の少なくとも一方が接合される前記ソース／コンタクト接合領域は、前記全ての前記ソース／コンタクト接合領域のうち前記第３位置までの距離が最も小さくなる前記ソース／コンタクト接合領域を含む、請求項９に記載の半導体装置。     the gate electrode is formed in a central region between the two peripheral regions in the active region and includes a central gate wiring extending along the peripheral regions;
    the gate connection electrode film is formed in a portion of the trench gate structure facing the central gate wiring, the gate connection electrode film covering the gate buried electrode and the insulating film and being joined to the central gate wiring;
    the source electrode includes two source pad portions disposed on both sides of the central gate wiring at a distance from the central gate wiring in the active region;
    10. The semiconductor device according to claim 9, wherein, among each position on the underside of the gate connection conductive film included in the gate connection electrode film joined to the central gate wiring, a position at which the minimum value of the distance from each of all the source/contact junction regions to the position is the largest is defined as a third position, and the source/contact junction region to which at least one of the two source pad portions is joined includes the source/contact junction region at which the distance to the third position is the smallest among all the source/contact junction regions.
  13. 　前記コンタクト領域が、活性領域において前記トレンチソース構造に沿う領域に形成された第１コンタクト領域を含み、
    　前記ソースパッド部が接合される前記ソース／コンタクト接合領域は、前記第１コンタクト領域のうち前記ソースパッド部が接合されている領域である、請求項１２に記載の半導体装置。     the contact region includes a first contact region formed in an active region along the trench source structure;
    13. The semiconductor device according to claim 12, wherein the source/contact junction region to which the source pad portion is joined is a region of the first contact region to which the source pad portion is joined.
  14. 　前記主面の内方部に形成された第１面部、前記第１面部から前記チップの厚さ方向に窪むように前記主面の周縁部に形成された第２面部、ならびに、前記第１面部および前記第２面部を接続する接続面部によって前記主面に区画された活性台地をさらに含み、
    　前記活性領域は、前記第１面部に設けられ、
    　前記外周領域は、前記第２面部に設けられ、
    　前記終端領域は、前記第１面部に設けられている、請求項５に記載の半導体装置。     the first surface portion is formed on an inner portion of the main surface, a second surface portion is formed on a peripheral portion of the main surface so as to be recessed from the first surface portion in a thickness direction of the chip, and an active plateau is defined on the main surface by a connecting surface portion connecting the first surface portion and the second surface portion,
    The active region is provided on the first surface portion,
    The outer circumferential region is provided on the second surface portion,
    The semiconductor device according to claim 5 , wherein said termination region is provided on said first surface portion.
  15. 　前記主面の内方部に形成された第１面部、前記第１面部から前記チップの厚さ方向に窪むように前記主面の周縁部に形成された第２面部、ならびに、前記第１面部および前記第２面部を接続する接続面部によって前記主面に区画された活性台地をさらに含み、
    　前記活性領域は、前記第１面部に設けられ、
    　前記外周領域は、前記第２面部に設けられ、
    　前記両側の周縁領域は、前記第１面部に設けられている、請求項９に記載の半導体装置。     the first surface portion is formed on an inner portion of the main surface, a second surface portion is formed on a peripheral portion of the main surface so as to be recessed from the first surface portion in a thickness direction of the chip, and an active plateau is defined on the main surface by a connecting surface portion connecting the first surface portion and the second surface portion,
    The active region is provided on the first surface portion,
    The outer circumferential region is provided on the second surface portion,
    The semiconductor device according to claim 9 , wherein said peripheral regions on both sides are provided on said first surface portion.
  16. 　前記トレンチ抵抗構造よりも低い抵抗値を有し、前記トレンチ抵抗構造を介して前記ゲートパッドに電気的に接続されるように前記主面の上に配置されたゲートサブパッドをさらに含む、請求項４に記載の半導体装置。 The semiconductor device according to claim 4, further comprising a gate subpad arranged on the main surface so as to have a resistance value lower than that of the trench resistor structure and to be electrically connected to the gate pad via the trench resistor structure.
  17. 　前記ゲートサブパッドは、前記ゲートパッドよりも幅狭に形成され、前記ゲート配線よりも幅広に形成されている、請求項１６に記載の半導体装置。 The semiconductor device according to claim 16, wherein the gate subpad is narrower than the gate pad and wider than the gate wiring.
PCT/JP2023/027048 2022-09-29 2023-07-24 Semiconductor device WO2024070164A1 (en)

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