JP3505461B2 - Insulated gate semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate type semiconductor device, and more particularly to an insulated gate type semiconductor device provided with a protective resistor for protection against electrostatic breakdown.

[0002]

2. Description of the Related Art With the popularization of portable terminals, small-sized and large-capacity lithium-ion batteries have been required. The protection circuit for battery management of charge and discharge of the lithium ion battery must be smaller and sufficiently resistant to load short circuit due to the need for weight reduction of the mobile terminal. Such a protection circuit is required to be miniaturized because it is built in the container of the lithium-ion battery, and a COB (Chip on Boar) that uses many chip parts
d) Technology has been used to meet the demand for miniaturization. However, on the other hand, the power MOS is connected in series with the lithium ion battery.
Since FETs are connected, there is a need to make the on-resistance of this power MOSFET extremely small, and this is an essential element in a mobile phone in order to lengthen the call time and standby time.

Particularly in the protection circuit, a lithium ion battery L
Two N-channel power MOSFE in series with iB
Since T is connected, the low on-resistance (R _{DS (on)} ) of these two power MOSFETs is the most required item. For this reason, in the manufacture of chips, development has been advanced to increase the cell density by fine processing.

Specifically, the cell density was 7.4 million cells / square inch in the planar structure in which the channels were formed on the surface of the semiconductor substrate, but in the first generation of the trench structure in which the channels were formed on the side surface of the trench, the cells were formed. Density is 25
Significantly improved to, 000,000 pieces / square inch. Furthermore, in the second generation of the trench structure, the cell density could be improved to 72 million cells / square inch. However, there is a limit to miniaturization, and the limit has become apparent to further improve the cell density.

On the other hand, in the power MOSFET, a protective resistor is inserted in the gate electrode in order to protect the gate oxide film from electrostatic breakdown. A plan view of a conventional power MOSFET is shown in FIG. Reference numeral 1 denotes a gate pad electrode, below which a protective Zener diode 2 (rectangular dotted line) is formed, and the electrode is taken out by a bonding wire as indicated by a dotted circle. 3 is a protective resistor formed of polysilicon for preventing electrostatic breakdown,
One end is connected to the gate pad electrode 1 and the other end is connected to the gate connecting electrode 4. Reference numeral 5 denotes an actual operation region in which a large number of MOS transistor cells 6 forming a power MOSFET are arranged. Reference numeral 7 denotes a source electrode, which is provided on the actual operation region 5 so as to be connected to the source region of each cell. Reference numeral 5 denotes a gate connection electrode 4, which is connected to the gate electrode of each cell 6 and arranged around the actual operation region 5. A bonding wire is thermally thickly attached to the source electrode 7 as indicated by a dotted circle to take out the electrode.

An equivalent circuit diagram of the power MOSFET according to FIG. 6 is shown. According to this figure, the Zener diode Z _D (reference numeral 2 in FIG. 5) is connected between the gate terminal G and the source terminal S, and the protective resistor R _P (reference numeral 3 in FIG. 5) is connected between the gate terminal G and the gate electrode. ) Is connected. The diode D _I is a substrate diode and is connected between the drain terminal D and the source terminal S.

[0007]

Such a conventional power M
In the OSFET, a resistor for licking a steep pulse-like waveform of static electricity is indispensable, and the space for arranging the resistor reduces the area of the actual operating region. Even if the cell structure is a trench type, a certain cell density is obtained. However, there was an unavoidable problem.

Further, since the resistor is connected to one part of the gate connecting electrode, there is a problem that the operation of each cell constituting the power MOSFET cannot be made uniform.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and provides an insulated gate semiconductor device having a high cell density by extending the area of an actual operating region by extending a resistor around the chip. To do.

By arranging the resistor, the source electrode and the gate pad electrode symmetrically, it is possible to provide an insulated gate type semiconductor device having a high cell density which allows uniform operation of each cell in the actual operation region. is there.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail with reference to FIGS. Power MOSF of the present invention
A plan view of the ET is shown in FIG. Reference numeral 11 denotes a gate pad electrode, below which a protective Zener diode 12 (rectangular dotted line) is formed, and the electrode is taken out by a bonding wire as indicated by a dotted circle. Reference numeral 13 denotes a protective resistor formed of polysilicon for preventing electrostatic breakdown, and has one end connected to the gate pad electrode 11 and the other end connected to the gate connecting electrode 14. Reference numeral 15 is an actual operating region, in which cells 16 of a large number of MOS transistors forming a power MOSFET are arranged. Reference numeral 17 denotes a source electrode, which is provided on the actual operation region 15 and is connected to the source region of each cell 16. Reference numeral 14 denotes a gate connection electrode, which is connected to the gate electrode of each cell 16 and arranged around the actual operation region 15. A bonding wire is thermally thickly attached to the source electrode 17 as indicated by a dotted circle to take out the electrode. Reference numeral 18 denotes a field electrode, which contacts a guard ring provided below the field electrode to prevent the depletion layer from spreading to the chip termination.

FIG. 3 shows a trench type cell 1 used in the present invention.
The sectional structure of No. 6 will be described. Each cell 16 has an N + type semiconductor substrate 21, a drain region 22 formed of an N− type epitaxial layer, a P type channel layer 23 provided thereon, and the channel layer 23 reaching the drain region 22. A trench 24, a gate oxide film 25 covering the inner wall of the trench 21, a gate electrode 26 made of polysilicon with which the trench 21 is filled, and a channel region 27 formed in a channel layer 27 below the gate electrode 26. , N formed on the surface of the channel layer 23 adjacent to the trench 24
A + type source region 28, a P + type body contact region 29 formed on the surface of the channel layer 23 between the source regions 28, and an interlayer insulating film 30 provided on the trench 24.
And the source electrode 17 in contact with the source region 28 and the body contact region 29. A large number of such cells 16 are arranged in the actual operation region 15 of FIGS. Specifically, one cell is represented by a small square.

The first feature of the present invention is that the protective resistor 13 is used.
Is located. The resistor 13 extends along the periphery of the chip, and is provided especially between the actual operation region 15 and the field electrode 18. As a result, it is only necessary to reduce the area of the actual operation region 15 a little, and the power MOSFE with a small chip size is used.
T is extremely advantageous in improving the cell density.

Further, since the resistor 13 is formed of polysilicon, if the surface of the polysilicon is insulated with an oxide film, a part or almost all of the resistor 13 can be arranged under the gate connecting electrode 14, and an actual operating region is obtained. 15 can be formed in the entire central portion of the chip except the gate pad electrode 11 and the gate connecting electrode 14.

The second feature of the present invention is to prepare two resistors 13 in order to realize a uniform operation of the entire chip, and to perform a symmetrical layout with the gate pad electrode 11, the gate connecting electrode 14 and the source electrode 17. Especially.

FIG. 1 shows a first layout in which a gate pad electrode 11 is provided at one corner portion of a chip and 2
The resistors 13 of the book extend from the gate pad electrode 11 along the two sides in contact with the electrode 11 between the actual operation region 15 and the field electrode 18. Gate connection electrode 1
Reference numeral 4 is provided so as to surround the actual operation region 15, and a part or most of the resistors 13, 13 is arranged below it. Therefore, the actual operation region 15 has a square or rectangular shape with a portion where the gate pad electrode 11 is cut out, and a large number of cells 16 are provided in the region 15. Therefore, this first
In this layout, the line is symmetrical with respect to the diagonal line passing over the gate pad electrode 11.

FIG. 2 shows a second layout in which the gate pad electrode 11 is provided at the central peripheral edge of one side of the chip, and the two resistors 13 and 13 are provided between the actual operating region 15 and the field electrode 18. From the gate pad electrode 11 to the electrode 1
1 extend in opposite directions along the contacting sides of 1, and are respectively bent at right angles and further extend along adjacent sides. The gate connection electrode 14 is provided so as to surround the actual operation region 15, and a part or most of the resistors 13, 13 is arranged under the gate connection electrode 14. Therefore, the actual operation region 15 is the gate pad electrode 1
1 has a concave shape in which a part is cut out, and the area 1
5, a large number of cells 16 are provided. Therefore, the second layout is line-symmetric with respect to the center line passing over the gate electrostatic breakdown withstanding pad electrode 11.

Due to the symmetrical layout described above, a large number of cells 16 provided in the actual operation region 15 can be operated uniformly.

The protective resistors 13 and 13 are formed in the same symmetrical shape, and one end of each of them is formed into the gate pad electrode 11.
To the gate connection electrode 1 at the other end
4 is in ohmic contact. The resistance value is determined by the level of electrostatic breakdown resistance, and when it is desired to obtain an electrostatic breakdown resistance of 300 V, it is set to about 1.5 KΩ in the P-channel power MOSFET. Therefore, the resistors 13 and 13 are extended until the required resistance value is obtained, and the other end of each is brought into contact with the gate connection electrode 14 at that position.

FIG. 4 shows an equivalent circuit diagram of the power MOSFET of the present invention. According to this figure, a Zener diode Z _D (reference numeral 12 in FIG. 5) is provided between the gate terminal G and the source terminal S.
Are connected between the gate terminal G and the gate electrode, and two protective resistors R _P1 , R _P2 (reference numeral 13, 13 in FIG. 5) is connected. The diode D _I is a substrate diode and is connected between the drain terminal D and the source terminal S.

220 in the power MOSFET according to the present invention
When the electrostatic breakdown withstand voltage was examined by pF capacitor charging, it was 70V in the past, but it could be improved to 200V in the present invention.

[0022]

According to the present invention, first, the resistance element 13 for electrostatic breakdown protection is extended between the field electrode 18 and the actual operating region 15, so that the area of the actual operating region 15 is reduced. Resistor 1 for minimizing electrostatic discharge resistance
3 has the advantage that it can be mounted in a chip.

Secondly, since the resistor 13 is made of polysilicon, it can be placed under the gate connecting electrode 14 partially or almost entirely. As a result, since the resistor 13 can be formed without substantially reducing the area of the actual operation region 15, the area of the actual operation region 15 can be significantly increased as compared with the conventional case, and the cell density with respect to the chip area can be improved. is there. When a high resistance to electrostatic breakdown is required, the resistance value of the resistor 13 increases, but the resistor 13 can extend under the gate connecting electrode 14 over the entire circumference, so that the area of the actual operating region 15 is reduced. There is also an advantage that a large resistor 13 can be built in without any need.

Thirdly, the layout of the entire chip is shown by the gate pad electrode 11, the resistors 13, 13, and the gate connecting electrode 1.
4. Since it can be made symmetrical including the actual operation region 15, each cell 16, the source electrode 17, etc., the operation of each cell can be made uniform,
Smaller chip size power MOS with good operation efficiency
It has the advantage that a FET can provide.

[Brief description of drawings]

FIG. 1 is a plan view illustrating an insulated gate semiconductor device of the present invention.

FIG. 2 is a plan view illustrating another insulated gate semiconductor device of the present invention.

FIG. 3 is a sectional view illustrating a cell structure of a power MOSFET used in the present invention.

FIG. 4 is a circuit diagram illustrating an equivalent circuit of the insulated gate semiconductor device of the present invention.

FIG. 5 is a plan view illustrating a conventional power MOSFET.

FIG. 6 is a circuit diagram illustrating an equivalent circuit of a conventional power MOSFET.

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Claims (5)

(57) [Claims] 1. An actual operation area in which cells of a large number of MOS transistors are arranged, and the MOS provided on the actual operation area.
A protection electrode provided with a source electrode connected to the source region of each cell of the transistor and a gate pad electrode connected to the gate electrode of each cell of the MOS transistor, and inserted between the gate pad electrode and the gate electrode; An insulated gate semiconductor device, comprising: a resistor for use in the periphery of a chip. 2. The insulated gate according to claim 1, wherein the resistor is formed of polysilicon and is disposed under a gate connecting electrode connecting the gate electrode and the gate pad electrode. Type semiconductor device. 3. The insulated gate semiconductor device according to claim 1, wherein the two resistance bodies are provided and are arranged symmetrically with the gate pad electrode and the source electrode. 4. The gate pad electrode is provided at a corner of a chip, the source electrode is provided substantially at a portion other than the gate pad electrode, and the resistor is extended from the gate pad electrode along two sides of the chip. The insulated gate semiconductor device according to any one of claims 1 to 3, which is symmetrical with respect to a diagonal line of the chip. 5. The gate pad electrode is provided at the center of one side of the chip, the source electrode is provided substantially at a portion other than the gate pad electrode, and the resistor is provided from the gate pad electrode along two sides of the chip. 4. The insulated gate semiconductor device according to claim 1, wherein the insulated gate semiconductor device is extended and symmetrical with respect to the center line of the chip.