JP3505461B2 - Insulated gate semiconductor device - Google Patents
Insulated gate semiconductor deviceInfo
- Publication number
- JP3505461B2 JP3505461B2 JP2000058642A JP2000058642A JP3505461B2 JP 3505461 B2 JP3505461 B2 JP 3505461B2 JP 2000058642 A JP2000058642 A JP 2000058642A JP 2000058642 A JP2000058642 A JP 2000058642A JP 3505461 B2 JP3505461 B2 JP 3505461B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- gate
- chip
- pad electrode
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Description
【発明の詳細な説明】Detailed Description of the Invention
【0001】[0001]
【発明の属する技術分野】本発明は絶縁ゲート型半導体
装置に係り、特に静電破壊から保護する保護用抵抗体を
備えた絶縁ゲート型半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate type semiconductor device, and more particularly to an insulated gate type semiconductor device provided with a protective resistor for protection against electrostatic breakdown.
【0002】[0002]
【従来の技術】携帯端末の普及に伴い小型で大容量のリ
チュウムイオン電池が求められるようになってきた。こ
のリチュウムイオン電池の充放電のバッテリーマネージ
メントを行う保護回路は携帯端末の軽量化のニーズによ
り、より小型で負荷ショートにも十分に耐えうるもので
なくてはならない。かかる保護回路はリチュウムイオン
電池の容器内に内蔵されるために小型化が求められ、チ
ップ部品を多用したCOB(Chip on Boar
d)技術が駆使され、小型化の要求に応えてきた。しか
し一方ではリチュウムイオン電池に直列にパワーMOS
FETを接続するのでこのパワーMOSFETのオン抵
抗も極めて小さくするニーズがあり、これが携帯電話で
は通話時間や待機時間を長くするために不可欠の要素で
ある。2. Description of the Related Art With the popularization of portable terminals, small-sized and large-capacity lithium-ion batteries have been required. The protection circuit for battery management of charge and discharge of the lithium ion battery must be smaller and sufficiently resistant to load short circuit due to the need for weight reduction of the mobile terminal. Such a protection circuit is required to be miniaturized because it is built in the container of the lithium-ion battery, and a COB (Chip on Boar) that uses many chip parts
d) Technology has been used to meet the demand for miniaturization. However, on the other hand, the power MOS is connected in series with the lithium ion battery.
Since FETs are connected, there is a need to make the on-resistance of this power MOSFET extremely small, and this is an essential element in a mobile phone in order to lengthen the call time and standby time.
【0003】特に保護回路ではリチュウムイオン電池L
iBに直列に2個のNチャンネル型のパワーMOSFE
Tが接続されるので、この2個のパワーMOSFETの
低オン抵抗(RDS(on))が最も要求される項目である。こ
のためにチップを製造する上で微細加工によりセル密度
を上げる開発が進められてきた。Particularly in the protection circuit, a lithium ion battery L
Two N-channel power MOSFE in series with iB
Since T is connected, the low on-resistance (R DS (on) ) of these two power MOSFETs is the most required item. For this reason, in the manufacture of chips, development has been advanced to increase the cell density by fine processing.
【0004】具体的には、チャンネルが半導体基板表面
に形成されるプレーナー構造ではセル密度は740万個
/平方インチであったが、チャンネルをトレンチの側面
に形成するトレンチ構造の第1世代ではセル密度は25
00万個/平方インチと大幅に向上した。さらにトレン
チ構造の第2世代ではセル密度は7200万個/平方イ
ンチまで向上できた。しかし微細化にも限度があり、セ
ル密度をさらに飛躍的に向上するには限界が見えてき
た。Specifically, the cell density was 7.4 million cells / square inch in the planar structure in which the channels were formed on the surface of the semiconductor substrate, but in the first generation of the trench structure in which the channels were formed on the side surface of the trench, the cells were formed. Density is 25
Significantly improved to, 000,000 pieces / square inch. Furthermore, in the second generation of the trench structure, the cell density could be improved to 72 million cells / square inch. However, there is a limit to miniaturization, and the limit has become apparent to further improve the cell density.
【0005】一方、パワーMOSFETではゲート酸化
膜を静電破壊から保護するために保護用の抵抗体がゲー
ト電極に挿入されている。従来のパワーMOSFETの
平面図を5図に示す。1はゲートパッド電極であり、そ
の下には保護用のツェナーダイオード2(長方形の点
線)が形成され、点線の丸印で示すようにボンディング
ワイヤーで電極の取り出しが行われる。3はポリシリコ
ンで形成された静電破壊防止の保護用の抵抗体であり、
一端をゲートパッド電極1に接続され、他端はゲート連
結電極4に接続されている。5は実動作領域であり、こ
の中にパワーMOSFETを構成する多数のMOSトラ
ンジスタのセル6が配列されている。7はソース電極で
あり、実動作領域5上には各セルのソース領域と接続て
設けられる。5はゲート連結電極4であり、各セル6の
ゲート電極と接続され且つ実動作領域5の周囲に配置さ
れている。なお、ソース電極7には点線の丸印で示すよ
うにボンディングワイヤが熱厚着され、電極の取り出し
を行う。On the other hand, in the power MOSFET, a protective resistor is inserted in the gate electrode in order to protect the gate oxide film from electrostatic breakdown. A plan view of a conventional power MOSFET is shown in FIG. Reference numeral 1 denotes a gate pad electrode, below which a protective Zener diode 2 (rectangular dotted line) is formed, and the electrode is taken out by a bonding wire as indicated by a dotted circle. 3 is a protective resistor formed of polysilicon for preventing electrostatic breakdown,
One end is connected to the gate pad electrode 1 and the other end is connected to the gate connecting electrode 4. Reference numeral 5 denotes an actual operation region in which a large number of MOS transistor cells 6 forming a power MOSFET are arranged. Reference numeral 7 denotes a source electrode, which is provided on the actual operation region 5 so as to be connected to the source region of each cell. Reference numeral 5 denotes a gate connection electrode 4, which is connected to the gate electrode of each cell 6 and arranged around the actual operation region 5. A bonding wire is thermally thickly attached to the source electrode 7 as indicated by a dotted circle to take out the electrode.
【0006】図6にかかるパワーMOSFETの等価回
路図を示す。この図によれば、ゲート端子Gとソース端
子S間にツェナーダイオードZD(図5 符号2)が接
続され、ゲート端子Gとゲート電極間には保護用の抵抗
体RP(図5 符号3)が接続される。なおダイオード
DIは基板ダイオードであり、ドレイン端子Dとソース
端子S間に接続される。An equivalent circuit diagram of the power MOSFET according to FIG. 6 is shown. According to this figure, the Zener diode Z D (reference numeral 2 in FIG. 5) is connected between the gate terminal G and the source terminal S, and the protective resistor R P (reference numeral 3 in FIG. 5) is connected between the gate terminal G and the gate electrode. ) Is connected. The diode D I is a substrate diode and is connected between the drain terminal D and the source terminal S.
【0007】[0007]
【発明が解決しようとする課題】かかる従来のパワーM
OSFETでは静電気の急峻なパルス状波形をなめすた
めの抵抗体 が不可欠であり、抵抗体を配置するスペー
スが実動作領域の面積を減らすことになり、セル構造を
トレンチ型にしてもある程度のセル密度の減少はさけら
れない問題点を有していた。Such a conventional power M
In the OSFET, a resistor for licking a steep pulse-like waveform of static electricity is indispensable, and the space for arranging the resistor reduces the area of the actual operating region. Even if the cell structure is a trench type, a certain cell density is obtained. However, there was an unavoidable problem.
【0008】また抵抗体はゲート連結電極の一個所に接
続されるので、パワーMOSFETを構成する各セルの
動作を均一にできない問題点もあった。Further, since the resistor is connected to one part of the gate connecting electrode, there is a problem that the operation of each cell constituting the power MOSFET cannot be made uniform.
【0009】[0009]
【課題を解決するための手段】本発明はかかる課題に鑑
みてなされ、抵抗体をチップの周辺に延在させることに
より実動作領域の面積を拡げ、セル密度の高い絶縁ゲー
ト型半導体装置を提供するものである。SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and provides an insulated gate semiconductor device having a high cell density by extending the area of an actual operating region by extending a resistor around the chip. To do.
【0010】またこの抵抗体、ソース電極およびゲート
パッド電極とを対称に配置することにより、実動作領域
での各セルの均一な動作を行うセル密度の高い絶縁ゲー
ト型半導体装置を提供するものである。By arranging the resistor, the source electrode and the gate pad electrode symmetrically, it is possible to provide an insulated gate type semiconductor device having a high cell density which allows uniform operation of each cell in the actual operation region. is there.
【0011】[0011]
【発明の実施の形態】本発明の実施の形態を図1から図
4を参照して詳細に説明する。本発明のパワーMOSF
ETの平面図を図1に示す。11はゲートパッド電極で
あり、その下には保護用のツェナーダイオード12(長
方形の点線)が形成され、点線の丸印で示すようにボン
ディングワイヤーで電極の取り出しが行われる。13は
ポリシリコンで形成された静電破壊防止の保護用の抵抗
体であり、一端をゲートパッド電極11に接続され、他
端はゲート連結電極14に接続されている。15は実動
作領域であり、この中にパワーMOSFETを構成する
多数のMOSトランジスタのセル16が配列されてい
る。17はソース電極であり、実動作領域15上に設け
られ且つ各セル16のソース領域と接続して設けられ
る。14はゲート連結電極であり、各セル16のゲート
電極と接続され且つ実動作領域15の周囲に配置されて
いる。なお、ソース電極17には点線の丸印で示すよう
にボンディングワイヤが熱厚着され、電極の取り出しを
行う。18はフィールド電極であり、その下に設けたガ
ードリングとコンタクトしてチップ終端への空乏層の拡
がりを抑える。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail with reference to FIGS. Power MOSF of the present invention
A plan view of the ET is shown in FIG. Reference numeral 11 denotes a gate pad electrode, below which a protective Zener diode 12 (rectangular dotted line) is formed, and the electrode is taken out by a bonding wire as indicated by a dotted circle. Reference numeral 13 denotes a protective resistor formed of polysilicon for preventing electrostatic breakdown, and has one end connected to the gate pad electrode 11 and the other end connected to the gate connecting electrode 14. Reference numeral 15 is an actual operating region, in which cells 16 of a large number of MOS transistors forming a power MOSFET are arranged. Reference numeral 17 denotes a source electrode, which is provided on the actual operation region 15 and is connected to the source region of each cell 16. Reference numeral 14 denotes a gate connection electrode, which is connected to the gate electrode of each cell 16 and arranged around the actual operation region 15. A bonding wire is thermally thickly attached to the source electrode 17 as indicated by a dotted circle to take out the electrode. Reference numeral 18 denotes a field electrode, which contacts a guard ring provided below the field electrode to prevent the depletion layer from spreading to the chip termination.
【0012】図3は本発明に用いるトレンチ型のセル1
6の断面構造を説明する。各セル16は、N+型の半導
体基板21と、N−型のエピタキシャル層からなるドレ
イン領域22と、その上に設けられたP型のチャネル層
23と、チャネル層23からドレイン領域22まで到達
するトレンチ24と、トレンチ21の内壁を被覆するゲ
ート酸化膜25と、トレンチ21にの充填されたポリシ
リコンよりなるゲート電極26と、ゲート電極26下の
チャネル層27に形成されるチャネル領域27と、トレ
ンチ24に隣接したチャネル層23表面に形成されるN
+型のソース領域28と、ソース領域28間のチャネル
層23表面に形成されるP+型のボディコンタクト領域
29と、トレンチ24上に設けられた層間絶縁膜30
と、ソース領域28およびボディコンタクト領域29に
コンタクトするソース電極17で構成される。かかるセ
ル16は図1および図2の実動作領域15に多数個配列
される。具体的には小さい四角で表示したものが1個の
セルである。FIG. 3 shows a trench type cell 1 used in the present invention.
The sectional structure of No. 6 will be described. Each cell 16 has an N + type semiconductor substrate 21, a drain region 22 formed of an N− type epitaxial layer, a P type channel layer 23 provided thereon, and the channel layer 23 reaching the drain region 22. A trench 24, a gate oxide film 25 covering the inner wall of the trench 21, a gate electrode 26 made of polysilicon with which the trench 21 is filled, and a channel region 27 formed in a channel layer 27 below the gate electrode 26. , N formed on the surface of the channel layer 23 adjacent to the trench 24
A + type source region 28, a P + type body contact region 29 formed on the surface of the channel layer 23 between the source regions 28, and an interlayer insulating film 30 provided on the trench 24.
And the source electrode 17 in contact with the source region 28 and the body contact region 29. A large number of such cells 16 are arranged in the actual operation region 15 of FIGS. Specifically, one cell is represented by a small square.
【0013】本発明の第1の特徴は保護用の抵抗体13
の配置にある。抵抗体13はチップ周辺に沿って延在さ
れ、特に実動作領域15とフィールド電極18の間に設
けられる。これにより実動作領域15の面積を少し減ら
すだけで良く、チップサイズの小さいパワーMOSFE
Tでは極めてセル密度を向上する上で有利となる。The first feature of the present invention is that the protective resistor 13 is used.
Is located. The resistor 13 extends along the periphery of the chip, and is provided especially between the actual operation region 15 and the field electrode 18. As a result, it is only necessary to reduce the area of the actual operation region 15 a little, and the power MOSFE with a small chip size is used.
T is extremely advantageous in improving the cell density.
【0014】またこの抵抗体13はポリシリコンで形成
されるので、ポリシリコン表面を酸化膜で絶縁すればゲ
ート連結電極14の下にその一部あるいはほとんど全部
を配置することができ、実動作領域15をゲートパッド
電極11とゲート連結電極14以外のチップ中央部全て
に形成できる。Further, since the resistor 13 is formed of polysilicon, if the surface of the polysilicon is insulated with an oxide film, a part or almost all of the resistor 13 can be arranged under the gate connecting electrode 14, and an actual operating region is obtained. 15 can be formed in the entire central portion of the chip except the gate pad electrode 11 and the gate connecting electrode 14.
【0015】本発明の第2の特徴はチップ全体の均一動
作を実現するために抵抗体13を2本準備し、しかもゲ
ートパッド電極11,ゲート連結電極14、ソース電極
17とともに対称なレイアウトを行うことにある。The second feature of the present invention is to prepare two resistors 13 in order to realize a uniform operation of the entire chip, and to perform a symmetrical layout with the gate pad electrode 11, the gate connecting electrode 14 and the source electrode 17. Especially.
【0016】図1は第1のレイアウトを示しており、ゲ
ートパッド電極11をチップの1コーナー部に設け、2
本の抵抗体13、13はゲートパッド電極11からその
電極11の接する2辺に沿って実動作領域15とフィー
ルド電極18の間に延在させている。ゲート連結電極1
4は実動作領域15を囲むように設けられ、その下に抵
抗体13、13の一部あるいは大部分を配置する。従っ
て実動作領域15はゲートパッド電極11がある部分を
切り欠いた正方形あるいは長方形をしており、その領域
15に多数のセル16を設けている。従って、この第1
のレイアウトではゲートパッド電極11上を通る対角線
に対して線対称となる。FIG. 1 shows a first layout in which a gate pad electrode 11 is provided at one corner portion of a chip and 2
The resistors 13 of the book extend from the gate pad electrode 11 along the two sides in contact with the electrode 11 between the actual operation region 15 and the field electrode 18. Gate connection electrode 1
Reference numeral 4 is provided so as to surround the actual operation region 15, and a part or most of the resistors 13, 13 is arranged below it. Therefore, the actual operation region 15 has a square or rectangular shape with a portion where the gate pad electrode 11 is cut out, and a large number of cells 16 are provided in the region 15. Therefore, this first
In this layout, the line is symmetrical with respect to the diagonal line passing over the gate pad electrode 11.
【0017】図2は第2のレイアウトを示しており、ゲ
ートパッド電極11をチップの1辺の中央周端部に設
け、2本の抵抗体13、13は実動作領域15とフィー
ルド電極18間をゲートパッド電極11からその電極1
1の接する辺に沿って反対方向に延在され、それぞれ直
角に曲げられて隣接する辺に沿って更に延在される。ゲ
ート連結電極14は実動作領域15を囲むように設けら
れ、その下に抵抗体13、13の一部あるいは大部分を
配置する。従って実動作領域15はゲートパッド電極1
1がある部分を切り欠いた凹形をしており、その領域1
5に多数のセル16を設けている。従って、この第2の
レイアウトではゲート静電破壊耐量パッド電極11上を
通る中心線に対して線対称となる。FIG. 2 shows a second layout in which the gate pad electrode 11 is provided at the central peripheral edge of one side of the chip, and the two resistors 13 and 13 are provided between the actual operating region 15 and the field electrode 18. From the gate pad electrode 11 to the electrode 1
1 extend in opposite directions along the contacting sides of 1, and are respectively bent at right angles and further extend along adjacent sides. The gate connection electrode 14 is provided so as to surround the actual operation region 15, and a part or most of the resistors 13, 13 is arranged under the gate connection electrode 14. Therefore, the actual operation region 15 is the gate pad electrode 1
1 has a concave shape in which a part is cut out, and the area 1
5, a large number of cells 16 are provided. Therefore, the second layout is line-symmetric with respect to the center line passing over the gate electrostatic breakdown withstanding pad electrode 11.
【0018】上述した対称なレイアウトにより実動作領
域15に多数個設けた各セル16は均一な動作が行え
る。Due to the symmetrical layout described above, a large number of cells 16 provided in the actual operation region 15 can be operated uniformly.
【0019】また保護用の抵抗体13、13は同じ対称
な形状に形成され、各々の一端をゲートパッド電極11
にオーミック接触させ、各々の他端はゲート連結電極1
4にオーミック接触させている。その抵抗値は静電破壊
耐量のレベルで決められ、300Vの静電破壊耐量を得
たい場合はPチャンネルのパワーMOSFETでは約
1.5KΩに設定する。従って抵抗体13、13は必要
な抵抗値が得られるまで延在され、各々の他端はその位
置のゲート連結電極14にコンタクトさせる。The protective resistors 13 and 13 are formed in the same symmetrical shape, and one end of each of them is formed into the gate pad electrode 11.
To the gate connection electrode 1 at the other end
4 is in ohmic contact. The resistance value is determined by the level of electrostatic breakdown resistance, and when it is desired to obtain an electrostatic breakdown resistance of 300 V, it is set to about 1.5 KΩ in the P-channel power MOSFET. Therefore, the resistors 13 and 13 are extended until the required resistance value is obtained, and the other end of each is brought into contact with the gate connection electrode 14 at that position.
【0020】図4に本発明のパワーMOSFETの等価
回路図を示す。この図によれば、ゲート端子Gとソース
端子S間にツェナーダイオードZD(図5 符号12)
が接続され、ゲート端子Gとゲート電極間には保護用の
2本の抵抗体RP1 , RP2(図5 符号13、13)が
接続される。なおダイオードDIは基板ダイオードであ
り、ドレイン端子Dとソース端子S間に接続される。FIG. 4 shows an equivalent circuit diagram of the power MOSFET of the present invention. According to this figure, a Zener diode Z D (reference numeral 12 in FIG. 5) is provided between the gate terminal G and the source terminal S.
Are connected between the gate terminal G and the gate electrode, and two protective resistors R P1 , R P2 (reference numeral 13, 13 in FIG. 5) is connected. The diode D I is a substrate diode and is connected between the drain terminal D and the source terminal S.
【0021】本発明によるパワーMOSFETで220
pFのコンデンサチャージで静電破壊耐量を調べると従
来では70Vであったものが、本発明では200Vまで
改善できた。220 in the power MOSFET according to the present invention
When the electrostatic breakdown withstand voltage was examined by pF capacitor charging, it was 70V in the past, but it could be improved to 200V in the present invention.
【0022】[0022]
【発明の効果】本発明に依れば、第1に静電破壊保護用
の抵抗体13をフィールド電極18と実動作領域15の
間に延在させるので、実動作領域15の面積の減少を最
小限に止め、所望の静電破壊耐量を得るための抵抗体1
3をチップ内に実装できる利点を有する。According to the present invention, first, the resistance element 13 for electrostatic breakdown protection is extended between the field electrode 18 and the actual operating region 15, so that the area of the actual operating region 15 is reduced. Resistor 1 for minimizing electrostatic discharge resistance
3 has the advantage that it can be mounted in a chip.
【0023】第2に、この抵抗体13はポリシリコンで
形成されているので、ゲート連結電極14の下にその一
部あるいはほとんど全部を重ねて配置できる。この結
果、実動作領域15の面積を実質的に減らさずに抵抗体
13が形成できるので、従来に比べて実動作領域15の
面積を大幅に増加でき、チップ面積に対するセル密度も
向上できる利点がある。また高い静電破壊耐量を求めら
れる場合、抵抗体13の抵抗値は大きくなるが、抵抗体
13はゲート連結電極14の下を全周に渡り延在できる
ので、実動作領域15の面積を減らすことなく大きい抵
抗体13を内蔵可能となる利点も有する。Secondly, since the resistor 13 is made of polysilicon, it can be placed under the gate connecting electrode 14 partially or almost entirely. As a result, since the resistor 13 can be formed without substantially reducing the area of the actual operation region 15, the area of the actual operation region 15 can be significantly increased as compared with the conventional case, and the cell density with respect to the chip area can be improved. is there. When a high resistance to electrostatic breakdown is required, the resistance value of the resistor 13 increases, but the resistor 13 can extend under the gate connecting electrode 14 over the entire circumference, so that the area of the actual operating region 15 is reduced. There is also an advantage that a large resistor 13 can be built in without any need.
【0024】第3に、チップ全体のレイアウトをゲート
パッド電極11、抵抗体13、13、ゲート連結電極1
4、実動作領域15、各セル16、ソース電極17等を
含めて対称にできるので、各セルの動作を均一にでき、
動作効率が良いより小さいチップサイズのパワーMOS
FETが提供できる利点を有する。Thirdly, the layout of the entire chip is shown by the gate pad electrode 11, the resistors 13, 13, and the gate connecting electrode 1.
4. Since it can be made symmetrical including the actual operation region 15, each cell 16, the source electrode 17, etc., the operation of each cell can be made uniform,
Smaller chip size power MOS with good operation efficiency
It has the advantage that a FET can provide.
【図1】本発明の絶縁ゲート型半導体装置を説明する平
面図である。FIG. 1 is a plan view illustrating an insulated gate semiconductor device of the present invention.
【図2】本発明の他の絶縁ゲート型半導体装置を説明す
る平面図である。FIG. 2 is a plan view illustrating another insulated gate semiconductor device of the present invention.
【図3】本発明に用いるパワーMOSFETのセル構造
を説明する断面図である。FIG. 3 is a sectional view illustrating a cell structure of a power MOSFET used in the present invention.
【図4】本発明の絶縁ゲート型半導体装置の等価回路を
説明する回路図である。FIG. 4 is a circuit diagram illustrating an equivalent circuit of the insulated gate semiconductor device of the present invention.
【図5】従来のパワーMOSFETを説明する平面図で
ある。FIG. 5 is a plan view illustrating a conventional power MOSFET.
【図6】従来のパワーMOSFETの等価回路を説明す
る回路図である。FIG. 6 is a circuit diagram illustrating an equivalent circuit of a conventional power MOSFET.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI H01L 21/822 H01L 27/04 H 27/04 ─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. 7 Identification code FI H01L 21/822 H01L 27/04 H 27/04
Claims (5)
れた実動作領域と該実動作領域上に設けられ前記MOS
トランジスタの各セルのソース領域と接続されたソース
電極と前記MOSトランジスタの各セルのゲート電極と
接続されたゲートパッド電極とを備え、前記ゲートパッ
ド電極と前記ゲート電極との間に挿入される保護用抵抗
体をチップの周辺に延在させたことを特徴とする絶縁ゲ
ート型半導体装置。1. An actual operation area in which cells of a large number of MOS transistors are arranged, and the MOS provided on the actual operation area.
A protection electrode provided with a source electrode connected to the source region of each cell of the transistor and a gate pad electrode connected to the gate electrode of each cell of the MOS transistor, and inserted between the gate pad electrode and the gate electrode; An insulated gate semiconductor device, comprising: a resistor for use in the periphery of a chip.
大部分が前記ゲート電極と前記ゲートパッド電極を接続
するゲート連結電極の下に配置されることを特徴とする
請求項1記載の絶縁ゲート型半導体装置。2. The insulated gate according to claim 1, wherein the resistor is formed of polysilicon and is disposed under a gate connecting electrode connecting the gate electrode and the gate pad electrode. Type semiconductor device.
電極および前記ソース電極とともに対称となるように配
置することを特徴とする請求項1または請求項2に記載
の絶縁ゲート型半導体装置。3. The insulated gate semiconductor device according to claim 1, wherein the two resistance bodies are provided and are arranged symmetrically with the gate pad electrode and the source electrode.
に設け、前記ソース電極をほぼ前記ゲートパッド電極以
外の部分に設け、前記抵抗体を前記ゲートパッド電極か
らチップの2辺に沿って延在させチップの対角線で対称
となることを特徴とする請求項1から請求項3のいずれ
かに記載の絶縁ゲート型半導体装置。4. The gate pad electrode is provided at a corner of a chip, the source electrode is provided substantially at a portion other than the gate pad electrode, and the resistor is extended from the gate pad electrode along two sides of the chip. The insulated gate semiconductor device according to any one of claims 1 to 3, which is symmetrical with respect to a diagonal line of the chip.
央に設け、前記ソース電極をほぼ前記ゲートパッド電極
以外の部分に設け、前記抵抗体を前記ゲートパッド電極
からチップの2辺に沿って延在させチップの中心線で対
称となることを特徴とする請求項1から請求項3のいず
れかに記載の絶縁ゲート型半導体装置。5. The gate pad electrode is provided at the center of one side of the chip, the source electrode is provided substantially at a portion other than the gate pad electrode, and the resistor is provided from the gate pad electrode along two sides of the chip. 4. The insulated gate semiconductor device according to claim 1, wherein the insulated gate semiconductor device is extended and symmetrical with respect to the center line of the chip.
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JP2000058642A JP3505461B2 (en) | 2000-03-03 | 2000-03-03 | Insulated gate semiconductor device |
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JP5775268B2 (en) * | 2010-06-09 | 2015-09-09 | ローム株式会社 | Semiconductor device and manufacturing method thereof |
JP5664302B2 (en) * | 2011-02-08 | 2015-02-04 | 株式会社デンソー | Semiconductor device |
EP2602828A1 (en) | 2011-12-07 | 2013-06-12 | Nxp B.V. | Semiconductor device having isolation trenches |
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CN103579322B (en) * | 2013-11-13 | 2016-09-21 | 国家电网公司 | A kind of IGBT device and manufacture method thereof strengthening switching speed and switching uniformity |
WO2015080162A1 (en) | 2013-11-28 | 2015-06-04 | ローム株式会社 | Semiconductor device |
CN105514154B (en) * | 2014-09-22 | 2019-04-05 | 国家电网公司 | Improve the IGBT device and manufacturing method of active area and terminal connection region field strength uniformity |
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