JP2001250946A - Insulated gate semiconductor device - Google Patents

Insulated gate semiconductor device

Info

Publication number
JP2001250946A
JP2001250946A JP2000058641A JP2000058641A JP2001250946A JP 2001250946 A JP2001250946 A JP 2001250946A JP 2000058641 A JP2000058641 A JP 2000058641A JP 2000058641 A JP2000058641 A JP 2000058641A JP 2001250946 A JP2001250946 A JP 2001250946A
Authority
JP
Japan
Prior art keywords
source
cell
electrode
pad electrode
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000058641A
Other languages
Japanese (ja)
Inventor
Mitsuhiro Yoshimura
充弘 吉村
Yasuhiro Igarashi
保裕 五十嵐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP2000058641A priority Critical patent/JP2001250946A/en
Publication of JP2001250946A publication Critical patent/JP2001250946A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05557—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05558—Shape in side view conformal layer on a patterned surface
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4807—Shape of bonding interfaces, e.g. interlocking features
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4845—Details of ball bonds
    • H01L2224/48451—Shape
    • H01L2224/48453—Shape of the interface with the bonding area
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01004—Beryllium [Be]
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    • H01L2924/01033—Arsenic [As]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

PROBLEM TO BE SOLVED: To solve the problem in a power MOSFET due to the fact that a layer insulation film is micro-cracked by stresses of welding a bonding wire to the source electrode and that gate-source short circuit is generated. SOLUTION: No cell 4 is formed beneath source pad electrodes 8 forming a part of source electrodes 5 and hence the gate-source short circuit can be prevented, if a stress is applied during bonding, thereby providing a high reliability insulated gate type semiconductor device.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は絶縁ゲート型半導体
装置に係り、特にトレンチ型のセルを備えた絶縁ゲート
型半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate semiconductor device, and more particularly to an insulated gate semiconductor device having a trench cell.

【０００２】[0002]

【従来の技術】携帯端末の普及に伴い小型で大容量のリ
チュウムイオン電池が求められるようになってきた。こ
のリチュウムイオン電池の充放電のバッテリーマネージ
メントを行う保護回路は携帯端末の軽量化のニーズによ
り、より小型で負荷ショートにも十分に耐えうるもので
なくてはならない。かかる保護回路はリチュウムイオン
電池の容器内に内蔵されるために小型化が求められ、チ
ップ部品を多用したＣＯＢ(Ｃｈｉｐ ｏｎ Ｂｏａｒ
ｄ)技術が駆使され、小型化の要求に応えてきた。しか
し一方ではリチュウムイオン電池に直列にパワーＭＯＳ
ＦＥＴを接続するのでこのパワーＭＯＳＦＥＴのオン抵
抗も極めて小さくするニーズがあり、これが携帯電話で
は通話時間や待機時間を長くするために不可欠の要素で
ある。2. Description of the Related Art With the spread of portable terminals, a small-sized and large-capacity lithium-ion battery has been required. The protection circuit for performing the battery management of the charging and discharging of the lithium ion battery must be smaller and capable of sufficiently withstanding a load short due to the need for reducing the weight of the portable terminal. Such a protection circuit is required to be miniaturized because it is built in a container of a lithium ion battery, and a COB (Chip on Boar) using a lot of chip components is required.
d) Technology has been used to meet the demand for miniaturization. However, on the other hand, a power MOS in series with a lithium ion battery
Since the FET is connected, there is a need to make the on-resistance of the power MOSFET extremely small, which is an indispensable factor for a mobile phone to increase the talk time and the standby time.

【０００３】特に保護回路ではリチュウムイオン電池Ｌ
ｉＢに直列に２個のＮチャンネル型のパワーＭＯＳＦＥ
Ｔが接続されるので、この２個のパワーＭＯＳＦＥＴの
低オン抵抗(ＲDS(on))が最も要求される項目である。こ
のためにチップを製造する上で微細加工によりセル密度
を上げる開発が進められてきた。In particular, in the protection circuit, a lithium ion battery L
Two N-channel power MOSFETs in series with iB
Since T is connected, the low on-resistance (R DS (on) ) of these two power MOSFETs is the most required item. For this reason, development for increasing the cell density by fine processing in manufacturing chips has been promoted.

【０００４】具体的には、チャンネルが半導体基板表面
に形成されるプレーナー構造ではセル密度は７４０万個
／平方インチであったが、チャンネルをトレンチの側面
に形成するトレンチ構造の第１世代ではセル密度は２５
００万個／平方インチと大幅に向上した。さらにトレン
チ構造の第２世代ではセル密度は７２００万個／平方イ
ンチまで向上できた。Specifically, in the planar structure in which the channel is formed on the surface of the semiconductor substrate, the cell density is 7.4 million cells / square inch. The density is 25
It has greatly improved to one million pieces / square inch. In the second generation of the trench structure, the cell density was improved to 72 million cells / square inch.

【０００５】従来のパワーＭＯＳＦＥＴの平面図を図３
に示す。１はゲートパッド電極であり、点線の丸印で示
すようにゲート電極取り出し用のボンディングワイヤー
２で電極の取り出しが行われる。３は実動作領域であ
り、この中にパワーＭＯＳＦＥＴを構成する多数のＭＯ
Ｓトランジスタのセル４が配列されている。５はソース
電極であり、実動作領域３上には各セル４のソース領域
と接続して設けられる。６はゲート連結電極であり、各
セル４のゲート電極と接続され且つ実動作領域３の周囲
に配置されている。なお、ソース電極５には点線の丸印
で示すようにソース電極取り出し用のボンディングワイ
ヤ７が熱圧着される。FIG. 3 is a plan view of a conventional power MOSFET.
Shown in Reference numeral 1 denotes a gate pad electrode, which is taken out by a bonding wire 2 for taking out a gate electrode as shown by a dotted circle. Reference numeral 3 denotes an actual operation area in which a number of MOs constituting a power MOSFET are arranged.
An S transistor cell 4 is arranged. Reference numeral 5 denotes a source electrode, which is provided on the actual operation region 3 so as to be connected to the source region of each cell 4. Reference numeral 6 denotes a gate connection electrode, which is connected to the gate electrode of each cell 4 and is disposed around the actual operation area 3. A bonding wire 7 for extracting the source electrode is thermocompression-bonded to the source electrode 5 as shown by a dotted circle.

【０００６】図４は従来から用いられたトレンチ型のセ
ル４の断面構造を示す。各セル４は、Ｎ+型の半導体基
板１１と、Ｎ−型のエピタキシャル層からなるドレイン
領域１２と、その上に設けられたＰ型のチャネル層１３
と、チャネル層１３からドレイン領域１２まで到達する
トレンチ１４と、トレンチ１４の内壁を被覆するゲート
酸化膜１５と、トレンチ１４に充填されたポリシリコン
よりなるゲート電極１６と、ゲート電極１６下のチャネ
ル層１３に形成されるチャネル領域１７と、トレンチ１
４に隣接したチャネル層１３表面に形成されるＮ＋型の
ソース領域１８と、ソース領域１８間のチャネル層１３
表面に形成されるＰ＋型のボディコンタクト領域１９
と、トレンチ１４上に設けられたＰＳＧ膜およびＢＰＳ
Ｇ膜で厚く形成された層間絶縁膜２０と、ソース領域１
８およびボディコンタクト領域１９にコンタクトするソ
ース電極５で構成される。かかるセル４は図３の実動作
領域３全面に多数個配列される。FIG. 4 shows a cross-sectional structure of a conventional trench type cell 4. Each cell 4 includes an N + type semiconductor substrate 11, a drain region 12 made of an N − type epitaxial layer, and a P type channel layer 13 provided thereon.
A trench 14 extending from the channel layer 13 to the drain region 12, a gate oxide film 15 covering the inner wall of the trench 14, a gate electrode 16 made of polysilicon filled in the trench 14, and a channel below the gate electrode 16. Channel region 17 formed in layer 13 and trench 1
N + type source region 18 formed on the surface of channel layer 13 adjacent to channel region 4 and channel layer 13 between source regions 18
P + type body contact region 19 formed on the surface
And a PSG film and a BPS provided on the trench 14.
An interlayer insulating film 20 formed of a thick G film and a source region 1
8 and the source electrode 5 that contacts the body contact region 19. A large number of such cells 4 are arranged on the entire surface of the actual operation area 3 in FIG.

【０００７】[0007]

【発明が解決しようとする課題】かかる従来のパワーＭ
ＯＳＦＥＴではソース電極取り出し用のボンディングワ
イヤ７をソース電極５に打つ際に、そのストレスで直下
にある層間絶縁膜２０にマイクロクラック２１が多数発
生しゲート・ソース間が短絡する不良が多く発生する問
題点を有していた。The conventional power M
In the OSFET, when the bonding wire 7 for taking out the source electrode is hit on the source electrode 5, a large number of microcracks 21 are generated in the interlayer insulating film 20 immediately below due to the stress, and a problem that a short circuit between the gate and the source frequently occurs. Had a point.

【０００８】[0008]

【課題を解決するための手段】本発明はかかる課題に鑑
みてなされ、ソース電極下の実動作領域にセルを設けな
いソースパッド電極を設け、ここにボンディングワイヤ
を固着することによりゲート・ソース間短絡のない絶縁
ゲート型半導体装置を提供するものである。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and provides a source pad electrode in which no cell is provided in an actual operation area below a source electrode. An object of the present invention is to provide an insulated gate semiconductor device without a short circuit.

【０００９】[0009]

【発明の実施の形態】本発明の実施の形態を図１および
図２を参照して詳細に説明する。なお、図１および図２
において図３および図４と同一構成要素は同一符号を付
している。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2
3, the same components as those in FIGS. 3 and 4 are denoted by the same reference numerals.

【００１０】本発明のパワーＭＯＳＦＥＴの平面図を図
１に示す。１はゲートパッド電極であり、点線の丸印で
示すようにゲート電極取り出し用のボンディングワイヤ
ー２で電極の取り出しが行われる。３は実動作領域であ
り、この中にパワーＭＯＳＦＥＴを構成する多数のＭＯ
Ｓトランジスタのセル４が配列されている。５はソース
電極であり、実動作領域３上には各セル４のソース領域
と接続して設けられる。６はゲート連結電極であり、各
セル４のゲート電極と接続され且つ実動作領域３の周囲
に配置されている。なお、ソース電極５の一部にソース
パッド電極８を設け、ソースパッド電極８に点線の丸印
で示すようにソース電極取り出し用のボンディングワイ
ヤ７が熱圧着される。FIG. 1 is a plan view of a power MOSFET according to the present invention. Reference numeral 1 denotes a gate pad electrode, which is taken out by a bonding wire 2 for taking out a gate electrode as shown by a dotted circle. Reference numeral 3 denotes an actual operation area in which a number of MOs constituting a power MOSFET are arranged.
An S transistor cell 4 is arranged. Reference numeral 5 denotes a source electrode, which is provided on the actual operation region 3 so as to be connected to the source region of each cell 4. Reference numeral 6 denotes a gate connection electrode, which is connected to the gate electrode of each cell 4 and is disposed around the actual operation area 3. A source pad electrode 8 is provided on a part of the source electrode 5, and a bonding wire 7 for taking out the source electrode is thermocompression-bonded to the source pad electrode 8 as shown by a dotted circle.

【００１１】図２は本発明で用いるトレンチ型のセル４
の断面構造を示す。各セル４は、Ｎ+型の半導体基板１
１と、Ｎ−型のエピタキシャル層からなるドレイン領域
１２と、その上に設けられたＰ型のチャネル層１３と、
チャネル層１３からドレイン領域１２まで到達するトレ
ンチ１４と、トレンチ１４の内壁を被覆するゲート酸化
膜１５と、トレンチ１４に充填されたポリシリコンより
なるゲート電極１６と、ゲート電極１６下のチャネル層
１３に形成されるチャネル領域１７と、トレンチ１４に
隣接したチャネル層１３表面に形成されるＮ＋型のソー
ス領域１８と、ソース領域１８間のチャネル層１３表面
に形成されるＰ＋型のボディコンタクト領域１９と、ト
レンチ１４上に設けられたＰＳＧ膜およびＢＰＳＧ膜で
厚く形成された層間絶縁膜２０と、ソース領域１８およ
びボディコンタクト領域１９にコンタクトするソース電
極５で構成される。かかるセル４は図１の実動作領域３
全面に多数個配列される。FIG. 2 shows a trench type cell 4 used in the present invention.
1 shows a cross-sectional structure. Each cell 4 is an N + type semiconductor substrate 1
1, a drain region 12 made of an N- type epitaxial layer, a P-type channel layer 13 provided thereon,
A trench 14 extending from the channel layer 13 to the drain region 12; a gate oxide film 15 covering the inner wall of the trench 14; a gate electrode 16 made of polysilicon filled in the trench 14; , A N + -type source region 18 formed on the surface of the channel layer 13 adjacent to the trench 14, and a P + -type body contact region 19 formed on the surface of the channel layer 13 between the source regions 18. And an interlayer insulating film 20 thickly formed of a PSG film and a BPSG film provided on the trench 14, and the source electrode 5 contacting the source region 18 and the body contact region 19. The cell 4 corresponds to the actual operation area 3 shown in FIG.
Many are arranged on the whole surface.

【００１２】本発明の特徴はソースパッド電極８を設け
ることにある。すなわち、ソース電極５の一部をソース
パッド電極８としその下にはセル４を設けない。このソ
ースパッド電極８は図１に示すように、チャネル層１３
を露出して実動作領域３全体を被覆するようにソース電
極５を形成し、その一部を利用して設けられる。このソ
ースパッド電極８上にはボンデイングワイヤ７のボール
部分が熱圧着される。このときにボンデイングによるス
トレスは直接チャネル層１３に加わるが、その部分には
セル４がなく、層間絶縁膜２０も存在しないので、層間
絶縁膜２０にマイクロクラックも発生せずゲート・ソー
ス間の短絡も起こらない。A feature of the present invention resides in that a source pad electrode 8 is provided. That is, a part of the source electrode 5 is used as the source pad electrode 8 and the cell 4 is not provided under the source pad electrode 8. This source pad electrode 8 is formed on the channel layer 13 as shown in FIG.
The source electrode 5 is formed so as to cover the entire actual operation area 3 by exposing the same, and a part of the source electrode 5 is provided. A ball portion of the bonding wire 7 is thermocompression-bonded on the source pad electrode 8. At this time, stress due to bonding is directly applied to the channel layer 13, but since there is no cell 4 and no interlayer insulating film 20 in that portion, no microcracks occur in the interlayer insulating film 20 and a short circuit between the gate and the source occurs. Does not occur.

【００１３】ソースパッド電極８はゲートパッド電極１
に隣接して設けられ、１辺に沿って細長く延在される。
またソースパッド電極８はチップ周端から１５０μｍ以
内に離間する位置に設けられ、できるだけ実動作領域３
の周端に設けてセル４の個数をあまり減らさないように
配慮される。ソースパッド電極８には４本のボンディン
グワイヤが打たれ、低オン抵抗を実現するために並列接
続によりワイヤ抵抗を低減し、しかもボンディングワイ
ヤ長を最短にしてコスト低減も図っている。更にウエフ
ァー測定時にウィスカーをソースパッド電極８に立てて
テスターで特性チェックを行い良否の判定を行う際に、
このウィスカーによる針跡の傷があってもセル４にダメ
ージを与えない。The source pad electrode 8 is a gate pad electrode 1
And is elongated along one side.
Further, the source pad electrode 8 is provided at a position separated from the peripheral edge of the chip by 150 μm or less.
Is provided so that the number of cells 4 is not reduced so much. Four bonding wires are struck on the source pad electrode 8, the wire resistance is reduced by parallel connection in order to realize a low on-resistance, and the cost is reduced by minimizing the bonding wire length. Furthermore, when a whisker is placed on the source pad electrode 8 at the time of wafer measurement and the characteristics are checked by a tester to determine pass / fail,
Even if the whisker has a scar on the needle mark, the cell 4 is not damaged.

【００１４】なお、図２ではＮチャネル ＭＯＳＦＥＴ
を対象に不純物の表記を行ったが、当然Ｐチャネル Ｍ
ＯＳＦＥＴにも本発明は適用できることは明白である。FIG. 2 shows an N-channel MOSFET.
, But the P-channel M
Obviously, the present invention can be applied to OSFETs.

【００１５】[0015]

【発明の効果】本発明に依れば、第１にボンディング時
にソースパッド電極８に加わるストレスがあっても、そ
の下にはセル４が存在しないので層間絶縁膜２０にマイ
クロクラックが発生することはなくパワーＭＯＳＦＥＴ
等の絶縁ゲート型半導体装置の信頼性が大幅に向上でき
る。According to the present invention, first, even if there is a stress applied to the source pad electrode 8 during bonding, microcracks are generated in the interlayer insulating film 20 because the cell 4 does not exist under the stress. Not power MOSFET
And the like, the reliability of the insulated gate semiconductor device can be greatly improved.

【００１６】第２に、ソースパッド電極８はチップ周端
から１５０μｍ以内に離間する位置に設けられているの
で、実動作領域３に形成されるセル４の個数をあまり減
らさないように配慮され、セル密度を従来と同等に維持
できる。またソースパッド電極８には４本のボンディン
グワイヤが打たれ、低オン抵抗を実現するために並列接
続によりワイヤ抵抗を低減し、しかもボンディングワイ
ヤ長を最短にしてコスト低減も図っている。Second, since the source pad electrode 8 is provided at a position separated from the peripheral edge of the chip by 150 μm or less, care is taken not to reduce the number of cells 4 formed in the actual operation area 3 so much. The cell density can be maintained at the same level as before. In addition, four bonding wires are struck on the source pad electrode 8, and the wire resistance is reduced by parallel connection in order to realize low on-resistance, and the cost is reduced by minimizing the bonding wire length.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の絶縁ゲート型半導体装置を説明する平
面図である。FIG. 1 is a plan view illustrating an insulated gate semiconductor device of the present invention.

【図２】本発明の絶縁ゲート型半導体装置を説明する断
面図である。FIG. 2 is a cross-sectional view illustrating an insulated gate semiconductor device of the present invention.

【図３】従来のパワーＭＯＳＦＥＴを説明する平面図で
ある。FIG. 3 is a plan view illustrating a conventional power MOSFET.

【図４】従来のパワーＭＯＳＦＥＴを説明する断面図で
ある。FIG. 4 is a cross-sectional view illustrating a conventional power MOSFET.

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】 多数のＭＯＳトランジスタのセルを配列
された実動作領域と該実動作領域上に設けられ前記ＭＯ
Ｓトランジスタの各セルのソース領域と接続されたソー
ス電極を備え、前記ソース電極下の前記実動作領域に前
記セルを設けないソースパッド電極を設けたことを特徴
とする絶縁ゲート型半導体装置。1. An actual operation area in which a large number of MOS transistor cells are arranged, and the MO is provided on the actual operation area.
An insulated gate semiconductor device comprising: a source electrode connected to a source region of each cell of an S transistor; and a source pad electrode provided with no cell in the actual operation region below the source electrode. 【請求項２】 前記ソースパッド電極はチップの周端に
細長く設けられることを特徴とする請求項１記載の絶縁
ゲート型半導体装置。2. The insulated gate semiconductor device according to claim 1, wherein said source pad electrode is provided to be elongated at a peripheral end of a chip. 【請求項３】 多数のＭＯＳトランジスタのセルを配列
された実動作領域と該実動作領域上に設けられ前記ＭＯ
Ｓトランジスタの各セルのソース領域と接続されたソー
ス電極と前記ＭＯＳトランジスタの各セルのゲート領域
と接続されたソゲートパッド電極とを備え、前記ソース
電極下の前記実動作領域に前記セルを設けないソースパ
ッド電極を設け、該ソースパッド電極と前記ゲートパッ
ド電極をチップの１辺の周端に並べて配置することを特
徴とする絶縁ゲート型半導体装置。3. An actual operation area in which a large number of MOS transistor cells are arranged and said MO provided on said actual operation area.
A source electrode connected to the source region of each cell of the S transistor; and a so-gate pad electrode connected to the gate region of each cell of the MOS transistor. The cell is provided in the actual operation region below the source electrode. An insulated gate type semiconductor device, wherein a source pad electrode is provided, and the source pad electrode and the gate pad electrode are arranged side by side on one side of a chip. 【請求項４】 前記ソースパッド電極はチップの周端に
細長く設けられることを特徴とする請求項３記載の絶縁
ゲート型半導体装置。4. The insulated gate semiconductor device according to claim 3, wherein said source pad electrode is provided to be elongated at a peripheral end of a chip.
JP2000058641A 2000-03-03 2000-03-03 Insulated gate semiconductor device Pending JP2001250946A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000058641A JP2001250946A (en) 2000-03-03 2000-03-03 Insulated gate semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000058641A JP2001250946A (en) 2000-03-03 2000-03-03 Insulated gate semiconductor device

Publications (1)

Publication Number Publication Date
JP2001250946A true JP2001250946A (en) 2001-09-14

Family

ID=18579210

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000058641A Pending JP2001250946A (en) 2000-03-03 2000-03-03 Insulated gate semiconductor device

Country Status (1)

Country Link
JP (1) JP2001250946A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101024474B1 (en) * 2007-04-06 2011-03-23 산요 세미컨덕터 컴퍼니 리미티드 Electrode structure and semiconductor device
DE112009004375B4 (en) * 2009-02-16 2014-03-27 Toyota Jidosha Kabushiki Kaisha SEMICONDUCTOR DEVICE

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101024474B1 (en) * 2007-04-06 2011-03-23 산요 세미컨덕터 컴퍼니 리미티드 Electrode structure and semiconductor device
US8154129B2 (en) 2007-04-06 2012-04-10 Sanyo Semiconductor Co., Ltd. Electrode structure and semiconductor device
DE112009004375B4 (en) * 2009-02-16 2014-03-27 Toyota Jidosha Kabushiki Kaisha SEMICONDUCTOR DEVICE
US8952553B2 (en) 2009-02-16 2015-02-10 Toyota Jidosha Kabushiki Kaisha Semiconductor device with stress relaxation during wire-bonding

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