JP2002043574A - Mosfet protective device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem of a power MOSFET having a 10 V guarantee value for its gate oxide film that leakage currents become as large as 0.5 μA and two P-N junction Zener diodes consume electric power even when the MOSFET is in a turned-off state when the impurity concentrations in P-N junctions are high although the MOSFET is constituted to adjust the total protective-level voltage of the diodes to 15 V by connecting the diodes in series. SOLUTION: In an MOSFET protective device, a depletion layer is spread and the formation of tunneled electron levels is prevented by providing an N- type area 22 between the P-N junctions of the Zener diodes. Consequently, the occurrence of leakage currents can be reduced significantly and the power consumption of the diodes during the turned-off period of the MOSFET can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a protection device for a MOSFET and a method for manufacturing the same, and more particularly to a protection device for a vertical MOSFET having a trench structure and a method for manufacturing the same.

[0002]

2. Description of the Related Art With the spread of portable terminals, a small-sized and large-capacity lithium-ion battery has been required. The protection circuit for performing the battery management of the charging and discharging of the lithium ion battery must be smaller and capable of sufficiently withstanding a load short due to the need for reducing the weight of the portable terminal. Such a protection circuit is required to be miniaturized because it is built in a container of a lithium ion battery, and a COB (Chip on Boar) using a lot of chip components is required.
d) Technology has been used to meet the demand for miniaturization. However, on the other hand, a power MOS in series with a lithium ion battery
Since the FET is connected, there is a need to make the on-resistance of the power MOSFET extremely small, which is an indispensable factor for a mobile phone in order to increase the talk time and the standby time.

In particular, in the protection circuit, a lithium ion battery L
Two N-channel power MOSFETs in series with iB
Since T is connected, the low on-resistance (R _{DS (on)} ) of these two power MOSFETs is the most required item. For this reason, development for increasing the cell density by fine processing in manufacturing chips has been promoted.

On the other hand, in a power MOSFET, a protection resistor is inserted into a gate electrode to protect a thin gate oxide film from electrostatic breakdown, and a Zener diode is provided between the gate electrode and a source electrode to release static electricity to the outside. It is connected.

FIG. 8 is a plan view of a conventional power MOSFET. The power MOSFET includes a gate pad electrode 31, a Zener diode 32, a gate connection electrode 34, an actual operation area 35, and a source electrode 37.

The gate pad electrode 31 is provided on the Zener diode 32 and is in contact with the central portion of the Zener diode 32. Further, as shown by a dotted circle, the electrode is taken out by a bonding wire.

The Zener diode 32 is formed by introducing impurities into the polysilicon and is formed below the gate pad electrode 31 as shown by a concentric dotted line, the center portion is in contact with the gate pad electrode 31, and the outermost periphery is each cell 36. Is connected to the source electrode of The Zener diode 32 is provided to prevent the gate oxide film from being broken by static electricity.

The resistor 33 is formed of polysilicon and is a protective resistor for preventing electrostatic breakdown. One end is connected to the gate pad electrode 31 and the other end is connected to the gate connection electrode 34. I have.

The gate connection electrode 34 is connected to the gate electrode of each cell 36 and is disposed around the actual operation area 35.

The actual operation area 35 includes a power MOSF therein.
A large number of MOS transistor cells 36 constituting the ET are arranged.

The source electrode 37 is provided on the actual operation area 35 so as to be connected to the source area of each cell 36. Also, as shown by the dotted circles, the bonding wires are thermally thickened,
Take out the electrode.

The shield electrode 38 contacts the annular ring below the shield electrode 38 to prevent the depletion layer from spreading to the end of the chip.

The sectional structure of each trench-type cell 36 is shown on the left side of FIG. In the N-channel power MOSFET, a drain region 42 made of an N ⁻ -type epitaxial layer is provided on an N ⁺ -type semiconductor substrate 41, and a P-type channel layer 43 is provided thereon.

A trench 44 extending from the channel layer 43 to the drain region 42 is formed, an inner wall of the trench 44 is coated with a gate oxide film 45, and a gate electrode 46 made of polysilicon filled in the trench 44 is provided.
To form

On the surface of the channel layer 43 adjacent to the trench 44, an N ⁺ type source region 48 is formed.
A P ⁺ type body contact region 49 is formed on the surface of channel layer 43 between source regions 48 of one cell.

Further, a source region 48 is formed in the channel layer 43.
Then, a channel region 47 is formed along the trench 44. The trench 44 is covered with an interlayer insulating film 50, and a source electrode 37 that contacts the source region 48 and the body contact region 49 is provided.

A large number of such cells 36 are arranged in the actual operation area 35 of FIG. Specifically, one cell is represented by a small square.

FIG. 9 shows the cross-sectional structure of the Zener diode 32 on the right side. The Zener diode 32 is formed by alternately arranging P-type and N ⁺ -type ion-introduced regions using polysilicon deposited when the polysilicon is buried in the trench 44 on the gate oxide film 45 covering the channel layer 43. Formed.

[0019] The PN junction, the joining end employs a closed loop shape concentrically so as not to be exposed to the polysilicon side, center N ⁺ -type region 53, and the P-type region 51 having a width of ten and several μm An N ⁺ type region 53 of several μm
It is formed in layers. Further, since the Zener voltage per PN junction is 6 to 7 V, a Zener voltage of 15 V can be guaranteed.

That is, the guaranteed value of the gate oxide film 45 is 1
In a 0 V N-channel power MOSFET, the N ⁺ -type region 53 -P-type region 51 -N ⁺ -type region 53 -P-type region 51 -N ⁺ -type region 53 are concentrically arranged from the center.

Further, the polysilicon upper surface is BPSG
(Boron PhosphorusSilicate
Glass) film 39 and the gate pad electrode 31
And the N ⁺ -type region 53 at the center of the Zener diode 32 makes contact with the outer periphery of the Zener diode 32.
It is in contact with the source electrode 37 of the SFET.

FIG. 10 shows an equivalent circuit diagram of the power MOSFET according to the present invention. In FIG. 10, a Zener diode Z _D (32 in FIG. 8) is connected between the gate terminal G and the source terminal S, and a protection resistor R _P (33 in FIG. 8) is connected between the gate terminal G and the gate electrode. Connected. Note diode D _I is a substrate diode, is connected between the drain terminal D and the source terminal S.

Next, referring to FIG. 11 to FIG.
A method of manufacturing the OSFET protection device will be described in detail. M
An OSFET protection device includes a step of introducing one conductivity type impurity into a polysilicon layer provided on a semiconductor substrate, and a step of introducing a normal concentration of a reverse conductivity type impurity into the polysilicon layer selectively so as to be concentric. It comprises a step of forming a plurality of Zener diodes and a step of contacting the Zener diodes with metal electrodes.

FIG. 11 shows a step of introducing one conductivity type impurity into a polysilicon layer provided on a semiconductor substrate. On the gate oxide film 45 covering the channel layer 43 of the semiconductor substrate 41,
Deposit polysilicon. This polysilicon is in cell 3
6 are simultaneously deposited when they are buried in the trenches 44 (see FIG. 9). After that, the whole B ⁺ ion dose is 5 × 10 ¹⁴ cm.
P-type region 51 is formed by doping with ^-2 .

FIG. 12 shows a process of selectively introducing a normal concentration of a reverse conductivity type impurity into the polysilicon layer to form a plurality of zener diodes concentrically. POCL ₃ (phosphorous oxychloride) is selectively adhered to a region adjacent to the center of the polysilicon layer and the P-type region 51 so as to have a width of more than ten μm using a mask made of the resist film PR and diffused. An N ⁺ type region 53 is provided, and a Zener diode 3
Form 2 The width of this N ⁺ type region 53 is several μm.

FIG. 13 shows a step of contacting a Zener diode with a metal electrode. At the same time when the interlayer insulating film 50 (see FIG. 9) is formed, the BPS
A G film 39 is deposited, and contact holes are provided at the center and the outer periphery of the Zener diode 32.

Thereafter, aluminum is also sputtered on the Zener diode 32 when the source electrode 37 is formed, and unnecessary portions are removed to form the gate pad electrode 31 which contacts the center of the Zener diode 32. The outer peripheral portion of the Zener diode 32 is brought into contact with the source electrode 37.

[0028]

The conventional power M
In the OSFET, in order to prevent the gate oxide film from being damaged by static electricity, for example, when a voltage of 30 V is applied to the gate oxide film, the gate oxide film is protected by breakdown with a zener voltage of 15 V with a Zener diode. However, if the PN junction has a high concentration at the time of applying a reverse bias, the depletion layer is narrow, electrons easily tunnel, and a level at the tunnel destination is secured, so that leakage tends to occur. For example, MOSFET OF
Even at the time of F, the leakage current of the PN junction of the Zener diode is as large as about 0.5 μA, and power consumption in the Zener diode due to this leakage current has been a problem.

[0029]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has been made in consideration of the above-mentioned problems, and has been made in consideration of the above-mentioned problems. In the method, a low-concentration region is formed by forming a low-concentration region between the one-conductivity-type region and the reverse-conductivity-type region. An object of the present invention is to provide a Zener diode that expands a depletion layer at a junction and further reduces a leak current by eliminating a level at a tunnel destination of electrons.

A step of introducing an impurity of one conductivity type into a polysilicon layer provided on a semiconductor substrate; a step of selectively introducing a low-concentration impurity of a low conductivity type into the polysilicon layer; A step of selectively introducing a normal concentration of a reverse conductivity type impurity to form a plurality of concentrically stacked Zener diodes. An object of the present invention is to provide a method for manufacturing a MOSFET protection device for reducing current.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail with reference to FIGS.

FIG. 1 is a plan view of a power MOSFET according to the present invention. Power MOSFET is gate pad electrode 1
, A Zener diode 2, a resistor 3, a gate connection electrode 4, an actual operation area 5, and a source electrode 7.

The gate pad electrode 1 is provided on the Zener diode 2 and is in contact with the center of the Zener diode 2. Further, as shown by a dotted circle, the electrode is taken out by a bonding wire.

The Zener diode 2 is formed as shown by a concentric dotted line below the gate pad electrode 1 by introducing an impurity into the polysilicon, and the center is formed by the gate pad electrode 1.
And the outermost periphery is connected to the source electrode of each cell 6. The Zener diode 2 is provided to prevent a gate oxide film from being damaged by static electricity.

The resistor 3 is made of polysilicon and is a protection resistor for preventing electrostatic breakdown. One end is connected to the gate pad electrode 1 and the other end is connected to the gate connection electrode 4.
It is connected to the.

The gate connection electrode 4 is connected to the gate electrode of each cell 6 and is arranged around the actual operation area 5.

The actual operation area 5 includes a power MOSFE therein.
A large number of MOS transistor cells 6 constituting T are arranged.

The source electrode 7 is located on the actual operation area 5 in each cell 6.
Is provided in connection with the source region of. Further, as shown by a dotted circle, a bonding wire is thermally thickened to take out the electrode.

The shield electrode 8 contacts the annular ring below the shield electrode 8 to prevent the depletion layer from spreading to the end of the chip.

FIG. 2 is a sectional view of a MOSFET protection device according to the present invention. The same components as those shown in FIG. 1 are denoted by the same reference numerals. MOSFET protection device is semiconductor substrate 1
1, a trench 14 provided in the channel layer 13, a cell 6 of the trench MOSFET, a polysilicon layer provided on the semiconductor substrate 11, a one conductivity type region 21 provided in the polysilicon layer, and a low-concentration reverse conductivity type region. The protective device is composed of a plurality of concentrically stacked Zener diodes 2 each comprising a region 22 and a normal-concentration reverse conductivity type region 23.

The left side of FIG. 2 shows a sectional structure of the trench type cell 6.

The channel layer 13 is an N ⁺ type semiconductor substrate 11
A drain region 12 made of an N ^-- type epitaxial layer is provided on the substrate, and the surface thereof is formed by doping P-type ions.

The trench 14 is formed by etching the semiconductor substrate 11, penetrating the channel layer 13, and reaching the drain region 12.

In each cell 6, first, the inner wall of the trench 14 is coated with a gate oxide film 15, and after filling the trench 14 with polysilicon, impurities are introduced to reduce the resistance, and a gate electrode 16 is provided.

On the surface of the channel layer 13 adjacent to the trench 14, an N ⁺ type source region 18 is formed.
On the surface of the channel layer 13 between the source regions 18 of one cell, a P ⁺ type body contact region 19 is formed. Further, a trench 14 is formed in the channel layer 13 from the source region 18.
A channel region 17 is formed along.

A large number of such cells 6 are arranged in the actual operation area 5 of FIG. Specifically, one cell is represented by a small square.

The source electrode 7 is provided so as to cover the trench 14 with an interlayer insulating film 20 and to contact the source region 18 and the body contact region 19 by sputtering metal thereon.

FIG. 2 shows the cross-sectional structure of the Zener diode 2 of the present invention on the right side.

The Zener diode 2 includes a channel layer 13
On the gate oxide film 15 covering the gate electrode, using polysilicon deposited when the polysilicon is buried in the trench 14,
It is formed by alternately arranging regions into which P-type and N ⁺ -type ions are introduced. The PN junction adopts a concentric closed loop shape so that the junction end is not exposed to the polysilicon side surface.

The center of the Zener diode 2 is an N ⁺ type region 23, and a P type region 21 having a width of several tens μm and a
Of the N ⁻ -type region 22 and the N ⁺ -type region 23 having a width of several μm are formed concentrically and doubly.

Since the Zener voltage per PN junction is 6 to 7 V, a Zener voltage of 15 V can be guaranteed.
In an N-channel type power MOSFET in which the guaranteed value of the gate oxide film 15 is 10 V, the N ⁺ type region 2 is formed concentrically from the center.
3-N ^- type region 22-P-type region 21-N ^- type region 22-N
⁺ -Type region 23 -N ^-- type region 22 -P-type region 21 -N ^-- type region 22 -N ⁺ -type region 23.

The upper surface of the Zener diode 2 has a BPSG (B
oron PhosphorusSilicate G
The gate pad electrode 1 and the N ⁺ -type region 23 at the center of the Zener diode 2 are in contact with each other, and the outer periphery of the Zener diode 2 is in contact with the source electrode 7 of the MOSFET.

The feature of the present invention is that the Zener diode 2 has a P
That is, an N ⁻ -type region 22 in which a low concentration impurity is introduced is provided between the type region 21 and the N ⁺ -type region 23. By providing a region with a low impurity concentration, the depletion layer is expanded, and by lowering the Fermi level, a level at the tunnel destination of electrons is eliminated, thereby reducing leakage current.

FIG. 3 shows an equivalent circuit diagram of the power MOSFET according to the present invention. The equivalent circuit diagram of the present invention is the same as that of FIG. 10. According to this diagram, a Zener diode Z _D (reference numeral 2 in FIG. 1) is connected between a gate terminal G and a source terminal S,
A protective resistor R is provided between the gate terminal G and the gate electrode.
_P (3 in FIG. 1) is connected. Note diode D _I is a substrate diode, the drain terminal D and the source terminal S
Connected between them.

Next, referring to FIG. 4 to FIG.
A method for manufacturing the SFET protection device will be described in detail.

The MOSFET protection device comprises a step of introducing one conductivity type impurity into a polysilicon layer provided on a semiconductor substrate, and a step of selectively introducing a lower than normal concentration of a reverse conductivity type impurity into the polysilicon layer. Forming a plurality of zener diodes concentrically by introducing a normal concentration impurity of the opposite conductivity type selectively into the polysilicon layer, and contacting the zener diodes with metal electrodes. .

FIG. 4 shows a step of introducing one conductivity type impurity into a polysilicon layer provided on a semiconductor substrate. Polysilicon is deposited on gate oxide film 15 covering channel layer 13 of semiconductor substrate 11. This polysilicon is deposited simultaneously with embedding in the trench 14 of the cell 6 (see FIG. 2). Thereafter, B ⁺ ions are entirely doped at a dose of 5 × 10 ¹⁴ cm ⁻² to form a P-type region 21.

FIG. 5 shows a feature of the present invention, in which a step of selectively introducing a lower concentration of an impurity of the opposite conductivity type into the polysilicon layer is performed.

A mask of a resist film PR is applied so that the width of the P-type region 21 becomes tens of μm and on the predetermined N ⁺ -type region. An N ⁻ -type region 22 is formed by selectively introducing an N ⁻ -type impurity at a lower concentration than usual by ion implantation. The implantation condition at this time is a dose amount of 1 to 5 × 10 ¹⁴ cm ⁻² ,
The accelerating voltage is 50 KeV. The width of the N ⁻ type region 22 is several μm.
Becomes

FIG. 6 shows a process of forming a plurality of zener diodes concentrically by selectively introducing a normal concentration of an inversely driven impurity into the polysilicon layer. POCL ₃ (phosphorus oxychloride) is selectively adhered to the central portion of the polysilicon layer and the region adjacent to the N ⁻ type region 22 using a mask made of the resist film PR. Thereafter, the N ⁺ -type region 23 having a width of several μm is provided by diffusion, and the double Zener diode 2 is formed concentrically.

FIG. 7 shows a step of contacting a Zener diode with a metal electrode. Interlayer insulating film 20 (see FIG. 2)
The BPSG film 9 is formed on the Zener diode 2 at the time of formation.
And contact holes are provided at the center and the outer periphery of the Zener diode 2.

Thereafter, aluminum is sputtered on the Zener diode 2 when the source electrode 7 is formed, and unnecessary portions are removed to form the gate pad electrode 1 contacting the center of the Zener diode 2. Further, the outer peripheral portion of the Zener diode 2 is brought into contact with the source electrode 7.

The feature of the present invention is that the Zener diode 2 has a P
That is, an N ⁻ -type region 22 in which a low concentration impurity is introduced is provided between the type region 21 and the N ⁺ -type region 23. The depletion layer can be expanded and the Fermi level can be further reduced only by the step of ion implantation for providing a region with a low impurity concentration. This makes it difficult for electrons to tunnel, and furthermore, eliminates the level at the tunnel destination of the electrons to reduce the leak current.

[0064]

According to the present invention, first, the total leak current can be greatly reduced. By providing the N ⁻ -type region 22 having a low impurity concentration between the P-type region 21 and the N ⁺ -type region 23, the depletion layer is widened to make it difficult for electrons to tunnel. Further, when the impurity concentration is low, the Fermi level is lowered, so that the level at the tunnel destination of electrons cannot be formed.

Therefore, the leak current can be greatly reduced.

Second, since the size of the Zener diode 2 fits beneath the gate pad electrode 1, there is an advantage that the leak current can be reduced without reducing the conventional cell density.

According to the manufacturing method of the present invention, the leak current can be reduced without increasing the manufacturing cost, because the manufacturing method can be realized only by adding the N ⁻ type ion implantation step.

Thus, it is possible to provide a semiconductor device which greatly contributes to reduction of power consumption in the Zener diode 2 when the MOSFET is off.

[Brief description of the drawings]

FIG. 1 is a plan view illustrating a MOSFET protection device according to the present invention.

FIG. 2 is a cross-sectional view illustrating a MOSFET protection device according to the present invention.

FIG. 3 is a circuit diagram illustrating an equivalent circuit of a MOSFET protection device according to the present invention.

FIG. 4 is a cross-sectional view illustrating a method for manufacturing a MOSFET protection device according to the present invention.

FIG. 5 is a cross-sectional view illustrating a method for manufacturing a MOSFET protection device according to the present invention.

FIG. 6 is a cross-sectional view for explaining the method for manufacturing the MOSFET protection device of the present invention.

FIG. 7 is a cross-sectional view for explaining the method for manufacturing the MOSFET protection device of the present invention.

FIG. 8 is a plan view illustrating a conventional MOSFET protection device.

FIG. 9 is a cross-sectional view illustrating a conventional MOSFET protection device.

FIG. 10 is a circuit diagram illustrating an equivalent circuit of a conventional MOSFET protection device.

FIG. 11 is a cross-sectional view illustrating a method for manufacturing a conventional MOSFET protection device.

FIG. 12 is a cross-sectional view illustrating a method for manufacturing a conventional MOSFET protection device.

FIG. 13 is a cross-sectional view illustrating a method for manufacturing a conventional MOSFET protection device.

Claims (5)

[Claims] 1. A protection device for a MOSFET comprising a plurality of concentrically stacked Zener diodes comprising one conductivity type region and a reverse conductivity type region provided in a polysilicon layer, wherein said one conductivity type region and said opposite conductivity type region A device for protecting a MOSFET, wherein a reverse conductivity type region having a lower concentration than the reverse conductivity type region is interposed therebetween. 2. The MO according to claim 1, wherein said Zener diode is provided below a gate pad electrode.
SFET protection device. 3. The MOSFET protection device according to claim 2, wherein a central portion of the Zener diode is connected to an input terminal, and an outer peripheral portion is connected to a source electrode of the MOSFET. 4. A step of introducing one conductivity type impurity into a polysilicon layer provided on a semiconductor substrate; a step of selectively introducing a low-concentration opposite conductivity type impurity into said polysilicon layer; Forming a plurality of concentrically stacked Zener diodes by selectively introducing a normal concentration impurity of the opposite conductivity type into the MOS transistor.
Method for manufacturing FET protection device. 5. The MO according to claim 4, wherein the low concentration impurity of the opposite conductivity type is introduced by ion implantation.
A method for manufacturing an SFET protection device.