CN214279985U - MOSFET device with improved antistatic capability - Google Patents

Abstract

The utility model relates to an improve MOSFET device of antistatic ability, including the grid metal that is used for drawing forth the grid and the source metal that is used for drawing forth the source, grid metal and source intermetallic are provided with ESD protection structure, and ESD protection structure includes a plurality of ESD protection slot, and a plurality of ESD protection slot are arranged side by side around grid PAD district, and the grid is established ties and is had a plurality of grid resistance Rg, and grid resistance Rg includes the grid resistance slot, and a plurality of grid resistance slots set up in active area and terminal protection interval; the utility model discloses on the basis of current area ESD protective structure device, grid resistance Rg has established ties at the grid, when the grid received strong electrostatic impact, Rg resistance can make flow direction polycrystalline silicon diode return circuit, has effectively protected the thin bars oxygen structure of MOS for original conventional diode protection return circuit (PN junction pair) plays bigger guard action, thereby has improved the anti ESD ability limit of device, has improved the reliability of device.

Description

MOSFET device with improved antistatic capability

Technical Field

The utility model belongs to the technical field of power semiconductor device and specifically relates to a improve MOSFET device of antistatic ability and belong to power semiconductor device technical field.

Background

Power MOSFET devices play an important role in the modern electronics industry, and as the application range of devices expands, more and more people have higher requirements on the antistatic ability of the devices. According to the structure of the MOSFET, only a thin oxide layer is arranged between the grid electrode and the source electrode of the MOSFET for separation, the oxide layer is generally within 100nm, when the MOS device is not protected by a special structure, the ESD resistance of the MOS device is low, generally within 500V, and in a relatively dry environment, the ESD resistance is far lower than the static value generated by a common human body, so that the permanent damage of the device is easily caused.

In order to make MOSFET devices more antistatic, engineers have tried to find ways to seal the MOSFET and the protection device during device packaging, and even add ESD protection units to the peripheral circuits. This, while solving the problem, also increases the cost significantly.

Under the premise of ensuring the functions of the devices, the most common method at present is to improve the antistatic capability between the gate and the source of the MOSFET, that is, to manufacture the MOSFET device with ESD protection, the prior art method is to arrange several groups of back-to-back PN junction structures (at least one group) on the basis of the original MOSFET manufacturing process flow, and then connect the PN junction structures between the gate and the source of the power MOSFET device, and the schematic diagram is shown in fig. 1: the specific manufacturing method is that a PN junction of ESD (two groups of PN junction structures back to back in figure 1) is formed in a certain area of the MOSFET device through a series of steps of thermally growing a field oxide layer, depositing and etching a polysilicon pattern, ion implantation and the like. The planned region can be located in a gate region, a terminal region or other regions of the chip, and the shape can be changed according to the design. As shown in fig. 2, which is a top view of the MOSFET device, an ESD protection structure is disposed on the PAD area of the device gate, as shown in fig. 3: fig. 3 is a schematic cross-sectional view of a portion a-a' in fig. 2, where the portion a is connected to the gate metal through the contact hole and the portion B is connected to the source metal through the contact hole.

The manufacturing process of the conventional N-type groove power MOSFET device is as follows:

the first step is as follows: after pretreatment, photoetching and etching are carried out to form a groove (a photoetching plate 1 is used);

the second step is that: depositing and back-etching the grid polysilicon to form grid polysilicon in the groove;

the third step: depositing an oxide layer, and photoetching and etching (using the photoetching plate 2) to form a bearing structure for manufacturing an ESD structure;

the fourth step: ESD polycrystal deposition, injection, photoetching and etching (using a photoetching plate 3) so as to manufacture polysilicon for forming PN junctions;

the fifth step: selective implantation of ESD polysilicon to form ESD PN junctions (using reticle 4), which is typically formed in conjunction with the implantation of the source region in a conventional process;

and a sixth step: photoetching and etching a contact hole (a photoetching plate 5), wherein the layer is a conventional process;

the seventh step: the metal layer is photoetched and etched (reticle 6), and the layer is a conventional process.

The method needs 6 times of photoetching in the technical process, and has complex manufacturing process and higher cost.

SUMMERY OF THE UTILITY MODEL

The utility model aims at overcoming the not enough of existence in the current power MOSFET device technique, a improve MOSFET device of antistatic ability is provided, on the basis of taking ESD protective structure device structure now, a plurality of grid resistance Rg have been established ties at the grid, when the grid receives stronger electrostatic impact, there is grid resistance Rg between grid and the source electrode, more electric currents can flow to polycrystalline silicon diode group return circuit, the thin grid oxygen structure of MOS device has effectively been protected, thereby the anti ESD ability limit of device has been improved, the reliability of device has been improved.

In order to realize the technical purpose, the technical proposal of the utility model is that: the utility model provides an improve MOSFET device of antistatic ability, is including the grid metal that is used for drawing forth the grid and the source metal that is used for drawing forth the source, its characterized in that, be provided with ESD protection structure between grid metal and the source metal, ESD protection structure includes a plurality of ESD protection slot, a plurality of ESD protection slot arrange side by side around grid PAD district, the grid is established ties there is grid resistance Rg, grid resistance Rg includes a plurality of grid resistance slots, and a plurality of grid resistance slots set up between active area and terminal protection.

Further, on the cross section of the device, the ESD protection groove is arranged in the first conduction type drift region, and a first conduction type substrate is arranged below and adjacent to the first conduction type drift region; the ESD protection device is characterized in that a plurality of groups of serially-connected polycrystalline silicon diode groups are arranged in the ESD protection groove, a groove oxide layer is arranged on the inner wall of the ESD protection groove and wraps the polycrystalline silicon diode groups, the polycrystalline silicon diode groups comprise back-to-back diode groups formed by alternately arranging first conductive type polycrystalline silicon and second conductive type polycrystalline silicon, an insulating medium is arranged on the ESD protection groove, metal contact holes are formed in the insulating medium, and grid metal and source metal are in ohmic contact with two ends of the serially-connected polycrystalline silicon diode groups respectively through the metal contact holes.

Further, on the cross section of the device, the gate resistance groove is arranged in the first conduction type drift region, and a first conduction type substrate is arranged below and is adjacent to the first conduction type drift region; the gate resistor structure comprises a gate resistor groove and is characterized in that a gate oxide layer is arranged on the inner wall of the gate resistor groove, conductive polycrystalline silicon is arranged in the gate resistor groove, the gate oxide layer wraps the conductive polycrystalline silicon, an insulating medium is arranged on the gate resistor groove, a metal contact hole is formed in the insulating medium, and gate metal is in ohmic contact with the conductive polycrystalline silicon in the gate resistor groove through the metal contact hole.

Further, within the gate resistance trench, the conductive polysilicon includes first conductivity type polysilicon or second conductivity type polysilicon.

Compared with the prior art, the utility model has the advantages of it is following:

1) the utility model discloses set up ESD protection architecture between grid and source electrode, ESD protection architecture adopts the structure of ESD protection slot to set up around grid PAD district, set up the polycrystalline silicon diode group of multiunit series connection in ESD protection slot, (the utility model discloses polycrystalline silicon diode group includes two sets or more, and polycrystalline silicon diode group quantity is according to the withstand voltage limit Vgs of grid), when the device receives electrostatic shock, polycrystalline silicon diode group can be punctured earlier than the gate oxide of grid, releases the electrostatic current in the twinkling of an eye, thereby protects the device not to be damaged;

2) as shown in fig. 8, the gate of the present invention is connected in series with a gate resistor Rg, the gate resistor Rg adopts a structure of gate resistor grooves, and a plurality of gate resistor grooves are arranged between the active region and the terminal protection region, when the device gate is subjected to stronger electrostatic impact, because the gate has the gate resistor Rg, more current flows to the polysilicon diode group loop, the thin gate oxide layer of the MOS device is effectively protected, the ESD protection structure exerts a greater protection effect, and the ESD resistance limit of the device is improved;

3) the resistance value of the grid resistor Rg of the utility model can be flexibly adjusted through the ion concentration in the grid resistor groove, the number, the length, the width and the like of the grid resistor groove, and the ESD protection capability is obviously improved, thereby improving the reliability of the device;

under the Human Body Mode (HBM), when the grid resistance Rg value of the utility model is 300ohm, the antistatic capacity limit value of the MOS device is improved to more than 3500V from 2000V, and the improvement effect is obvious;

4) compared with the prior art manufacturing method, the utility model discloses a process manufacturing method only needs 4 layers of photolithography boards, and current process manufacturing method needs 6 layers of photolithography boards at least, the utility model discloses process manufacturing method has reduced the quantity of photolithography boards, has not only practiced thrift the cost, has simplified process manufacturing flow moreover.

Drawings

Fig. 1 is a circuit schematic of a prior art device with ESD protection structure.

Fig. 2 is a schematic diagram of a top view structure of a prior art device with ESD protection structure.

Fig. 3 is an enlarged structural diagram of the ESD protection region (S region) in fig. 2.

FIG. 4 is a schematic sectional view of A-A' in FIG. 3.

Fig. 5 is a schematic top view of embodiment 1 of the present invention.

Fig. 6 is a schematic top view of an ESD protection trench according to embodiment 1 of the present invention.

Fig. 7 is a schematic top view of a gate resistor trench according to embodiment 1 of the present invention.

Fig. 8 is a schematic circuit diagram of a device with ESD protection structure according to the present invention.

Fig. 9 is a schematic cross-sectional structure diagram of fig. 5B-B' in embodiment 1 of the present invention.

Fig. 10 is a schematic cross-sectional structure view of fig. 5C-C' in embodiment 1 of the present invention.

Fig. 11 is a schematic cross-sectional structure diagram of forming a semiconductor substrate in embodiment 1 of the present invention.

Fig. 12 is a schematic cross-sectional view of the ESD protection trench, the gate resistance trench, and the gate trench formed in embodiment 1 of the present invention.

Fig. 13 is a schematic cross-sectional view of the structure after etching the oxide layer and the polysilicon layer in embodiment 1 of the present invention.

Fig. 14 is a schematic cross-sectional view of a P-type well region and P-type polysilicon in a trench formed in embodiment 1 of the present invention.

Fig. 15 is a schematic cross-sectional view of a second hard mask window formed by photolithography in embodiment 1 of the present invention.

Fig. 16 is a schematic cross-sectional view of the N-type polysilicon in the N-type source region, the polysilicon diode group and the gate resistor trench formed in embodiment 1 of the present invention.

Fig. 17 is a schematic cross-sectional structure diagram of forming a metal contact hole and an insulating medium in embodiment 1 of the present invention.

Description of reference numerals: 100-an active region; 101-terminal protection area; 102-gate PAD region; a 1-N type substrate; a 2-N type drift region; 3-an ESD protection trench; 4-gate resistance trench; 5-a trench oxide layer; 6-polysilicon diode group; 7-an insulating medium; 8-metal contact holes; 9-source metal; 10-gate metal; 11-a gate oxide layer; 12-N type polycrystalline silicon; 13-P type well region; 14-N type source region; 15-a gate trench; 16-P type polysilicon; 17 — a first hard mask window; 18-a second hard mask window; 19-drain metal.

Detailed Description

The present invention will be further described with reference to the following specific embodiments.

In the following embodiment 1, an MOSFET device with improved anti-static capability takes an N-type trench gate MOSFET as an example, the first conductivity type is N-type, and the second conductivity type is P-type;

as shown in fig. 5, a MOSFET device with improved anti-static capability includes a gate metal 10 for leading out a gate and a source metal 9 for leading out a source, an ESD protection structure is disposed between the gate metal 10 and the source metal 9, the ESD protection structure includes a plurality of ESD protection trenches 3, the ESD protection trenches 3 are arranged in parallel around a gate PAD region 102, the gate is connected in series with a gate resistor Rg, the gate resistor Rg includes a plurality of gate resistor trenches 4, and the gate resistor trenches 4 are disposed between an active region 100 and a terminal protection region 101; the termination protection region 101 surrounds the active region 100, the gate PAD region 102 is disposed at any position of the active region 100, and the gate resistor Rg is disposed between the termination protection region 101 and the active region 100 in the form of a gate resistor trench 4;

as shown in fig. 6 and 9, the ESD protection trench 3 is disposed in the N-type drift region 2, and an N-type substrate 1 is disposed below and adjacent to the N-type drift region 2; a plurality of groups of polysilicon diode groups 6 connected in series are arranged in the ESD protection groove 3, a groove oxide layer 5 is arranged on the inner wall of the ESD protection groove 3, the groove oxide layer 5 wraps the polysilicon diode groups 6, the polysilicon diode groups 6 comprise back-to-back diode groups (namely N-P-N) formed by alternately arranging N-type polysilicon 12 and P-type polysilicon 16, an insulating medium 7 is arranged on the ESD protection groove 3, a metal contact hole 8 is arranged in the insulating medium 7, and the grid metal 10 and the source metal 9 are in ohmic contact with two ends of the polysilicon diode groups 6 connected in series respectively through the metal contact hole 8;

in embodiment 1 of the present invention, two sets of polysilicon diode groups 6 are included in the ESD protection trench 3, and the gate metal 10 and the source metal 9 are in ohmic contact with N-type polysilicon 12 at two ends of the polysilicon diode groups 6 connected in series respectively through the metal contact holes 8.

As shown in fig. 7, 9 and 10, the gate resistor Rg includes a gate resistor trench 4, the gate resistor trench 4 is disposed in the N-type drift region 2, and an N-type substrate 1 is disposed below and adjacent to the N-type drift region 2; a gate oxide layer 11 is arranged on the inner wall of the gate resistor groove 4, N-type polycrystalline silicon 12 is arranged in the gate resistor groove 4, the gate oxide layer 11 wraps the N-type polycrystalline silicon 12, an insulating medium 7 is arranged on the gate resistor groove 4, a metal contact hole 8 is arranged in the insulating medium 7, and the gate metal 10 is in ohmic contact with the N-type polycrystalline silicon 12 in the gate resistor groove 4 through the metal contact hole 8;

the utility model discloses the electrically conductive polycrystalline silicon in the grid resistance slot 4 can be N type polycrystalline silicon 12 or P type polycrystalline silicon 16, in the embodiment 1 of the utility model provides an electrically conductive polycrystalline silicon in the grid resistance slot 4 is N type polycrystalline silicon 12.

On the device cross-section, active area 100 includes the cell unit that a plurality of mutual parallel arrangement, the cell unit is including being located P type well region 13 in the N type drift region 2, being located N type source region 14 in the P type well region 13, be located the grid slot 15 between P type well region 13, the inner wall of grid slot 15 is equipped with gate oxide 11, be equipped with N type polycrystalline silicon 12 in the grid slot 15, gate oxide 11 parcel N type polycrystalline silicon 12, the last insulating medium 7 that covers of grid slot 15, be equipped with metal contact hole 8 in the insulating medium 7, source electrode metal 9 passes through metal contact hole 8 respectively with P type well region 13, 14 ohmic contact in N type source region.

The terminal protection area 101 includes a voltage division protection area and a cut-off area, the cut-off area is located at an outer ring of the terminal protection area 101, and the structures of the voltage division protection area and the cut-off area are well known to those skilled in the art and are not described herein again;

the method for manufacturing the MOSFET device with improved anti-static capability in embodiment 1 includes the following steps:

as shown in fig. 11, a, providing a semiconductor substrate, where the semiconductor substrate includes an N-type drift region 2 and an N-type substrate 1 located below the N-type drift region 2, an upper surface of the N-type drift region 2 is a first main surface 001 of the semiconductor substrate, and a lower surface of the N-type substrate 1 is a second main surface 002 of the semiconductor substrate;

as shown in fig. 12, b, depositing a hard mask layer on the first main surface 001 of the semiconductor substrate, and selectively etching the hard mask layer to obtain a patterned first hard mask window 17;

c. etching the first main surface 001 under the masking of the first hard mask window 17 to obtain a plurality of gate trenches 15 uniformly distributed in parallel in the active region 100, ESD protection trenches 3 distributed in parallel around the gate PAD region 102, and a plurality of gate resistance trenches 4 between the active region 100 and the terminal protection region 101;

as shown in fig. 13, d, growing an oxide layer and depositing polysilicon on the first main surface 001 of the semiconductor substrate, and etching the polysilicon and the oxide layer in sequence, wherein only the oxide layer and the polysilicon in the gate trench 15, the ESD protection trench 3, and the gate resistance trench 4 remain;

here, the polysilicon in the gate trench 15, the ESD protection trench 3, and the gate resistance trench 4 is undoped polysilicon;

as shown in fig. 14, e, implanting P-type ions into the first main surface 001 of the semiconductor substrate, and annealing to obtain a P-type well region 13 located in the active region 100, a trench oxide layer 5 and P-type polysilicon 16 located in the ESD protection trench 3, and a gate oxide layer 11 and P-type polysilicon 16 located in the gate resistance trench 4;

here, the P-type ions are implanted as normal, and the gate resistance trench 4 and the gate trench 15 are also implanted with P-type ions;

as shown in fig. 15, f, depositing a hard mask layer on the first main surface 001 of the semiconductor substrate, and selectively etching the hard mask layer to obtain a patterned second hard mask window 18;

as shown in fig. 16, g, under the masking of the patterned second hard mask window 18, selectively implanting N-type ions, and annealing to obtain an N-type source region 14 located in the P-type well region 13, a gate oxide layer 11 and conductive polysilicon located in the gate resistance trench 4, a trench oxide layer 5 and N-type polysilicon 12 located in the ESD protection trench 3;

here, the implantation concentration of the P-type ions in the step e is far less than that of the N-type ions in the step g; in step g, N-type ions are selectively implanted, if N-type ions are implanted into the gate resistor trench 4, the P-type polysilicon 16 in the gate resistor trench 4 is inverted into N-type polysilicon 12, and if N-type ions are not implanted into the gate resistor trench 4, the conductive polysilicon in the gate resistor trench 4 is still P-type polysilicon 16;

in embodiment 1 of the present invention, N-type ions are injected into the gate resistor trench 4, so that the conductive polysilicon in the gate resistor trench 4 is N-type polysilicon 12;

at this time, the N-type polysilicon 12 and the P-type polysilicon 16 in the ESD protection trench 3 are alternately arranged to form a polysilicon diode group 6;

in embodiment 1 of the present invention, the N-type polysilicon 12 and the P-type polysilicon 16 in the ESD protection trench 3 are alternately arranged to form two polysilicon diode groups 6;

as shown in fig. 17, h, depositing an insulating medium 7 on the first main surface 001 of the semiconductor substrate, and etching the insulating medium 7 to obtain a plurality of metal contact holes 8;

as shown in fig. 5, i, depositing metal in the metal contact hole 8 and on the insulating medium 7, and etching the metal to obtain a source metal 9 and a gate metal 10;

in the active region 001, the source metal 9 is in ohmic contact with the P-type well region 13 and the N-type source region 14 respectively; in the gate resistance trench 4, the gate metal 10 is in ohmic contact with N-type polysilicon 12;

in embodiment 1 of the present invention, the gate metal 10 and the source metal 9 are in ohmic contact with the N-type polysilicon 12 at two ends of the two polysilicon diode groups 6, respectively;

j. thinning the semiconductor second main surface 002, depositing metal to obtain drain metal 19 positioned on the lower surface of the N-type substrate 1, wherein the drain metal 19 is in ohmic contact with the lower surface of the N-type substrate 1.

The N-type polysilicon 12 and the P-type polysilicon 16 in the ESD protection groove 3 are alternately arranged to form a polysilicon diode group 6 in which a plurality of groups are connected in series, in embodiment 1 of the present invention, the ESD protection groove 3 contains two polysilicon diode groups 6.

As shown in fig. 8, the gate of the present invention is connected in series with a gate resistor Rg, the gate resistor Rg adopts a structure of a gate resistor groove 4, and a plurality of gate resistor grooves 4 are arranged between the active region 100 and the terminal protection region 101, when the device gate is subjected to stronger electrostatic impact, because the gate has the gate resistor Rg, more current flows to the polysilicon diode group 6 loop, the thin gate oxide layer of the MOS device is effectively protected, the ESD protection structure exerts a greater protection effect, and the ESD resistance limit of the whole device is improved; the resistance value of the grid resistor Rg in the utility model can be flexibly adjusted through the ion concentration in the grid resistor groove 4, the number, the length, the width and the like of the grid resistor groove 4, and the ESD protection capability is obviously improved; under the Human Body Mode (HBM), when the gate resistance Rg value is 300ohm, the antistatic capacity limit value of the MOS device is improved to more than 3500V from 2000V, and the improvement effect is obvious.

Compared with the prior art manufacturing method, the utility model discloses a process manufacturing method only needs 4 layers of photolithography mask (photolithography mask 1: be used for etching grid slot 15, ESD protection slot 3, grid resistance slot 4; photolithography mask 2: be used for selectively pouring into N type ion, photolithography mask 3: be used for etching metal contact 8, photolithography mask 4: be used for etching the metal level), and current process manufacturing method needs 6 layers of photolithography masks at least, the utility model discloses process manufacturing method has reduced the quantity of photolithography mask, has not only practiced thrift the cost, has simplified process manufacturing flow moreover.

The present invention and the embodiments thereof have been described above, but the description is not limited thereto, and what is shown in the drawings is only one of the embodiments of the present invention, and the actual structure is not limited thereto. In summary, those skilled in the art should understand that they should not be limited to the embodiments described above, and that they can design the similar structure and embodiments without departing from the spirit of the invention.

Claims (4)

1. The utility model provides an improve MOSFET device of antistatic ability, is including the grid metal that is used for drawing forth the grid and the source metal that is used for drawing forth the source, its characterized in that, be provided with ESD protection structure between grid metal and the source metal, ESD protection structure includes a plurality of ESD protection slot, a plurality of ESD protection slot arrange side by side around grid PAD district, the grid is established ties there is grid resistance Rg, grid resistance Rg includes a plurality of grid resistance slots, and a plurality of grid resistance slots set up between active area and terminal protection.

2. The MOSFET device of claim 1, wherein: on the cross section of the device, the ESD protection groove is arranged in a first conduction type drift region, and a first conduction type substrate is arranged below and adjacent to the first conduction type drift region; the ESD protection device is characterized in that a plurality of groups of serially-connected polycrystalline silicon diode groups are arranged in the ESD protection groove, a groove oxide layer is arranged on the inner wall of the ESD protection groove and wraps the polycrystalline silicon diode groups, the polycrystalline silicon diode groups comprise back-to-back diode groups formed by alternately arranging first conductive type polycrystalline silicon and second conductive type polycrystalline silicon, an insulating medium is arranged on the ESD protection groove, metal contact holes are formed in the insulating medium, and grid metal and source metal are in ohmic contact with two ends of the serially-connected polycrystalline silicon diode groups respectively through the metal contact holes.

3. The MOSFET device of claim 1, wherein: on the cross section of the device, the gate resistance groove is arranged in a first conduction type drift region, and a first conduction type substrate is arranged below and is adjacent to the first conduction type drift region; the gate resistor structure is characterized in that a gate oxide layer is arranged on the inner wall of the gate resistor groove, conductive polycrystalline silicon is arranged in the gate resistor groove, the gate oxide layer wraps the conductive polycrystalline silicon, an insulating medium covers the gate resistor groove, a metal contact hole is formed in the insulating medium, and gate metal is in ohmic contact with the conductive polycrystalline silicon in the gate resistor groove through the metal contact hole.

4. A MOSFET device with improved electrostatic discharge protection as claimed in claim 3, wherein: within the gate resistance trench, the conductive polysilicon includes first conductivity type polysilicon or second conductivity type polysilicon.

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