JP2002009285A - Protection device of mosfet - Google Patents
Protection device of mosfetInfo
- Publication number
- JP2002009285A JP2002009285A JP2000190794A JP2000190794A JP2002009285A JP 2002009285 A JP2002009285 A JP 2002009285A JP 2000190794 A JP2000190794 A JP 2000190794A JP 2000190794 A JP2000190794 A JP 2000190794A JP 2002009285 A JP2002009285 A JP 2002009285A
- Authority
- JP
- Japan
- Prior art keywords
- zener diode
- mosfet
- protection device
- type region
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 16
- 229920005591 polysilicon Polymers 0.000 claims description 16
- 230000002093 peripheral effect Effects 0.000 claims 1
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 19
- 108091006146 Channels Proteins 0.000 description 14
- 239000000758 substrate Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- HBBGRARXTFLTSG-UHFFFAOYSA-N Lithium ion Chemical compound [Li+] HBBGRARXTFLTSG-UHFFFAOYSA-N 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 229910001416 lithium ion Inorganic materials 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 230000005611 electricity Effects 0.000 description 4
- 230000003068 static effect Effects 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 239000008186 active pharmaceutical agent Substances 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7808—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a breakdown diode, e.g. Zener diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明はＭＯＳＦＥＴの保護
装置に係り、特にトレンチ構造を有する縦型ＭＯＳＦＥ
Ｔの保護装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a protection device for a MOSFET, and more particularly to a vertical MOSFET having a trench structure.
T protection device.
【０００２】[0002]
【従来の技術】携帯端末の普及に伴い小型で大容量のリ
チュウムイオン電池が求められるようになってきた。こ
のリチュウムイオン電池の充放電のバッテリーマネージ
メントを行う保護回路は携帯端末の軽量化のニーズによ
り、より小型で負荷ショートにも十分に耐えうるもので
なくてはならない。かかる保護回路はリチュウムイオン
電池の容器内に内蔵されるために小型化が求められ、チ
ップ部品を多用したＣＯＢ(Ｃｈｉｐ ｏｎ Ｂｏａｒ
ｄ)技術が駆使され、小型化の要求に応えてきた。しか
し一方ではリチュウムイオン電池に直列にパワーＭＯＳ
ＦＥＴを接続するのでこのパワーＭＯＳＦＥＴのオン抵
抗も極めて小さくするニーズがあり、これが携帯電話で
は通話時間や待機時間を長くするために不可欠の要素で
ある。2. Description of the Related Art With the spread of portable terminals, a small-sized and large-capacity lithium-ion battery has been required. The protection circuit for performing the battery management of the charging and discharging of the lithium ion battery must be smaller and capable of sufficiently withstanding a load short due to the need for reducing the weight of the portable terminal. Such a protection circuit is required to be miniaturized because it is built in a container of a lithium ion battery, and a COB (Chip on Boar) using a lot of chip components is required.
d) Technology has been used to meet the demand for miniaturization. However, on the other hand, a power MOS in series with a lithium ion battery
Since the FET is connected, there is a need to make the on-resistance of the power MOSFET extremely small, which is an indispensable factor for a mobile phone in order to increase the talk time and the standby time.
【０００３】特に保護回路ではリチュウムイオン電池Ｌ
ｉＢに直列に２個のＮチャンネル型のパワーＭＯＳＦＥ
Ｔが接続されるので、この２個のパワーＭＯＳＦＥＴの
低オン抵抗(ＲDS(on))が最も要求される項目である。こ
のためにチップを製造する上で微細加工によりセル密度
を上げる開発が進められてきた。In particular, in the protection circuit, a lithium ion battery L
Two N-channel power MOSFETs in series with iB
Since T is connected, the low on-resistance (R DS (on) ) of these two power MOSFETs is the most required item. For this reason, development for increasing the cell density by fine processing in manufacturing chips has been promoted.
【０００４】一方、パワーＭＯＳＦＥＴでは薄いゲート
酸化膜を静電破壊から保護するために保護用の抵抗体が
ゲート電極に挿入され更に静電気を外部に逃がすために
ゲート電極とソース電極間にツェナーダイオードが接続
されている。On the other hand, in a power MOSFET, a protection resistor is inserted into a gate electrode to protect a thin gate oxide film from electrostatic breakdown, and a Zener diode is provided between the gate electrode and a source electrode to release static electricity to the outside. It is connected.
【０００５】図４に従来のパワーＭＯＳＦＥＴの平面図
を示す。パワーＭＯＳＦＥＴはゲートパッド電極３１と
ツェナーダイオード３２とゲート連結電極３４と実動作
領域３５とソース電極３７とで構成される。FIG. 4 is a plan view of a conventional power MOSFET. The power MOSFET includes a gate pad electrode 31, a Zener diode 32, a gate connection electrode 34, an actual operation area 35, and a source electrode 37.
【０００６】ゲートパッド電極３１はツェナーダイオー
ド３２上に設けられ、ツェナーダイオード３２の中心部
分とコンタクトしている。また、点線の丸印で示すよう
にボンディングワイヤーで電極の取り出しが行われる。The gate pad electrode 31 is provided on the Zener diode 32 and is in contact with the central portion of the Zener diode 32. Further, as shown by a dotted circle, the electrode is taken out by a bonding wire.
【０００７】ツェナーダイオード３２はポリシリコンに
不純物を導入して、ゲートパッド電極３１の下に同心円
の点線で示すように形成され、中心部はゲートパッド電
極３１とコンタクトし、最外周は各セル３６のソース電
極と連結される。このツェナーダイオード３２は、静電
気によるゲート酸化膜の破壊を防止するために設けられ
る。The Zener diode 32 is formed by introducing impurities into the polysilicon and is formed below the gate pad electrode 31 as shown by a concentric dotted line, the center portion is in contact with the gate pad electrode 31, and the outermost periphery is each cell 36. Is connected to the source electrode of The Zener diode 32 is provided to prevent the gate oxide film from being broken by static electricity.
【０００８】抵抗体３３はポリシリコンで形成され、静
電破壊を防止するための保護用の抵抗体であり、一端を
ゲートパッド電極３１に接続され、他端はゲート連結電
極３４に接続されている。The resistor 33 is formed of polysilicon and is a protective resistor for preventing electrostatic breakdown. One end is connected to the gate pad electrode 31 and the other end is connected to the gate connection electrode 34. I have.
【０００９】ゲート連結電極３４は各セル３６のゲート
電極と接続され且つ実動作領域３５の周囲に配置されて
いる。The gate connection electrode 34 is connected to the gate electrode of each cell 36 and is disposed around the actual operation area 35.
【００１０】実動作領域３５はこの中にパワーＭＯＳＦ
ＥＴを構成する多数のＭＯＳトランジスタのセル３６が
配列されている。The actual operation area 35 includes a power MOSF therein.
A large number of MOS transistor cells 36 constituting the ET are arranged.
【００１１】ソース電極３７は実動作領域３５上に各セ
ル３６のソース領域と接続して設けられる。また、点線
の丸印で示すようにボンディングワイヤが熱厚着され、
電極の取り出しを行う。The source electrode 37 is provided on the actual operation area 35 so as to be connected to the source area of each cell 36. Also, as shown by the dotted circles, the bonding wires are thermally thickened,
Take out the electrode.
【００１２】シールド電極３８はその下のアニュラーリ
ングとコンタクトして、チップ終端への空乏層の拡がり
を抑える。The shield electrode 38 contacts the annular ring below the shield electrode 38 to prevent the depletion layer from spreading to the end of the chip.
【００１３】図５の左側に、トレンチ型の各セル３６の
断面構造を示す。ＮチャンネルのパワーＭＯＳＦＥＴに
おいては、Ｎ+型の半導体基板４１の上にＮ-型のエピタ
キシャル層からなるドレイン領域４２を設け、その上に
Ｐ型のチャネル層４３を設ける。チャネル層４３からド
レイン領域４２まで到達するトレンチ４４を作り、トレ
ンチ４４の内壁をゲート酸化膜４５で被膜し、トレンチ
４４に充填されたポリシリコンよりなるゲート電極４６
を設けて各セル３６を形成する。The cross-sectional structure of each trench-type cell 36 is shown on the left side of FIG. In the N-channel power MOSFET, a drain region 42 made of an N − -type epitaxial layer is provided on an N + -type semiconductor substrate 41, and a P-type channel layer 43 is provided thereon. A trench 44 extending from the channel layer 43 to the drain region 42 is formed, an inner wall of the trench 44 is coated with a gate oxide film 45, and a gate electrode 46 made of polysilicon filled in the trench 44 is formed.
Are provided to form each cell 36.
【００１４】トレンチ４４に隣接したチャネル層４３表
面にはＮ+型のソース領域４８が形成され、隣り合う２
つのセルのソース領域４８間のチャネル層４３表面には
Ｐ+型のボディコンタクト領域４９が形成される。On the surface of the channel layer 43 adjacent to the trench 44, an N + type source region 48 is formed.
A P + type body contact region 49 is formed on the surface of channel layer 43 between source regions 48 of one cell.
【００１５】さらにチャネル層４３にはソース領域４８
からトレンチ４４に沿ってチャネル領域４７が形成され
る。トレンチ４４上は層間絶縁膜５０で覆い、ソース領
域４８およびボディコンタクト領域４９にコンタクトす
るソース電極３７を設ける。Further, a source region 48 is provided in the channel layer 43.
Then, a channel region 47 is formed along the trench 44. The trench 44 is covered with an interlayer insulating film 50, and a source electrode 37 that contacts the source region 48 and the body contact region 49 is provided.
【００１６】かかるセル３６は図４の実動作領域５に多
数個配列される。具体的には小さい四角で表示したもの
が１個のセルである。A large number of such cells 36 are arranged in the actual operation area 5 of FIG. Specifically, one cell is represented by a small square.
【００１７】図５の右側にツェナーダイオード３２の断
面構造を示す。チャネル層４３を覆うゲート酸化膜４５
上にトレンチ４４にポリシリコンを埋め込む時に堆積さ
れたポリシリコンを用いて、Ｐ型とＮ+型のイオンを交
互に配置して形成される。The cross-sectional structure of the Zener diode 32 is shown on the right side of FIG. Gate oxide film 45 covering channel layer 43
P-type and N + -type ions are alternately arranged using polysilicon deposited when polysilicon is buried in trench 44 above.
【００１８】このＰＮ接合は、その接合端をポリシリコ
ン側面に露出しないように同心円状に閉ループの形状を
採用する。つまり最初にＢ+イオンをドーズ量５×1014c
m-2でドープしてＰ型領域５１を形成し、その後ソース
領域４８のイオン注入時に選択的にPOCL3を付着して拡
散（950℃、180分）し、Ｎ+型領域５２を形成する。The PN junction adopts a concentric closed loop shape so that the junction end is not exposed to the side surface of the polysilicon. That is, first, the dose of B + ions is 5 × 10 14 c
P-type region 51 is formed by doping with m −2 , and then POCL 3 is selectively adhered and diffused (950 ° C., 180 minutes) during ion implantation of source region 48 to form N + -type region 52. .
【００１９】このツェナーダイオード３２は中心のＮ+
型領域５２の直径が136μｍ、Ｐ型領域５１の幅が15μ
ｍになり、ＰＮ接合が同心円状に２重に形成される。ま
た、１つのＰＮ接合あたりのツェナー電圧が６〜７Ｖな
ので１５Ｖのツェナー電圧を保証できる。This zener diode 32 has a central N +
The diameter of the mold region 52 is 136 μm, and the width of the P-type region 51 is 15 μm.
m, and the PN junction is formed concentrically and doubly. Further, since the Zener voltage per PN junction is 6 to 7 V, a Zener voltage of 15 V can be guaranteed.
【００２０】すなわち、ゲート酸化膜４５の保証値が１
０Ｖ系のＮチャネル型パワーＭＯＳＦＥＴでは、中心か
ら同心円状にＮ+型領域５２−Ｐ型領域５１−Ｎ+型領域
５２−Ｐ型領域５１−Ｎ+型領域５２となる。That is, the guaranteed value of the gate oxide film 45 is 1
In the 0V N-channel type power MOSFET, the N + -type region 52 -P-type region 51 -N + -type region 52 -P-type region 51 -N + -type region 52 are concentrically arranged from the center.
【００２１】さらにそのポリシリコン上面はＢＰＳＧ
（Ｂｏｒｏｎ ＰｈｏｓｐｈｏｒｕｓＳｉｌｉｃａｔｅ
Ｇｌａｓｓ）膜３９で覆われ、ゲートパット電極３１
とツェナーダイオード３２の中心部のＮ+型領域５２が
コンタクトし、ツェナーダイオード３２の外周部はＭＯ
ＳＦＥＴのソース電極３７にコンタクトしている。Further, the polysilicon upper surface is BPSG
(Boron PhosphorusSilicate
Glass) film 39 and the gate pad electrode 31
And the N + -type region 52 at the center of the Zener diode 32 is in contact with the outer periphery of the Zener diode 32.
It is in contact with the source electrode 37 of the SFET.
【００２２】図６にかかるパワーＭＯＳＦＥＴの等価回
路図を示す。図６では、ゲート端子Ｇとソース端子Ｓ間
にツェナーダイオードＺD（図４ 符号３２）が接続さ
れ、ゲート端子Ｇとゲート電極間には保護用の抵抗体Ｒ
P（図４ 符号３３）が接続される。なおダイオードＤI
は基板ダイオードであり、ドレイン端子Ｄとソース端子
Ｓ間に接続される。FIG. 6 shows an equivalent circuit diagram of the power MOSFET. In FIG. 6, a Zener diode Z D (reference numeral 32 in FIG. 4) is connected between the gate terminal G and the source terminal S, and a protection resistor R is provided between the gate terminal G and the gate electrode.
P (33 in FIG. 4) is connected. The diode D I
Is a substrate diode, which is connected between the drain terminal D and the source terminal S.
【００２３】[0023]
【発明が解決しようとする課題】かかる従来のパワーＭ
ＯＳＦＥＴでは静電気によるゲート酸化膜の破壊を防止
するために、例えばゲート酸化膜に３０Ｖの電圧がかか
る場合にはツェナーダイオードで１５Ｖのツェナー電圧
で降伏させて保護している。しかし、ＭＯＳＦＥＴのＯ
ＦＦ時でも、ツェナーダイオードのＰＮ接合のリーク電
流が約0.5μＡと大きく、このリーク電流によるツェナ
ーダイオードでの電力消費が問題となっていた。The conventional power M
In the OSFET, in order to prevent the gate oxide film from being damaged by static electricity, for example, when a voltage of 30 V is applied to the gate oxide film, the gate oxide film is protected by breakdown with a zener voltage of 15 V with a Zener diode. However, MOSFET O
Even at the time of FF, the leakage current of the PN junction of the Zener diode is as large as about 0.5 μA, and power consumption in the Zener diode due to the leakage current has been a problem.
【００２４】[0024]
【課題を解決するための手段】本発明はかかる課題に鑑
みてなされ、ポリシリコン層に設けた一導電型領域およ
び逆導電型領域からなるツェナーダイオードを同心状に
複数個重ねたＭＯＳＦＥＴの保護装置において、前記ツ
ェナーダイオードの中心部の一導電型領域の面積を縮小
し、接合面積を縮小することを特徴とするもので、電流
はその経路の面積に比例することから、ツェナーダイオ
ードのＰＮ接合の面積を縮小することによりリーク電流
を低減できるツェナーダイオードを保護装置として有す
るパワーＭＯＳＦＥＴを提供するものである。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has been made in consideration of the above-mentioned problems, and has been made in consideration of the above-mentioned problems. Wherein the area of one conductivity type region at the center of the Zener diode is reduced, and the junction area is reduced. Since the current is proportional to the area of the path, the PN junction of the Zener diode is reduced. An object of the present invention is to provide a power MOSFET having a Zener diode capable of reducing a leak current by reducing an area as a protection device.
【００２５】[0025]
【発明の実施の形態】本発明の実施の形態を図１から図
３を参照して詳細に説明する。図１に本発明のパワーＭ
ＯＳＦＥＴの平面図を示す。パワーＭＯＳＦＥＴはゲー
トパッド電極１と、ツェナーダイオード２と、抵抗体３
と、ゲート連結電極４と実動作領域５とソース電極７と
で構成される。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail with reference to FIGS. FIG. 1 shows the power M of the present invention.
1 shows a plan view of an OSFET. The power MOSFET has a gate pad electrode 1, a Zener diode 2, a resistor 3
, A gate connection electrode 4, an actual operation region 5, and a source electrode 7.
【００２６】ゲートパッド電極１はツェナーダイオード
２上に設けられ、ツェナーダイオード２の中心部分とコ
ンタクトしている。また、点線の丸印で示すようにボン
ディングワイヤーで電極の取り出しが行われる。The gate pad electrode 1 is provided on the Zener diode 2 and is in contact with the center of the Zener diode 2. Further, as shown by a dotted circle, the electrode is taken out by a bonding wire.
【００２７】ツェナーダイオード２はポリシリコンに不
純物を導入して、ゲートパッド電極１の下に同心円の点
線で示すように形成され、中心部はゲートパッド電極１
とコンタクトし、最外周は各セル６のソース電極と連結
される。このツェナーダイオード２は、静電気によるゲ
ート酸化膜の破壊を防止するために設けられる。The Zener diode 2 is formed by introducing impurities into the polysilicon, and is formed below the gate pad electrode 1 as shown by a concentric dotted line.
And the outermost periphery is connected to the source electrode of each cell 6. The Zener diode 2 is provided to prevent a gate oxide film from being damaged by static electricity.
【００２８】抵抗体３はポリシリコンで形成され、静電
破壊を防止するための保護用の抵抗体であり、一端をゲ
ートパッド電極１に接続され、他端はゲート連結電極４
に接続されている。The resistor 3 is made of polysilicon and is a protection resistor for preventing electrostatic breakdown. One end is connected to the gate pad electrode 1 and the other end is connected to the gate connection electrode 4.
It is connected to the.
【００２９】ゲート連結電極４は各セル６のゲート電極
と接続され且つ実動作領域５の周囲に配置されている。The gate connection electrode 4 is connected to the gate electrode of each cell 6 and is arranged around the actual operation area 5.
【００３０】実動作領域５はこの中にパワーＭＯＳＦＥ
Ｔを構成する多数のＭＯＳトランジスタのセル６が配列
されている。The actual operation area 5 includes a power MOSFE therein.
A large number of MOS transistor cells 6 constituting T are arranged.
【００３１】ソース電極７は実動作領域５上に各セル６
のソース領域と接続して設けられる。また、点線の丸印
で示すようにボンディングワイヤが熱厚着され、電極の
取り出しを行う。The source electrode 7 is disposed on the actual operation area 5 in each cell 6.
Is provided in connection with the source region of. Further, as shown by a dotted circle, a bonding wire is thermally thickened to take out the electrode.
【００３２】シールド電極８はその下のアニュラーリン
グとコンタクトして、チップ終端への空乏層の拡がりを
抑える。The shield electrode 8 contacts the annular ring below the shield electrode 8 to prevent the depletion layer from spreading to the chip end.
【００３３】図２に本発明のＭＯＳＦＥＴの保護装置の
断面図を示す。尚、図１に示すものと同一構成要素は同
一符号とする。ＭＯＳＦＥＴの保護装置は半導体基板１
１上のチャネル層１３に設けたトレンチ１４とトレンチ
１４内に形成したトレンチ型のＭＯＳＦＥＴのセル６と
半導体基板１１上に設けたポリシリコン層とポリシリコ
ン層に設けた一導電型領域２１および逆導電型領域２２
からなるツェナーダイオード２を同心円状に複数個重ね
た保護装置から構成される。FIG. 2 is a sectional view of a MOSFET protection device according to the present invention. The same components as those shown in FIG. 1 are denoted by the same reference numerals. MOSFET protection device is semiconductor substrate 1
1, a trench 14 provided in the channel layer 13, a trench-type MOSFET cell 6 formed in the trench 14, a polysilicon layer provided on the semiconductor substrate 11, a one conductivity type region 21 provided in the polysilicon layer, and the reverse. Conductive region 22
And a protective device in which a plurality of zener diodes 2 are concentrically stacked.
【００３４】図２の左側はトレンチ型のセル６の断面構
造を示す。The left side of FIG. 2 shows a sectional structure of the trench type cell 6.
【００３５】チャネル層１３はＮ+型の半導体基板１１
の上にＮ-型のエピタキシャル層からなるドレイン領域
１２を設け、その表面にＰ型のイオンをドープして形成
する。The channel layer 13 is an N + type semiconductor substrate 11
A drain region 12 made of an N -- type epitaxial layer is provided on the substrate, and the surface thereof is formed by doping P-type ions.
【００３６】トレンチ１４は、半導体基板１１をエッチ
ングし、チャネル層１３を貫通し、ドレイン領域１２ま
で到達させる。The trench 14 is formed by etching the semiconductor substrate 11, penetrating the channel layer 13, and reaching the drain region 12.
【００３７】各セル６は、トレンチ１４の内壁をゲート
酸化膜１５で被膜し、トレンチ１４にポリシリコンを充
填後、不純物を導入して低抵抗化を図り、ゲート電極１
６を設けて形成する。トレンチ１４に隣接したチャネル
層１３表面にはＮ+型のソース領域１８が形成され、隣
り合う２つのセルのソース領域１８間のチャネル層１３
表面にはＰ+型のボディコンタクト領域１９が形成され
る。さらにチャネル層１３にはソース領域１８からトレ
ンチ１４に沿ってチャネル領域１７が形成される。In each of the cells 6, the inner wall of the trench 14 is coated with a gate oxide film 15, and after filling the trench 14 with polysilicon, impurities are introduced to reduce the resistance.
6 is formed. An N + type source region 18 is formed on the surface of the channel layer 13 adjacent to the trench 14, and the channel layer 13 between the source regions 18 of two adjacent cells is formed.
A P + type body contact region 19 is formed on the surface. Further, a channel region 17 is formed in the channel layer 13 from the source region 18 along the trench 14.
【００３８】かかるセル６は図１の実動作領域５に多数
個配列される。具体的には小さい四角で表示したものが
１個のセルである。A large number of such cells 6 are arranged in the actual operation area 5 of FIG. Specifically, one cell is represented by a small square.
【００３９】ソース電極７は、トレンチ１４上を層間絶
縁膜２０で覆い、その上にソース領域１８およびボディ
コンタクト領域１９にコンタクトするように設ける。The source electrode 7 is provided so as to cover the trench 14 with an interlayer insulating film 20 and to contact the source region 18 and the body contact region 19 thereon.
【００４０】図２の右側に本発明のツェナーダイオード
２の断面構造を示す。FIG. 2 shows the cross-sectional structure of the Zener diode 2 of the present invention on the right side.
【００４１】ツェナーダイオード２は、チャネル層１３
を覆うゲート酸化膜１５上に、トレンチ１４にポリシリ
コンを埋め込む時に堆積されたポリシリコンを用いて、
Ｐ型とＮ+型のイオンを交互に配置して形成される。こ
のＰＮ接合は、その接合端をポリシリコン側面に露出し
ないように同心円状に閉ループの形状を採用する。さら
にＰＮ接合の面積を縮小するために、中心のＮ+型領域
２２の直径を縮小して形成する。The Zener diode 2 includes a channel layer 13
On the gate oxide film 15 covering the gate electrode, using polysilicon deposited when the polysilicon is buried in the trench 14,
It is formed by alternately arranging P-type and N + -type ions. The PN junction adopts a concentric closed loop shape so that the junction end is not exposed to the polysilicon side surface. In order to further reduce the area of the PN junction, the central N + -type region 22 is formed with a reduced diameter.
【００４２】つまり最初に全体にＢ+イオンをドーズ量
５×1014cm-2でドープしてＰ型領域２１を形成した後、
ソース領域１８のイオン注入時にフォトレジストにより
選択的にPOCL3を付着し、拡散（950℃、180分）してＮ+
型領域２２を形成する。That is, first, after doping the whole with B + ions at a dose of 5 × 10 14 cm −2 to form the P-type region 21,
At the time of ion implantation of the source region 18, POCL 3 is selectively adhered by a photoresist and diffused (950 ° C., 180 minutes) to form N +
A mold region 22 is formed.
【００４３】このツェナーダイオード２は中心のＮ+型
領域２２の直径が6μｍ、Ｐ型領域２１の幅が15μｍに
なり、ＰＮ接合が同心円状に２重に形成される。中心の
Ｎ+型領域２２の直径を６μｍにしたことにより、その
面積（円周）が縮小するので最内周のＰＮ接合面積は大
幅に低減できる。The Zener diode 2 has a central N + -type region 22 having a diameter of 6 μm and a P-type region 21 having a width of 15 μm, and has a double PN junction formed concentrically. By setting the diameter of the central N + type region 22 to 6 μm, the area (circumference) is reduced, so that the innermost PN junction area can be significantly reduced.
【００４４】また、１つのＰＮ接合あたりのツェナー電
圧が６〜７Ｖなので１５Ｖのツェナー電圧を保証でき、
ゲート酸化膜１５の保証値が１０Ｖ系Ｎチャネル型パワ
ーＭＯＳＦＥＴでは、中心から同心円状にＮ+型領域２
２−Ｐ型領域２１−Ｎ+型領域２２−Ｐ型領域２１−Ｎ+
型領域２２となる。Since the Zener voltage per one PN junction is 6 to 7 V, a Zener voltage of 15 V can be guaranteed.
In an N-channel type power MOSFET in which the guaranteed value of the gate oxide film 15 is 10 V, the N + type region 2 is formed concentrically from the center.
2-P type region 21-N + type region 22-P type region 21-N +
It becomes the mold region 22.
【００４５】ここで、中心部のＮ+型領域２２を縮小す
ると、必然的にゲートパッド電極１とのコンタクト部分
の直径も小さくなってしまう。コンタクト径が小さすぎ
ると、金属との接触面積も小さくなり安定したオーミッ
ク性が得られなくなるので、中心のＮ+型領域２２のコ
ンタクト部分を掘り下げて、溝２３（直径４μｍ、深さ
0.3μｍ）を設け、この溝２３の側面で金属との接触面
積を稼げば、安定したオーミック性が得られる。Here, when the central N + type region 22 is reduced, the diameter of the contact portion with the gate pad electrode 1 is inevitably reduced. If the contact diameter is too small, the contact area with the metal becomes small and stable ohmic properties cannot be obtained. Therefore, the contact portion of the central N + -type region 22 is dug down to form the groove 23 (4 μm in diameter, depth of
If 0.3 μm) is provided and the contact area with the metal on the side surface of the groove 23 is increased, a stable ohmic property can be obtained.
【００４６】一方、この構造になってもツェナーダイオ
ード２の大きさはゲートパッド電極１の下に収まる大き
さであり、セル密度への影響はない。On the other hand, even with this structure, the size of the Zener diode 2 is small enough to fit under the gate pad electrode 1, and does not affect the cell density.
【００４７】ツェナーダイオード２上面はＢＰＳＧ（Ｂ
ｏｒｏｎ ＰｈｏｓｐｈｏｒｕｓＳｉｌｉｃａｔｅ Ｇ
ｌａｓｓ）膜９で覆われ、ゲートパット電極１とツェナ
ーダイオード２の中心部のＮ+型領域２２がコンタクト
し、ツェナーダイオード２の外周部はＭＯＳＦＥＴのソ
ース電極７にコンタクトしている。The Zener diode 2 has a BPSG (B
oron PhosphorusSilicate G
The gate pad electrode 1 and the N + -type region 22 at the center of the Zener diode 2 are in contact with each other, and the outer periphery of the Zener diode 2 is in contact with the source electrode 7 of the MOSFET.
【００４８】本発明の特徴はツェナーダイオード２の中
心のＮ+型領域２２の直径を縮小して最内周のＰＮ接合
の接合面積を縮小することにある。A feature of the present invention is that the diameter of the N + -type region 22 at the center of the Zener diode 2 is reduced to reduce the junction area of the innermost PN junction.
【００４９】電流はその経路に比例して流れることか
ら、ツェナーダイオード２のリーク電流を低減するには
リーク電流の経路であるツェナーダイオード２の接合面
積を縮小すればよい。中心部のＮ+型領域２２の直径を
従来の136μｍから６μｍに縮小することにより面積
（円周）を縮小でき、最内周のＰＮ接合面積も95.6％縮
小できる。Since the current flows in proportion to the path, the leakage current of the Zener diode 2 can be reduced by reducing the junction area of the Zener diode 2 which is the path of the leakage current. The area (circumference) can be reduced by reducing the diameter of the central N + -type region 22 from 136 μm to 6 μm, and the innermost PN junction area can be reduced by 95.6%.
【００５０】ツェナーダイオード２は２重構造で、最内
周とその外側にＰＮ接合を有する構造となっており、具
体的には最内周のＰＮ接合面積を従来に比べて95.6％縮
小すれば、それに伴い外側のＰＮ接合面積も従来に比べ
て24.4％低減できる。The Zener diode 2 has a double structure, and has a structure in which a PN junction is provided on the innermost periphery and the outer periphery thereof. Specifically, if the PN junction area on the innermost periphery is reduced by 95.6% as compared with the related art, Accordingly, the outer PN junction area can be reduced by 24.4% as compared with the conventional case.
【００５１】ここで、ツェナーダイオード２は直列接続
されているので、トータルのリーク電流はいずれか小さ
い方のＰＮ接合のリーク電流となり、本発明では最内周
のリーク電流がツェナーダイオード２のリーク電流とな
る。従ってツェナーダイオード２のリーク電流は、最内
周のＰＮ接合面積縮小率と同じで従来に比べて95.6％の
大幅な低減ができる。Here, since the Zener diodes 2 are connected in series, the total leak current is the leak current of the smaller PN junction, and in the present invention, the leak current at the innermost circumference is the leak current of the Zener diode 2. Becomes Accordingly, the leak current of the Zener diode 2 is the same as the PN junction area reduction rate at the innermost circumference, and can be greatly reduced by 95.6% as compared with the conventional case.
【００５２】一方、中心部のＮ+型領域２２が小さくな
るので必然的にゲートパッド電極１とのコンタクト径も
４μｍに減少してしまうが、中心のＮ+型領域２２を掘
り下げて溝２３を形成することにより、溝２３の側面で
の接触面積が増えるので、安定したオーミック性が得ら
れる。On the other hand, since the central N + -type region 22 becomes smaller, the contact diameter with the gate pad electrode 1 necessarily decreases to 4 μm, but the central N + -type region 22 is dug down to form the groove 23. By forming, the contact area on the side surface of the groove 23 increases, so that a stable ohmic property can be obtained.
【００５３】図３にかかるパワーＭＯＳＦＥＴの等価回
路図を示す。本発明の等価回路図はは図６と同じであ
り、この図によれば、ゲート端子Ｇとソース端子Ｓ間に
ツェナーダイオードＺD（図１ 符号２）が接続され、
ゲート端子Ｇとゲート電極間には保護用の抵抗体Ｒ
P（図１ 符号３）が接続される。なおダイオードＤIは
基板ダイオードであり、ドレイン端子Ｄとソース端子Ｓ
間に接続される。FIG. 3 shows an equivalent circuit diagram of the power MOSFET according to the present invention. The equivalent circuit diagram of the present invention is the same as FIG. 6, and according to this diagram, a Zener diode Z D (reference numeral 2 in FIG. 1) is connected between the gate terminal G and the source terminal S,
A protective resistor R is provided between the gate terminal G and the gate electrode.
P (3 in FIG. 1) is connected. Note diode D I is a substrate diode, the drain terminal D and the source terminal S
Connected between them.
【００５４】[0054]
【発明の効果】本発明に依れば、第１にトータルのリー
ク電流を大幅に低減できる。従来136μｍであったツェ
ナーダイオード２の中心部の直径が６μｍになるので、
中心部のＮ+型領域の面積（円周）が縮小され、最内周
のＰＮ接合面積を95.6％低減できる。According to the present invention, first, the total leak current can be greatly reduced. Since the diameter of the central portion of the Zener diode 2 which was conventionally 136 μm becomes 6 μm,
The area (circumference) of the central N + -type region is reduced, and the innermost PN junction area can be reduced by 95.6%.
【００５５】リーク電流はその電流経路に比例するの
で、電流経路である接合面積の縮小に伴い、リーク電流
を95.6％と大幅に低減できる。これによりＭＯＳＦＥＴ
がＯＦＦの場合のツェナーダイオード２での電力消費の
低減に大きく寄与する半導体装置を提供できる。Since the leak current is proportional to the current path, the leak current can be greatly reduced to 95.6% as the junction area as the current path is reduced. This allows MOSFET
Can be provided, which greatly contributes to a reduction in power consumption in the Zener diode 2 when is OFF.
【００５６】また、中心部を掘り下げて溝２３を設けた
ことにより、溝２３の側面でのゲートパッド電極との接
触面積を増やすことができるので、ＰＮ接合面積を縮小
しても安定したオーミック性が得られる。Further, since the groove 23 is formed by digging down the central portion, the contact area with the gate pad electrode on the side surface of the groove 23 can be increased. Is obtained.
【００５７】第２に個々のツェナーダイオード２の個数
を増やしても、ツェナーダイオード２の大きさはゲート
パッド電極１の下部に収まるため、従来のセル密度を減
らさずにリーク電流を低減できる利点を有する。Second, even if the number of the individual Zener diodes 2 is increased, the size of the Zener diode 2 can be accommodated below the gate pad electrode 1, so that there is an advantage that the leak current can be reduced without reducing the conventional cell density. Have.
【図１】本発明のＭＯＳＦＥＴの保護装置を説明する平
面図である。FIG. 1 is a plan view illustrating a MOSFET protection device according to the present invention.
【図２】本発明のＭＯＳＦＥＴの保護装置を説明する断
面図である。FIG. 2 is a cross-sectional view illustrating a MOSFET protection device according to the present invention.
【図３】本発明のＭＯＳＦＥＴの保護装置の等価回路を
説明する回路図である。FIG. 3 is a circuit diagram illustrating an equivalent circuit of a MOSFET protection device according to the present invention.
【図４】従来のＭＯＳＦＥＴの保護装置を説明する平面
図である。FIG. 4 is a plan view illustrating a conventional MOSFET protection device.
【図５】従来のＭＯＳＦＥＴの保護装置を説明する断面
図である。FIG. 5 is a cross-sectional view illustrating a conventional MOSFET protection device.
【図６】従来のＭＯＳＦＥＴの保護装置の等価回路を説
明する回路図である。FIG. 6 is a circuit diagram illustrating an equivalent circuit of a conventional MOSFET protection device.
Claims (4)
び逆導電型領域からなるツェナーダイオードを同心状に
複数個重ねたＭＯＳＦＥＴの保護装置において、前記ツ
ェナーダイオードの中心部の一導電型領域の面積を縮小
し、接合面積を縮小することを特徴とするとするＭＯＳ
ＦＥＴの保護装置。1. A protection device for a MOSFET in which a plurality of zener diodes comprising a one conductivity type region and a reverse conductivity type region provided on a polysilicon layer are concentrically stacked, wherein the one conductivity type region at the center of the zener diode is provided. MOS characterized in that the area is reduced and the junction area is reduced.
FET protection device.
け、ゲートパッド電極との接触面積を大きくすることを
特徴とする請求項１に記載のＭＯＳＦＥＴの保護装置。2. The MOSFET protection device according to claim 1, wherein a groove is provided in a center portion of said Zener diode to increase a contact area with a gate pad electrode.
極の下に設けることを特徴とする請求項１に記載のＭＯ
ＳＦＥＴの保護装置。3. The MO according to claim 1, wherein said Zener diode is provided below a gate pad electrode.
SFET protection device.
子に接続し、外周部をＭＯＳＦＥＴのソース電極に接続
することを特徴とする請求項３に記載のＭＯＳＦＥＴの
保護装置。4. The MOSFET protection device according to claim 3, wherein a central portion of the Zener diode is connected to an input terminal, and an outer peripheral portion is connected to a source electrode of the MOSFET.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000190794A JP2002009285A (en) | 2000-06-26 | 2000-06-26 | Protection device of mosfet |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000190794A JP2002009285A (en) | 2000-06-26 | 2000-06-26 | Protection device of mosfet |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002009285A true JP2002009285A (en) | 2002-01-11 |
Family
ID=18690203
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000190794A Pending JP2002009285A (en) | 2000-06-26 | 2000-06-26 | Protection device of mosfet |
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| Country | Link |
|---|---|
| JP (1) | JP2002009285A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010034188A (en) * | 2008-07-28 | 2010-02-12 | Nec Electronics Corp | Semiconductor device |
-
2000
- 2000-06-26 JP JP2000190794A patent/JP2002009285A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010034188A (en) * | 2008-07-28 | 2010-02-12 | Nec Electronics Corp | Semiconductor device |
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