JP2001257349A - Protective device for mosfet - Google Patents
Protective device for mosfetInfo
- Publication number
- JP2001257349A JP2001257349A JP2000064496A JP2000064496A JP2001257349A JP 2001257349 A JP2001257349 A JP 2001257349A JP 2000064496 A JP2000064496 A JP 2000064496A JP 2000064496 A JP2000064496 A JP 2000064496A JP 2001257349 A JP2001257349 A JP 2001257349A
- Authority
- JP
- Japan
- Prior art keywords
- zener diode
- trench
- polysilicon layer
- mosfet
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001681 protective effect Effects 0.000 title claims abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 34
- 229920005591 polysilicon Polymers 0.000 claims abstract description 34
- 241000283070 Equus zebra Species 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 11
- 239000010410 layer Substances 0.000 description 25
- 108091006146 Channels Proteins 0.000 description 15
- 239000011229 interlayer Substances 0.000 description 6
- HBBGRARXTFLTSG-UHFFFAOYSA-N Lithium ion Chemical compound [Li+] HBBGRARXTFLTSG-UHFFFAOYSA-N 0.000 description 5
- 229910001416 lithium ion Inorganic materials 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000006378 damage Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 239000008186 active pharmaceutical agent Substances 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7808—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a breakdown diode, e.g. Zener diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明はＭＯＳＦＥＴの保護
装置に係り、特にトレンチ構造を有する縦型ＭＯＳＦＥ
Ｔの保護装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a protection device for a MOSFET, and more particularly to a vertical MOSFET having a trench structure.
T protection device.
【０００２】[0002]
【従来の技術】携帯端末の普及に伴い小型で大容量のリ
チュウムイオン電池が求められるようになってきた。こ
のリチュウムイオン電池の充放電のバッテリーマネージ
メントを行う保護回路は携帯端末の軽量化のニーズによ
り、より小型で負荷ショートにも十分に耐えうるもので
なくてはならない。かかる保護回路はリチュウムイオン
電池の容器内に内蔵されるために小型化が求められ、チ
ップ部品を多用したＣＯＢ(Ｃｈｉｐ ｏｎ Ｂｏａｒ
ｄ)技術が駆使され、小型化の要求に応えてきた。しか
し一方ではリチュウムイオン電池に直列にパワーＭＯＳ
ＦＥＴを接続するのでこのパワーＭＯＳＦＥＴのオン抵
抗も極めて小さくするニーズがあり、これが携帯電話で
は通話時間や待機時間を長くするために不可欠の要素で
ある。2. Description of the Related Art With the spread of portable terminals, a small-sized and large-capacity lithium-ion battery has been required. The protection circuit for performing the battery management of the charging and discharging of the lithium ion battery must be smaller and capable of sufficiently withstanding a load short due to the need for reducing the weight of the portable terminal. Such a protection circuit is required to be miniaturized because it is built in a container of a lithium ion battery, and a COB (Chip on Boar) using a lot of chip components is required.
d) Technology has been used to meet the demand for miniaturization. However, on the other hand, a power MOS in series with a lithium ion battery
Since the FET is connected, there is a need to make the on-resistance of the power MOSFET extremely small, which is an indispensable factor for a mobile phone to increase the talk time and the standby time.
【０００３】特に保護回路ではリチュウムイオン電池Ｌ
ｉＢに直列に２個のＮチャンネル型のパワーＭＯＳＦＥ
Ｔが接続されるので、この２個のパワーＭＯＳＦＥＴの
低オン抵抗(ＲDS(on))が最も要求される項目である。こ
のためにチップを製造する上で微細加工によりセル密度
を上げる開発が進められてきた。In particular, in the protection circuit, a lithium ion battery L
Two N-channel power MOSFETs in series with iB
Since T is connected, the low on-resistance (R DS (on) ) of these two power MOSFETs is the most required item. For this reason, development for increasing the cell density by fine processing in manufacturing chips has been promoted.
【０００４】具体的には、チャンネルが半導体基板表面
に形成されるプレーナー構造ではセル密度は７４０万個
／平方インチであったが、チャンネルをトレンチの側面
に形成するトレンチ構造の第１世代ではセル密度は２５
００万個／平方インチと大幅に向上した。さらにトレン
チ構造の第２世代ではセル密度は７２００万個／平方イ
ンチまで向上できた。しかし微細化にも限度があり、セ
ル密度をさらに飛躍的に向上するには限界が見えてき
た。Specifically, in the planar structure in which the channel is formed on the surface of the semiconductor substrate, the cell density is 7.4 million cells / square inch. The density is 25
It has greatly improved to one million pieces / square inch. In the second generation of the trench structure, the cell density was improved to 72 million cells / square inch. However, there is a limit to miniaturization, and a limit has been seen to further improve the cell density dramatically.
【０００５】一方、パワーＭＯＳＦＥＴでは薄いゲート
酸化膜を静電破壊から保護するために保護用の抵抗体が
ゲート電極に挿入され更に静電気を外部に逃がすために
ゲート電極とソース電極間にツェナーダイオードが接続
されている。On the other hand, in a power MOSFET, a protection resistor is inserted into a gate electrode to protect a thin gate oxide film from electrostatic breakdown, and a zener diode is provided between the gate electrode and a source electrode to release static electricity to the outside. It is connected.
【０００６】従来のパワーＭＯＳＦＥＴの平面図を図５
に示す。１はゲートパッド電極であり、その下には保護
用のツェナーダイオード２（同心円の点線）が形成さ
れ、点線の丸印で示すようにボンディングワイヤーで電
極の取り出しが行われる。３はポリシリコンで形成され
た静電破壊防止の保護用の抵抗体であり、一端をゲート
パッド電極１に接続され、他端はゲート連結電極４に接
続されている。５は実動作領域であり、この中にパワー
ＭＯＳＦＥＴを構成する多数のＭＯＳトランジスタのセ
ル６が配列されている。７はソース電極であり、実動作
領域５上に各セルのソース領域と接続して設けられる。
ゲート連結電極４は各セル６のゲート電極と接続され且
つ実動作領域５の周囲に配置されている。なお、ソース
電極７には点線の丸印で示すようにボンディングワイヤ
が熱厚着され、電極の取り出しを行う。FIG. 5 is a plan view of a conventional power MOSFET.
Shown in Reference numeral 1 denotes a gate pad electrode, under which a protective Zener diode 2 (concentric dotted line) is formed, and the electrode is taken out by a bonding wire as shown by a dotted circle. Numeral 3 denotes a protection resistor made of polysilicon for preventing electrostatic destruction. One end is connected to the gate pad electrode 1 and the other end is connected to the gate connection electrode 4. Reference numeral 5 denotes an actual operation area, in which a number of MOS transistor cells 6 constituting a power MOSFET are arranged. Reference numeral 7 denotes a source electrode, which is provided on the actual operation region 5 so as to be connected to the source region of each cell.
The gate connection electrode 4 is connected to the gate electrode of each cell 6 and is arranged around the actual operation area 5. A bonding wire is thermally attached to the source electrode 7 as indicated by a dotted circle, and the electrode is taken out.
【０００７】図４の左側に、トレンチ型の各セル６の断
面構造を示す。ＮチャンネルのパワーＭＯＳＦＥＴにお
いては、Ｎ+型の半導体基板２１の上にＮ-型のエピタキ
シャル層からなるドレイン領域２２を設け、その上にＰ
型のチャネル層２３を設ける。チャネル層２３からドレ
イン領域２２まで到達するトレンチ２４を作り、トレン
チ２４の内壁をゲート酸化膜２５で被膜し、トレンチ２
４に充填されたポリシリコンよりなるゲート電極２６を
設けて各セル６を形成する。トレンチ２４に隣接したチ
ャネル層２３表面にはＮ+型のソース領域２８が形成さ
れ、隣り合う２つのセルのソース領域２８間のチャネル
層２３表面にはＰ+型のボディコンタクト領域２９が形
成される。さらにチャネル層２３にはソース領域２８か
らトレンチ２４に沿ってチャネル領域２７が形成され
る。トレンチ２４上は層間絶縁膜３０で覆い、ソース領
域２８およびボディコンタクト領域２９にコンタクトす
るソース電極７を設ける。かかるセル６は図５の実動作
領域５に多数個配列される。具体的には小さい四角で表
示したものが１個のセルである。FIG. 4 shows a cross-sectional structure of each trench type cell 6 on the left side. In an N-channel power MOSFET, a drain region 22 made of an N − -type epitaxial layer is provided on an N + -type semiconductor substrate 21, and a P-type drain region 22 is formed thereon.
A channel layer 23 is provided. A trench 24 extending from the channel layer 23 to the drain region 22 is formed, and an inner wall of the trench 24 is coated with a gate oxide film 25.
A gate electrode 26 made of polysilicon filled in 4 is provided to form each cell 6. An N + -type source region 28 is formed on the surface of the channel layer 23 adjacent to the trench 24, and a P + -type body contact region 29 is formed on the surface of the channel layer 23 between the source regions 28 of two adjacent cells. You. Further, a channel region 27 is formed in the channel layer 23 from the source region 28 along the trench 24. The trench 24 is covered with an interlayer insulating film 30, and a source electrode 7 that contacts the source region 28 and the body contact region 29 is provided. Many such cells 6 are arranged in the actual operation area 5 in FIG. Specifically, one cell is represented by a small square.
【０００８】図４の右側にツェナーダイオード２の断面
構造を示す。チャネル層２３を覆うゲート酸化膜２５上
にトレンチ２４にポリシリコンを埋め込む時に堆積され
たポリシリコンを用いて、最初に全体をＰ-型にドープ
した後ソース領域２８のイオン注入時に選択的にＮ+型
にドープしてツェナーダイオード２を形成している。す
なわち、中心から同心円状にＮ+型領域−Ｐ-型領域−Ｎ
+型領域−Ｐ-型領域−Ｎ+型領域−Ｐ-型領域−Ｎ+型領
域となり、６個のツェナーダイオードが直列に接続され
る。さらにそのポリシリコン上面はＰＳＧ（Ｐｈｏｓｐ
ｈｏｒｕｓ Ｓｉｌｉｃａｔｅ Ｇｌａｓｓ）膜９で覆
われ、ゲートパット電極１とツェナーダイオード２の中
心のＮ+型領域がコンタクトしている。ツェナーダイオ
ード２を形成するＰＮ接合はポリシリコンに形成される
ので、その接合端をポリシリコン側面に露出しないよう
に同心円上に閉ループの形状を採用する。従って、ツェ
ナーダイオード２に３０Ｖのツェナー降伏電圧が要求さ
れるときは１つのＰＮ接合当たりのツェナー降伏電圧が
５〜７Ｖであるので６個のＰＮ接合が同心円上に形成さ
れればよい。FIG. 4 shows the cross-sectional structure of the Zener diode 2 on the right side. Using polysilicon deposited when the polysilicon is buried in the trench 24 on the gate oxide film 25 covering the channel layer 23, the whole is first doped into P − type, and then N is selectively implanted during the ion implantation of the source region 28. The zener diode 2 is formed by doping into a + type. That is, the N + type region −P − type region −N concentrically from the center.
A + type region-P - type region-N + type region-P - type region-N + type region, and six Zener diodes are connected in series. Further, the upper surface of the polysilicon is formed by PSG (Phosp).
The gate pad electrode 1 is in contact with the N + type region at the center of the Zener diode 2. Since the PN junction forming the Zener diode 2 is formed of polysilicon, a closed loop shape is adopted on a concentric circle so that the junction end is not exposed on the side surface of the polysilicon. Therefore, when a Zener breakdown voltage of 30 V is required for the Zener diode 2, the Zener breakdown voltage per PN junction is 5 to 7 V, so that six PN junctions may be formed concentrically.
【０００９】図６にかかるパワーＭＯＳＦＥＴの等価回
路図を示す。この図によれば、ゲート端子Ｇとソース端
子Ｓ間にツェナーダイオードＺD（図５ 符号２）が接
続され、ゲート端子Ｇとゲート電極間には保護用の抵抗
体ＲP（図５ 符号３）が接続される。なおダイオード
ＤIは基板ダイオードであり、ドレイン端子Ｄとソース
端子Ｓ間に接続される。FIG. 6 shows an equivalent circuit diagram of the power MOSFET. According to this figure, a Zener diode Z D (2 in FIG. 5) is connected between the gate terminal G and the source terminal S, and a protection resistor R P (3 in FIG. 5) is connected between the gate terminal G and the gate electrode. ) Is connected. Note diode D I is a substrate diode, is connected between the drain terminal D and the source terminal S.
【００１０】[0010]
【発明が解決しようとする課題】かかる従来のパワーＭ
ＯＳＦＥＴではリーク電流を防ぐためにツェナーダイオ
ード２のＰＮ接合が同心円上に配列されるため、ツェナ
ーダイオード２に例えば５０Ｖと高いツェナー降伏電圧
を要求されると１０個のＰＮ接合を同心円上に配列しな
ければならずツェナーダイオード２を形成するポリシリ
コンの大きさは実動作領域を狭めることになり、セル構
造をトレンチ型にしてもある程度のセル密度の減少はさ
けられない問題点を有していた。The conventional power M
In the OSFET, the PN junctions of the Zener diode 2 are arranged concentrically in order to prevent leakage current. Therefore, when a high Zener breakdown voltage of, for example, 50 V is required for the Zener diode 2, ten PN junctions must be arranged concentrically. In other words, the size of the polysilicon forming the Zener diode 2 narrows the actual operation region, and there is a problem that a certain reduction in cell density cannot be avoided even if the cell structure is a trench type.
【００１１】またツェナーダイオード２を形成するポリ
シリコンにはまずボロン（Ｐ-）を注入し、その後砒素
（Ｎ+）を注入させるが、同心円が大きくなると中心部
分と外側のＮ+型領域の大きさが異なり、Ｎ+型領域の濃
度のばらつきも大きくなるため、結果的に中心部分と外
側でのツェナー降伏電圧にもばらつきが出る問題点もあ
った。[0011] First boron into the polysilicon to form the Zener diode 2 (P -) was injected, then it is implanted with arsenic (N +), the size of the central portion and the outer N + -type region when concentrically increases However, since the variation in the concentration of the N + -type region becomes large, there is also a problem that the Zener breakdown voltage at the central portion and at the outside also varies.
【００１２】[0012]
【課題を解決するための手段】本発明はかかる課題に鑑
みてなされ、半導体基板上のチャネル層に設けたトレン
チ内に埋設したポリシリコン層に複数個のツェナーダイ
オードを形成することにより、ツェナーダイオードの専
有面積を減らして実動作領域の面積を拡げ、セル密度の
高いパワーＭＯＳＦＥＴを提供するものである。SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and has been made by forming a plurality of Zener diodes in a polysilicon layer buried in a trench provided in a channel layer on a semiconductor substrate. The present invention provides a power MOSFET having a high cell density by reducing the area occupied by the device and increasing the area of the actual operation region.
【００１３】またこのツェナーダイオードをストライプ
状に形成しＰＮ接合をゼブラ状に形成することにより高
いツェナー降伏電圧が要求されても少ない専有面積のツ
ェナーダイオードを実現するパワーＭＯＳＦＥＴを提供
するものである。It is another object of the present invention to provide a power MOSFET which realizes a Zener diode having a small occupied area even when a high Zener breakdown voltage is required by forming the Zener diode in a stripe shape and forming a PN junction in a zebra shape.
【００１４】[0014]
【発明の実施の形態】本発明の実施の形態を図１から図
３を参照して詳細に説明する。本発明のパワーＭＯＳＦ
ＥＴの平面図を図３に示す。尚、図５に示すものと同一
構成要素は同一符号とする。１はゲートパッド電極であ
り、その近くにポリシリコンより成る保護用のツェナー
ダイオード２が形成され、点線の丸印で示すようにボン
ディングワイヤーで電極の取り出しが行われる。３はポ
リシリコンで形成された静電破壊防止の保護用の抵抗体
であり、一端をゲートパッド電極１に接続され、他端は
ゲート連結電極４に接続されている。５は実動作領域で
あり、この中にパワーＭＯＳＦＥＴを構成する多数のＭ
ＯＳトランジスタのセル６が配列されている。７はソー
ス電極であり、実動作領域５上に設けられ且つ各セル６
のソース領域と接続して設けられる。ゲート連結電極４
は各セル６のゲート電極と接続され且つ実動作領域５の
周囲に配置されている。なお、ソース電極７には点線の
丸印で示すようにボンディングワイヤが熱厚着され、電
極の取り出しを行う。８はシールド電極であり、その下
にはアニュラーリングが設けられシールド電極８とコン
タクトして、チップ終端への空乏層の拡がりを抑える。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail with reference to FIGS. Power MOSF of the present invention
FIG. 3 shows a plan view of the ET. The same components as those shown in FIG. Reference numeral 1 denotes a gate pad electrode, on which a protective zener diode 2 made of polysilicon is formed, and an electrode is taken out by a bonding wire as shown by a dotted circle. Numeral 3 denotes a protection resistor made of polysilicon for preventing electrostatic destruction. One end is connected to the gate pad electrode 1 and the other end is connected to the gate connection electrode 4. Reference numeral 5 denotes an actual operation area, in which a number of Ms constituting a power MOSFET are arranged.
OS transistor cells 6 are arranged. Reference numeral 7 denotes a source electrode which is provided on the actual operation area 5 and has
Is provided in connection with the source region of. Gate connecting electrode 4
Are connected to the gate electrode of each cell 6 and are arranged around the actual operation area 5. A bonding wire is thermally attached to the source electrode 7 as indicated by a dotted circle, and the electrode is taken out. Reference numeral 8 denotes a shield electrode. An annular ring is provided below the shield electrode 8 to make contact with the shield electrode 8 to prevent the depletion layer from spreading to the chip end.
【００１５】図１の左側は本発明に用いるトレンチ型の
セル６の断面構造を示す。尚、図４に示すものと同一構
成要素は同一記号とする。Ｎ+型の半導体基板２１の上
にＮ-型のエピタキシャル層からなるドレイン領域２２
を設け、その上にＰ型のチャネル層２３を設ける。チャ
ネル層２３からドレイン領域２２まで到達するトレンチ
２４を作り、トレンチ２４の内壁をゲート酸化膜２５で
被膜し、トレンチ２４に充填されたポリシリコンよりな
るゲート電極２６を設けて各セル６を形成する。トレン
チ２４に隣接したチャネル層２３表面にはＮ+型のソー
ス領域２８が形成され、隣り合う２つのセルのソース領
域２８間のチャネル層２３表面にはＰ+型のボディコン
タクト領域２９が形成される。さらにチャネル層２３に
はソース領域２８からトレンチ２４に沿ってチャネル領
域２７が形成される。トレンチ２４上は層間絶縁膜３０
で覆い、ソース領域２８およびボディコンタクト領域２
９にコンタクトするソース電極７を設ける。かかるセル
６は図３の実動作領域５に多数個配列される。具体的に
は小さい四角で表示したものが１個のセルである。The left side of FIG. 1 shows a sectional structure of a trench type cell 6 used in the present invention. The same components as those shown in FIG. A drain region 22 composed of an N − type epitaxial layer on an N + type semiconductor substrate 21
And a P-type channel layer 23 is provided thereon. A trench 24 extending from the channel layer 23 to the drain region 22 is formed, an inner wall of the trench 24 is coated with a gate oxide film 25, and a gate electrode 26 made of polysilicon filled in the trench 24 is provided to form each cell 6. . An N + -type source region 28 is formed on the surface of the channel layer 23 adjacent to the trench 24, and a P + -type body contact region 29 is formed on the surface of the channel layer 23 between the source regions 28 of two adjacent cells. You. Further, a channel region 27 is formed in the channel layer 23 from the source region 28 along the trench 24. On the trench 24, the interlayer insulating film 30
And the source region 28 and the body contact region 2
9 is provided. Many such cells 6 are arranged in the actual operation area 5 of FIG. Specifically, one cell is represented by a small square.
【００１６】本発明の特徴は保護用のツェナーダイオー
ド２の形状にある。ツェナーダイオード２はゲートパッ
ド電極１の近くに配置され、一端をゲートパッド電極１
に接続され、他端はソース電極７に接続されている。A feature of the present invention lies in the shape of the Zener diode 2 for protection. The Zener diode 2 is disposed near the gate pad electrode 1 and has one end connected to the gate pad electrode 1.
And the other end is connected to the source electrode 7.
【００１７】このツェナーダイオード２は図１の右側お
よび図２の平面図に示すように、セル６のトレンチ２４
と同時にトレンチ１７を形成し、その内壁をゲート酸化
膜２５で被覆し、ポリシリコンを付着させる。このポリ
シリコン層１９はセル６のトレンチ２４を埋めるポリシ
リコンの生成時に同時に付着される。ポリシリコン層１
９はチャネル層２３上面のゲート酸化膜２５からトレン
チ１７の側面および底面のゲート酸化膜２５上を延在さ
れて細長いストライプ状にエッチングされ、両端はコン
タクトを形成されるために大きく形成されている。従っ
てツェナーダイオード２を形成する部分はトレンチ１７
内に埋め込まれ、その上には厚い層間絶縁膜２０で覆わ
れている。このポリシリコン層１９は、最初に全体をＰ
-型にドープした後ソース領域２８のイオン注入時にホ
トレジストで選択的にＮ+型にドープしてツェナーダイ
オード２を形成している。すなわち、端部からゼブラ状
にＮ+型領域−Ｐ-型領域−Ｎ+型領域−Ｐ-型領域−Ｎ+
型領域−Ｐ-型領域−Ｎ+型領域となり、６個のツェナー
ダイオードが直列に接続される。ツェナーダイオード２
を形成する平坦なＰＮ接合はその上面および側面端部を
トレンチ１７内の層間絶縁膜２０で被覆されているの
で、ＰＮ接合端でのリーク電流の発生はない。従って、
ツェナーダイオード２に３０Ｖのツェナー降伏電圧が要
求されるときは１つのＰＮ接合当たりのツェナー降伏電
圧が５〜７Ｖであるので６個のＰＮ接合がゼブラ状に形
成されればよい。As shown in the right side of FIG. 1 and the plan view of FIG.
At the same time, a trench 17 is formed, its inner wall is covered with a gate oxide film 25, and polysilicon is deposited. This polysilicon layer 19 is deposited at the same time that the polysilicon filling the trench 24 of the cell 6 is generated. Polysilicon layer 1
Numeral 9 extends from the gate oxide film 25 on the upper surface of the channel layer 23 to the gate oxide film 25 on the side and bottom surfaces of the trench 17 and is etched in a long and narrow stripe shape. Both ends are formed large to form contacts. . Therefore, the portion where the Zener diode 2 is formed is the trench 17
And is covered with a thick interlayer insulating film 20. This polysilicon layer 19 is initially entirely P
After doping into the − type, the zener diode 2 is formed by selectively doping with N + type with photoresist at the time of ion implantation of the source region 28. That is, an N + type region-P - type region-N + type region-P - type region-N + like a zebra from the end.
A type region -P - type region -N + type region, and six Zener diodes are connected in series. Zener diode 2
Is covered with the interlayer insulating film 20 in the trench 17, so that no leak current occurs at the PN junction end. Therefore,
When a Zener breakdown voltage of 30 V is required for the Zener diode 2, the Zener breakdown voltage per PN junction is 5 to 7 V, so that six PN junctions may be formed in a zebra shape.
【００１８】本発明のパワーＭＯＳＦＥＴの等価回路図
は図６と同じであり、ゲート端子Ｇとソース端子Ｓ間に
ツェナーダイオードＺD（図３ 符号２）が接続され、
ゲート端子Ｇとゲート電極間には保護用の抵抗体Ｒ
P（図３ 符号３）が接続される。なおダイオードＤIは
基板ダイオードであり、ドレイン端子Ｄとソース端子Ｓ
間に接続される。The equivalent circuit diagram of the power MOSFET of the present invention is the same as that of FIG. 6, and a Zener diode Z D (2 in FIG. 3) is connected between the gate terminal G and the source terminal S.
A protective resistor R is provided between the gate terminal G and the gate electrode.
P (3 in FIG. 3) is connected. Note diode D I is a substrate diode, the drain terminal D and the source terminal S
Connected between them.
【００１９】[0019]
【発明の効果】本発明に依れば、第１にポリシリコン層
１９をトレンチ２４内に細長くストライプ状に形成し、
ゼブラ状に同じ大きさのＮ+領域とＰ-領域を形成してツ
ェナーダイオード２を形成することができる。従って、
従来の同心円状の場合よりＮ+領域の拡散による不純物
濃度のばらつきを減少させることができ、各ＰＮ接合の
ツェナー降伏電圧のばらつきを減少できるので、トレン
チ２４内でのＰＮ接合数の増減により所定のツェナーダ
イオード２のツェナー降伏電圧をその面積を増やすこと
なく容易に実現できる利点を有する。According to the present invention, first, the polysilicon layer 19 is formed in the trench 24 in an elongated stripe shape,
The zener diode 2 can be formed by forming an N + region and a P − region having the same size in a zebra shape. Therefore,
Since the variation in the impurity concentration due to the diffusion of the N + region can be reduced and the variation in the Zener breakdown voltage of each PN junction can be reduced as compared with the conventional concentric shape, the predetermined number can be reduced by increasing or decreasing the number of PN junctions in the trench 24. Has the advantage that the Zener breakdown voltage of the Zener diode 2 can be easily realized without increasing its area.
【００２０】第２に、本発明のツェナーダイオード２は
トレンチ２４内に埋め込まれたポリシリコン層１９で形
成されるので、ポリシリコン層１９の側面は層間絶縁膜
３０およびトレンチ内壁のゲート酸化膜２５で覆われて
いる。従って、ツェナーダイオード２を構成するＰＮ接
合がポリシリコン層１９の側面で終端しても層間絶縁膜
３０およびゲート酸化膜２５で保護されているので、Ｐ
Ｎ接合のリーク電流を最小限に押さえることができる利
点を有する。Second, since the Zener diode 2 of the present invention is formed by the polysilicon layer 19 buried in the trench 24, the side surface of the polysilicon layer 19 has an interlayer insulating film 30 and a gate oxide film 25 on the inner wall of the trench. Covered with. Therefore, even if the PN junction constituting the Zener diode 2 is terminated at the side surface of the polysilicon layer 19, the PN junction is protected by the interlayer insulating film 30 and the gate oxide film 25.
This has the advantage that the leakage current of the N-junction can be minimized.
【００２１】第３に、本発明のツェナーダイオード２は
ポリシリコン層１９の細長い形状に形成できるので、ツ
ェナーダイオード２の占有面積は従来より大幅に小さく
できる。このため従来ではツェナーダイオード２の同心
円状のＰＮ接合の数でその占有面積は決められ、ゲート
パッド電極１より大きく形成される場合が多かったが、
本発明ではゲートパッド電極１をボンディングに必要な
大きさに決めれば良く、具体的にはゲートパッド電極１
の面積は金線直径２３μｍの場合、従来より約７５％
減、金線直径７０μｍの場合、従来より約５６％減とな
り、その分実動作領域５の面積を増大でき、結果的にチ
ップ面積当たりのセル密度を上げられる利点を有する。Third, since the Zener diode 2 of the present invention can be formed in an elongated shape of the polysilicon layer 19, the area occupied by the Zener diode 2 can be significantly reduced as compared with the conventional case. For this reason, conventionally, the occupied area is determined by the number of concentric PN junctions of the Zener diode 2 and is often formed larger than the gate pad electrode 1.
In the present invention, the gate pad electrode 1 may be determined to have a size necessary for bonding.
Area is about 75% compared to the conventional case when the gold wire diameter is 23 μm.
In the case where the diameter is reduced and the gold wire diameter is 70 μm, it is reduced by about 56% compared to the conventional case, and the area of the actual operation region 5 can be increased accordingly, and as a result, the cell density per chip area can be increased.
【００２２】第４に、本発明では従来のトレンチ構造の
セル６を形成するプロセスを変更することなく、本発明
のツェナーダイオード２を形成できる利点もある。Fourth, according to the present invention, there is also an advantage that the Zener diode 2 of the present invention can be formed without changing the process of forming the conventional cell 6 having a trench structure.
【図１】本発明のＭＯＳＦＥＴの保護装置を説明する断
面図である。FIG. 1 is a cross-sectional view illustrating a MOSFET protection device according to the present invention.
【図２】本発明のＭＯＳＦＥＴの保護装置のみを説明す
る平面図である。FIG. 2 is a plan view illustrating only a MOSFET protection device according to the present invention.
【図３】本発明のＭＯＳＦＥＴの保護装置を説明する平
面図である。FIG. 3 is a plan view illustrating a MOSFET protection device according to the present invention.
【図４】従来のＭＯＳＦＥＴの保護装置を説明する断面
図である。FIG. 4 is a cross-sectional view illustrating a conventional MOSFET protection device.
【図５】従来のＭＯＳＦＥＴの保護装置を説明する平面
図である。FIG. 5 is a plan view illustrating a conventional MOSFET protection device.
【図６】本発明および従来のＭＯＳＦＥＴの保護装置の
等価回路を説明する回路図である。FIG. 6 is a circuit diagram illustrating an equivalent circuit of the present invention and a conventional MOSFET protection device.
Claims (8)
チと、該トレンチ内に埋設したポリシリコン層と該ポリ
シリコン層に形成した複数個のツェナーダイオードとを
具備することを特徴とするＭＯＳＦＥＴの保護装置。1. A MOSFET comprising: a trench provided in a channel layer on a semiconductor substrate; a polysilicon layer buried in the trench; and a plurality of Zener diodes formed in the polysilicon layer. Protective equipment.
を前記ポリシリコン層の側面で終わらせることを特徴と
する請求項１記載のＭＯＳＦＥＴの保護装置。2. The MOSFET protection device according to claim 1, wherein a junction end for forming said Zener diode ends at a side surface of said polysilicon layer.
前記ツェナーダイオードを形成する接合をゼブラ状にし
て前記ポリシリコン層の側面で終わらせることを特徴と
する請求項２記載のＭＯＳＦＥＴの保護装置。3. The method according to claim 2, wherein the polysilicon layer is formed in a stripe shape.
3. The MOSFET protection device according to claim 2, wherein a junction forming the Zener diode is formed in a zebra shape and ends at a side surface of the polysilicon layer.
極の近傍に設けることを特徴とする請求項１記載のＭＯ
ＳＦＥＴの保護装置。4. The MO according to claim 1, wherein said Zener diode is provided near a gate pad electrode.
SFET protection device.
チと、実動作領域の該トレンチ内に形成したトレンチ型
のＭＯＳＦＥＴのセルと、ゲートパッド電極が形成され
る近くに設けた前記トレンチに埋設したポリシリコン層
と、該ポリシリコン層に形成した複数個のツェナーダイ
オードとを具備することを特徴とするＭＯＳＦＥＴの保
護装置。5. A trench provided in a channel layer on a semiconductor substrate, a trench type MOSFET cell formed in the trench in an actual operation region, and embedded in the trench provided near a gate pad electrode. A MOSFET protection device comprising: a polysilicon layer formed as described above; and a plurality of Zener diodes formed in the polysilicon layer.
を前記ポリシリコン層の側面で終わらせることを特徴と
する請求項５記載のＭＯＳＦＥＴの保護装置。6. The MOSFET protection device according to claim 5, wherein a junction end forming said Zener diode ends at a side surface of said polysilicon layer.
前記ツェナーダイオードを形成する接合をゼブラ状にし
て前記ポリシリコン層の側面で終わらせることを特徴と
する請求項５または請求項６記載のＭＯＳＦＥＴの保護
装置。7. The polysilicon layer is striped,
7. The MOSFET protection device according to claim 5, wherein a junction forming the Zener diode is formed in a zebra shape and ends at a side surface of the polysilicon layer.
極の近傍に設けることを特徴とする請求項５記載のＭＯ
ＳＦＥＴの保護装置。8. The MO according to claim 5, wherein said Zener diode is provided near a gate pad electrode.
SFET protection device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000064496A JP2001257349A (en) | 2000-03-09 | 2000-03-09 | Protective device for mosfet |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000064496A JP2001257349A (en) | 2000-03-09 | 2000-03-09 | Protective device for mosfet |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001257349A true JP2001257349A (en) | 2001-09-21 |
Family
ID=18584193
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000064496A Pending JP2001257349A (en) | 2000-03-09 | 2000-03-09 | Protective device for mosfet |
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| Country | Link |
|---|---|
| JP (1) | JP2001257349A (en) |
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| JP2006100494A (en) * | 2004-09-29 | 2006-04-13 | Nec Electronics Corp | Vertical mosfet |
| WO2007092089A1 (en) | 2005-12-28 | 2007-08-16 | Vishay-Siliconix | Trench polysilicon diode |
| JP2009111320A (en) * | 2007-11-01 | 2009-05-21 | Fuji Electric Device Technology Co Ltd | Silicon carbide trench mos type semiconductor device |
| KR100922555B1 (en) | 2007-12-27 | 2009-10-21 | 주식회사 동부하이텍 | Method of manufacturing a semiconductor for protecting electrostatic discharge |
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| JP2018182324A (en) * | 2017-04-13 | 2018-11-15 | インフィネオン テクノロジーズ アーゲーＩｎｆｉｎｅｏｎ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ａｇ | Semiconductor device having electrostatic discharge protection structure |
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| DE102004045467A1 (en) * | 2004-09-20 | 2006-03-30 | Infineon Technologies Ag | Field effect trench transistor |
| US8772861B2 (en) * | 2004-09-20 | 2014-07-08 | Infineon Technologies Ag | Field effect trench transistor having active trenches |
| DE102004045467B4 (en) | 2004-09-20 | 2020-07-30 | Infineon Technologies Ag | Field effect trench transistor |
| JP2006100317A (en) * | 2004-09-28 | 2006-04-13 | Nec Electronics Corp | Semiconductor device |
| JP2006100494A (en) * | 2004-09-29 | 2006-04-13 | Nec Electronics Corp | Vertical mosfet |
| US9111754B2 (en) | 2005-07-26 | 2015-08-18 | Vishay-Siliconix | Floating gate structure with high electrostatic discharge performance |
| EP1966830A4 (en) * | 2005-12-28 | 2010-06-02 | Vishay Siliconix | Trench polysilicon diode |
| JP2009522784A (en) * | 2005-12-28 | 2009-06-11 | ビシェイ−シリコニクス | Trench polysilicon diode |
| EP1966830A1 (en) * | 2005-12-28 | 2008-09-10 | Vishay-Siliconix | Trench polysilicon diode |
| US8072013B1 (en) | 2005-12-28 | 2011-12-06 | Vishay-Siliconix | Trench polysilicon diode |
| US9431550B2 (en) | 2005-12-28 | 2016-08-30 | Vishay-Siliconix | Trench polysilicon diode |
| KR101098918B1 (en) * | 2005-12-28 | 2011-12-27 | 비쉐이-실리코닉스 | Trench polysilicon diode |
| WO2007092089A1 (en) | 2005-12-28 | 2007-08-16 | Vishay-Siliconix | Trench polysilicon diode |
| US7859083B2 (en) | 2007-08-09 | 2010-12-28 | Fuji Electric Systems Co., Ltd. | Semiconductor device |
| US7872307B2 (en) | 2007-10-12 | 2011-01-18 | Promos Technologies Inc. | Power MOSFET array |
| JP2009111320A (en) * | 2007-11-01 | 2009-05-21 | Fuji Electric Device Technology Co Ltd | Silicon carbide trench mos type semiconductor device |
| KR100922555B1 (en) | 2007-12-27 | 2009-10-21 | 주식회사 동부하이텍 | Method of manufacturing a semiconductor for protecting electrostatic discharge |
| JP2011009337A (en) * | 2009-06-24 | 2011-01-13 | Toshiba Corp | Semiconductor device |
| US9576841B2 (en) | 2011-06-08 | 2017-02-21 | Rohm Co., Ltd. | Semiconductor device and manufacturing method |
| US8772827B2 (en) | 2011-06-08 | 2014-07-08 | Rohm Co., Ltd. | Semiconductor device and manufacturing method |
| US9129982B2 (en) | 2011-06-08 | 2015-09-08 | Rohm Co., Ltd. | Semiconductor device and manufacturing method |
| US9362352B2 (en) | 2011-06-08 | 2016-06-07 | Rohm Co., Ltd. | Semiconductor device and manufacturing method |
| US8889493B2 (en) | 2011-06-08 | 2014-11-18 | Rohm Co., Ltd. | Manufacturing method of semiconductor device |
| US8994066B2 (en) | 2011-06-08 | 2015-03-31 | Rohm Co., Ltd. | Manufacturing method of semiconductor device |
| CN102280382A (en) * | 2011-09-07 | 2011-12-14 | 杭州士兰集成电路有限公司 | Electrostatic discharge protecting structure integrated in insulated gate bipolar transistor (IGBT) apparatus and manufacturing method of electrostatic discharge protecting structure |
| US10090294B2 (en) | 2016-03-04 | 2018-10-02 | Rohm Co., Ltd. | Semiconductor device |
| US10566325B2 (en) | 2016-03-04 | 2020-02-18 | Rohm Co., Ltd. | Semiconductor device |
| CN107293486A (en) * | 2016-03-31 | 2017-10-24 | 北大方正集团有限公司 | Channel-type semiconductor device and its manufacture method with ESD structures |
| JP2018182324A (en) * | 2017-04-13 | 2018-11-15 | インフィネオン テクノロジーズ アーゲーＩｎｆｉｎｅｏｎ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ａｇ | Semiconductor device having electrostatic discharge protection structure |
| JP7207861B2 (en) | 2017-04-13 | 2023-01-18 | インフィネオン テクノロジーズ アーゲー | Semiconductor device including electrostatic discharge protection structure |
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