JP4032622B2 - Semiconductor element and semiconductor device and converter using the same - Google Patents

Semiconductor element and semiconductor device and converter using the same Download PDF

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JP4032622B2
JP4032622B2 JP2000274991A JP2000274991A JP4032622B2 JP 4032622 B2 JP4032622 B2 JP 4032622B2 JP 2000274991 A JP2000274991 A JP 2000274991A JP 2000274991 A JP2000274991 A JP 2000274991A JP 4032622 B2 JP4032622 B2 JP 4032622B2
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JP2002083964A (en
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長谷川　　満
弘則 児玉
秀男 小林
正浩 長洲
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Hitachi Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

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Description

【０００１】
【発明の属する技術分野】
本発明は、半導体素子に係り、特に均一なスイッチング動作に優れた半導体素子及びこれを用いた半導体装置並びに電力変換器に関する。
【０００２】
【従来の技術】
近年、省エネルギー等の推進のため、半導体パワーデバイスのインバータ装置等への適用が進められている。特に高い耐電圧性能を有する半導体素子の開発も進められており、最近では絶縁ゲート型バイポーラトランジスタ（以降ＩＧＢＴと記す）やＭＯＳＦＥＴ等の半導体素子が広く用いられている。また、半導体装置の電流容量を向上させる場合には、上記の半導体素子を複数、並列接続して所望の大きな電流容量を得ることが行われている。
【０００３】
上記のように複数の半導体素子を並列に接続する場合に、半導体素子間で特性にバラツキがあると素子の均一動作が難しく、素子の破壊が生じる。これらの問題に対して、日本国特許第02608451号公報では、制御端子に外付けチップ抵抗を接続して、半導体素子の均一動作を図る方法が開示されている。さらに、各々の制御電極同士も並列接続されるが、スイッチング動作時には配線のインダクタンスによって過渡的に制御電流振動が生じ、素子の誤動作や、最悪の場合は素子の破壊が生じる。これを抑制する目的で素子の制御電極と外部端子との間に外付けチップ抵抗を接続することが行われている。
【０００４】
【発明が解決しようとする課題】
上記の場合、半導体装置の大容量化を図ろうとする場合、並列接続される半導体素子数が増えると、各半導体素子に接続される外付けチップ抵抗の数も増大するため、製造プロセスの複雑化やコストが上昇するという問題があった。
【０００５】
本発明は、上記問題点を考慮してなされたものであり、複数半導体素子の並列接続時に於けるスイッチング動作を安定化し、かつ、半導体素子内部での不均一動作を抑えた、高信頼な半導体素子及びこれを用いた半導体装置と電力変換器を提供することにある。
【０００６】
【課題を解決するための手段】
本発明による半導体素子においては、外付けチップ抵抗と同等の効果を有するゲート抵抗を、半導体素子に内蔵させる。
【０００７】
より具体的には、半導体基板の一方の主表面上に、半導体素子の通電動作に関与する半導体能動領域と、半導体基板から絶縁されて半導体能動領域を制御する制御配線と、制御配線と電気的に接続され、かつ外部制御端子と接続するために設けられた制御電極が設けられる。さらに、制御配線と制御電極との接続間に電気抵抗領域を有し、かつ電気抵抗領域と制御配線の接続位置を基準とした場合の電気抵抗領域側の抵抗値が、制御配線側の最大の配線抵抗値よりも大きくなる構造とする。
【０００８】
さらに、電気抵抗領域の一端が制御電極に接続され、他の一端が低抵抗配線を介して複数の制御配線端部と接続される構造とすることが、半導体内部の均一動作という点でより好ましい。
【０００９】
本発明によれば、半導体素子内部にゲート抵抗を内蔵させることで、半導体素子間の不均一動作を抑制することが出来る。また、半導体素子内部の動作も均一性が向上する。
【００１０】
【発明の実施の形態】
以下、図面を用いて本発明を詳細に説明する。ただし、本発明は下記実施例に限定されるものではない。
【００１１】
図２は本発明を実施したプレーナ型ＩＧＢＴの一部断面及び表面鳥瞰図である。シリコンで形成されたｎ型半導体基板１の一方の表面にはｐ導電型半導体層１１及びｎ型半導体層１２が形成されている。このｎ型半導体基板１の表面には、隣り合ったｐ型半導体層１１の間に挟まれる形で、シリコン酸化物(ＳｉＯ2）で形成されたゲート酸化膜２１及び多結晶シリコンで形成された制御配線膜２２が形成される。このゲート酸化膜２１及び制御配線膜２２の全面を被うように、りんガラス（ＰＳＧ）で層間絶縁膜２３が形成される。さらにこれらを被い、ｐ導電型半導体層１１及びｎ型半導体層１２の露出面に接触した形で、Ｓｉを１〜３ｗｔ％含有するＡｌ合金により構成されるエミッタ電極膜３０を形成する。ここで、エミッタ電極膜に接続されて半導体素子の通電動作に寄与する部分を、半導体能動領域と呼ぶ。
【００１２】
また、これらの領域を取り囲むように環状のｐ+ 型半導体層１３及びｎ+ 型半導体層１４が形成される。ｎ型半導体基板１の表面には、ｐ+ 型半導体層１３及びｎ+ 型半導体層１４の間に隣接してＳｉＯ2 によるフィールド酸化膜２４が形成される。さらにフィールド酸化膜２４の間でｐ+ 型半導体層１３及びｎ+ 型半導体層１４に接するように、Ｓｉを１〜３ｗｔ％含有するＡｌ合金で金属層３１が形成される。これらの領域は特にターミネーション領域と呼ぶ。
【００１３】
また、制御配線膜２２を被う層間絶縁膜２３の一部に開口部を設け、隣接するエミッタ電極膜とは絶縁されて制御配線膜２２の露出部に接続するように、Ｓｉを１〜３ｗｔ％含有するＡｌ合金で制御配線電極膜３２が形成される。この制御配線電極膜３２が接続された部分の制御配線膜２２は、それ以外の部分に比べて配線抵抗が低くなることから、半導体能動領域内に所定の間隔で形成して、半導体能動領域全体の単位素子への信号の伝達が均等になる。なお、半導体領域の動作を制御するための制御配線は、制御配線膜２２と制御配線電極膜３２との複合構造であっても良い。また、制御配線膜２２と外部端子との接続を行うために、隣接するエミッタ電極膜とは絶縁されて、Ｓｉを１〜３ｗｔ％含有するＡｌ合金で制御電極３３が形成される。さらに、制御電極３３と制御配線膜２２との間には、多結晶シリコンで形成された電気抵抗領域４０が接続される。また、ｎ型半導体基板１の他方の表面には、ｐ導電型半導体層２を有しており、このｐ導電型半導体層２の露出した表面には裏面電極膜３が接続して形成されている。ここで、本実施例では電気抵抗領域４０を個別に設けて形成しているが、例えば制御配線電極膜３２を接続しない制御配線膜２２の一部を利用してもかまわない。なお本実施例において、電気抵抗領域４０と制御配線膜２２との接続位置を基準位置とした場合に、制御電極３３までの電気抵抗値が、制御配線膜２２の配線抵抗値の最大値より大きくなるように、電気抵抗領域４０を設けている。ここで配線抵抗値とは、基準位置と、アクティブ領域のある位置との間における、制御配線膜２２の電気抵抗値である。
【００１４】
このように、電気抵抗領域を半導体素子に作り込むことで、外付け部品の実装工数の増加が無く、外付けチップ抵抗部品も不要となるため、並列動作に優れた半導体素子を低コストで得ることができる。電気抵抗領域の材質として多結晶シリコンを用いる場合、電気抵抗領域の幅や厚みなどの形状を調節すれば所望の抵抗値を得ることができる。この他、ＴｉＳｉ2，ＭｏＳｉ2，ＷＳｉ2 等のシリサイド系材料や、ＲｕＯ2，ＳｎＯ2，Ｔａ−Ｎ，Ｔａ−Ｓｉ等のセラミックス材料を用いることももちろん可能である。さらには、半導体基体中に不純物を拡散して形成した半導体層を電気抵抗領域として用いることもできる。
【００１５】
図３には本発明を実施した半導体素子の平面図を示す。図３（ａ）は制御電極３３を半導体素子のコーナー部分に配置し、制御配線膜２２との間に電気抵抗領域４０を設けた場合の平面図である。図３（ｂ）は制御電極３３を半導体素子のある一辺の中央部に配置した場合の平面図である。図３（ｃ）は制御電極３３を中央に配置した場合の平面図である。この時、制御電極に入力されたゲート信号は各電気抵抗領域を通って制御配線によりチップ全体へ分配され、半導体能動領域に伝えられる。
【００１６】
図１は本発明を実施したプレーナ型ＩＧＢＴの断面・鳥瞰図であり、電気抵抗領域４０と制御配線膜２２とが接続される複数の箇所同士を、Ｓｉを１〜３wt％含有するＡｌ合金により構成される低抵抗配線４１で一体に接続したものである。この場合ゲート信号は、電気抵抗領域４０から各制御配線膜２２に伝わる際に低抵抗配線４１で一旦均一化されるため、各半導体能動領域の動作もより均一化することができる。
【００１７】
図１の等価回路を図４（ａ），図４（ｂ）に、図２の等価回路を図４（ｃ）に示す。ｒｇ１，ｒｇ２，ｒｇ３，ｒｇ４はそれぞれ電気抵抗領域を表す。また、ｉｇｂｔ１，ｉｇｂｔ２，ｉｇｂｔ３，ｉｇｂｔ４は、同一チップ内にあってそれぞれ主としてｒｇ１，ｒｇ２，ｒｇ３，ｒｇ４を通るゲート信号により制御される単位素子の集まりを表す。図２のように低抵抗配線４１が無い場合、例えば製造条件の変動などでｒｇ１が規定の抵抗値から変化した場合には、ｒｇ１が接続されるｉｇｂｔ１ではほかのｉｇｂｔ２，ｉｇｂｔ３，ｉｇｂｔ４と比べて動作にばらつきが生じることがある。一方、図１のように低抵抗配線４１を設けた場合、図４（ａ）のように高電気抵抗領域ｒｇ１，ｒｇ２，ｒｇ３，ｒｇ４は図１に示した低抵抗配線４１により一旦並列接続された後、それぞれのｉｇｂｔ１，ｉｇｂｔ２，ｉｇｂｔ３，ｉｇｂｔ４に分配して接続される。この場合、例えばｒｇ１の抵抗値が規定からずれていたとしてもｉｇｂｔ１の動作だけがずれることはなく、各ｉｇｂｔには合成抵抗Ｒｇが接続されたものとして動作する（図４（ｂ））ため、半導体素子内部での動作不均一を抑制することができる。
【００１８】
図５には本発明を実施した半導体素子の平面図を示す。図５（ａ）は制御電極３３を半導体素子のコーナー部分に配置し、制御配線膜２２との間に電気抵抗領域４０を設けた場合の平面図である。図５（ｂ）は制御電極３３を半導体素子のある一辺の中央部に配置した場合の平面図である。図５（ｃ）は制御電極を中央に配置した場合の平面図である。また、図５（ｄ）のように低抵抗配線４１と制御電極３３の間の全体に電気抵抗領域４０を設けた場合でも、一旦低抵抗配線４１でゲート信号が均一化される。さらに、図５（ｅ）のように電気抵抗領域４０が一つだけの場合でも、低抵抗配線４１によってゲート信号が均一化され、これに接続される複数の制御配線膜２２にも均等に信号が伝えられ、不均一動作が改善できる。なお、低抵抗配線の電気抵抗配線と制御電極との間の電気抵抗値より小さくする。
【００１９】
次に電気抵抗領域の配置に関しての実施例について説明する。図３に示すように、半導体素子の半導体能動領域や制御電極，制御配線の配置はその形状あるいは電気的にみて、ある対称性を持たせるのが一般的である。これは半導体素子製造用のホトマスク設計を容易にするほか、複数の半導体素子を一枚のウエハから効率よく得るためには必然的にチップ形状が正方形或いは長方形となるため、この半導体素子内部を均一動作させるためには、外形に沿った対称構造とすることが好ましいためである。電気抵抗領域の配置に関しては、例えば半導体能動領域配置の対称軸に対して、電気抵抗領域も同様に対称配置とすることが、半導体素子内部の均一動作に有効で好ましい。これにより制御電極から半導体能動領域の最遠部分までの距離を揃えること等で半導体素子内部の均一動作を図ることができる。図３（ａ）は斜め方向に対称軸がある場合の配置例を示した。図３（ｂ）は横方向に対称軸がある場合の配置例、図３（ｃ）は縦横に対称軸がある場合の配置例を示している。
【００２０】
なお、電気抵抗領域は対称軸を中心にして相対する位置にそれぞれ配置することが、素子内部の均一動作に有効であり、よって、高電気抵抗領域の数は対称軸の数に応じて２，４，６・・・と、２の倍数だけ配置することがより好ましい。
【００２１】
図６は本発明の他の実施例を示したもので、特に制御電極周辺の構造について述べる。本実施例は電気抵抗領域の形状に関するものである。電気抵抗領域４０に所望の抵抗値を持たせるため、細長い形状にする場合がある。しかし、例えば制御電極３３から放射状に接続した場合には半導体能動領域内に深く入り込むことになる等、構造が複雑となる。そこでこの細長い抵抗体を、図６（ａ）のように長手方向が制御電極３３の外周形状に沿うように配置することで、電気抵抗領域４０を制御電極３３の近傍に集約できるため、半導体能動領域の構造も簡略化されて、設計が容易となる利点がある。また、前述のように電気抵抗領域の対称性を考慮して、図６（ｂ）のように、電気抵抗領域４０の長手方向の中央部と制御電極３３とを導体により電気的に接続することも好ましい。
【００２２】
次に複数の半導体素子を並列に接続する実施例について説明する。本実施例は電気抵抗領域の抵抗値設計に関するものである。図７は２つのＩＢＧＴチップ（点線内）が並列接続される場合で、それぞれの制御電極及びエミッタ電極同士が短絡されている場合の等価回路を示している。Ｒｇは半導体素子に内蔵される電気抵抗領域の抵抗値、Ｃｉｅは半導体素子のゲート・エミッタ間入力容量、Ｌはそれぞれの半導体素子間のエミッタ配線のインダクタンスである。一般に抵抗Ｒ，キャパシタＣ，インダクタＬの直列回路では
Ｒ2＜４Ｌ／Ｃ …（１）
という関係が成り立つ場合には電流の振動が生じる。ここではゲート電流の振動を引き起こすことになり、これが半導体素子の誤動作や、破壊につながる。このゲート電流振動の防止策としては、
Ｒ2＞４Ｌ／Ｃ …（２）
の関係を満たすようにして、電流振動が生じないようにする必要がある。
【００２３】
図７の回路の場合、式（２）のＲ＝２・Ｒｇ，Ｃ＝Ｃｉｅ／２、とおいて、
(２・Ｒｇ)２＞４Ｌ／(Ｃｉｅ／２) …（３）
Ｒｇ2＞２（Ｌ／Ｃｉｅ） …（４）
従って、この（４）を満たすＲｇ値を有する電気抵抗領域を各々の半導体素子内部の制御電極と制御配線との接続間に設けることにより、複数チップ間でのゲート電流振動を起こさず、高信頼で良好な特性を有する半導体素子を低コストで得ることが可能となる。
【００２４】
上記各実施例によれば半導体素子に電気抵抗領域を内蔵することで、外付けチップ抵抗は不要とすることができる。しかし、図８のように外付けチップ抵抗Ｒｇｅと電気抵抗領域Ｒｇを同時に接続して各半導体素子のゲート抵抗値を同等に揃えて、動作の均一化を図ることも有効である。この時、例えばトリミング等が可能な外付け抵抗体を設けて抵抗値の微調整を行えば、より動作の均一性が向上した半導体装置を得ることができる。
【００２５】
なお、ここまでの実施例では半導体素子としてＩＧＢＴを中心に述べてきたが、本発明は他のＭＯＳ制御型半導体素子等について適用した場合にも同様の効果を得ることができ、ＩＧＢＴに制限されるものではない。
【００２６】
次に、図９には本発明により得られた複数の半導体素子を、平型半導体装置に組み込み、この平型半導体装置を主変換素子として電力変換器に応用した場合の例を、１ブリッジ分の構成回路図で示す。主変換素子となるＩＧＢＴ５１とダイオード５２が逆並列に配置され、これらがｎ個直列に接続された構成となっている。図中の各ＩＧＢＴ５１とダイオード５２は、本発明によるそれぞれ多数の半導体素子を並列実装した平型半導体装置を示している。なお、図９のような逆導通型ＩＧＢＴ平型半導体装置の場合には図中のＩＧＢＴ５１とダイオード５２がまとめて一つのパッケージに収められた形となる。これにスナバ回路５３、及び限流回路が設けてある。
【００２７】
図１０は、図９の３相ブリッジを４多重した自励式変換器の構成を示したものである。本発明の半導体装置は、複数個をその主電極板外側と面接触する形で水冷電極を挟んで直列接続するスタック構造と呼ぶ形に実装され、スタック全体を一括で加圧する。また、平型半導体装置のみでなくモジュール型と呼ばれる実装形態による半導体装置としてももちろん可能である。モジュール型半導体装置の場合には上記装置間は直列接続より、むしろ並列接続の方が好ましい。
【００２８】
本発明の半導体装置は、上記の例に限らず広く各種変換器に用いられる。特に平型半導体装置は、電力系統に用いられる自励式大容量変換器の他、ミル用変換器として用いられる大容量変換器等に適しており、また、可変速揚水発電，ビル内変電所設備，電鉄用変電設備，ナトリウム硫黄（ＮａＳ）電池システム，車両等の変換器にも用いることができる。一方、モジュール型半導体装置は車両，電鉄用地上設備，鉄鋼などの産業用大型変換器や、中・小型容量の変換器を用いる家電機器，自動車などあらゆる分野で広く用いることができる。
【００２９】
【発明の効果】
本発明によれば、均一動作性が向上した半導体素子を得ることができる。
【図面の簡単な説明】
【図１】本発明の第２の実施例の部分鳥瞰図。
【図２】本発明の第１の実施例の部分鳥瞰図。
【図３】本発明の第１の実施例の平面図。
【図４】本発明の第１の実施例及び第２の実施例の等価回路図。
【図５】本発明の第２の実施例の平面図。
【図６】本発明の第３の実施例の平面図。
【図７】二つの半導体素子を並列接続したときの等価回路図。
【図８】本発明の実施例における二つの半導体素子を並列接続したときの等価回路図。
【図９】本発明の第５の実施例の等価回路図。
【図１０】本発明の半導体装置を用いた１ブリッジ分の構成回路図。
【符号の説明】
１…ｎ型半導体基板、２…ｐ導電型半導体層、３…裏面電極膜、１１…ｐ導電型半導体層、１２…ｎ型半導体層、１３…ｐ+型半導体層、１４…ｎ+型半導体層、２１…ゲート酸化膜、２２…制御配線膜、２３…層間絶縁膜、２４…フィールド酸化膜、３０…エミッタ電極膜、３１…金属層、３２…制御配線電極膜、３３…制御電極、４０…電気抵抗領域、４１…低抵抗配線、５１…ＩＧＢＴ、５２…ダイオード、５３…スナバ回路、６０…半導体能動領域、６１…ターミネーション領域。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor element, and more particularly to a semiconductor element excellent in uniform switching operation, a semiconductor device using the same, and a power converter.
[0002]
[Prior art]
In recent years, application of semiconductor power devices to inverter devices and the like has been promoted in order to promote energy saving and the like. In particular, development of semiconductor devices having high withstand voltage performance has been promoted, and recently, semiconductor devices such as insulated gate bipolar transistors (hereinafter referred to as IGBT) and MOSFETs are widely used. Further, in order to improve the current capacity of a semiconductor device, a desired large current capacity is obtained by connecting a plurality of the above semiconductor elements in parallel.
[0003]
When a plurality of semiconductor elements are connected in parallel as described above, if there is a variation in characteristics between the semiconductor elements, uniform operation of the elements is difficult, and element destruction occurs. In response to these problems, Japanese Patent No. 02608451 discloses a method in which an external chip resistor is connected to a control terminal to achieve uniform operation of a semiconductor element. Further, although the control electrodes are connected in parallel, the control current oscillation is transiently generated by the inductance of the wiring during the switching operation, and the malfunction of the element or the destruction of the element in the worst case occurs. In order to suppress this, an external chip resistor is connected between the control electrode of the element and the external terminal.
[0004]
[Problems to be solved by the invention]
In the above case, when increasing the capacity of a semiconductor device, the number of external chip resistors connected to each semiconductor element increases as the number of semiconductor elements connected in parallel increases, which complicates the manufacturing process. There was a problem that the cost increased.
[0005]
The present invention has been made in consideration of the above-mentioned problems, and is a highly reliable semiconductor that stabilizes the switching operation at the time of parallel connection of a plurality of semiconductor elements and suppresses non-uniform operation inside the semiconductor elements. It is an object to provide an element, a semiconductor device using the element, and a power converter.
[0006]
[Means for Solving the Problems]
In the semiconductor device according to the present invention, a gate resistor having the same effect as the external chip resistor is built in the semiconductor device.
[0007]
More specifically, on one main surface of the semiconductor substrate, a semiconductor active region involved in the energization operation of the semiconductor element, a control wiring that is insulated from the semiconductor substrate and controls the semiconductor active region, and the control wiring and the electrical And a control electrode provided for connecting to an external control terminal. Further, the resistance value on the electric resistance region side when the electric resistance region is provided between the control wiring and the control electrode and the connection position between the electric resistance region and the control wiring is used as a reference is the maximum on the control wiring side. The structure is larger than the wiring resistance value.
[0008]
Furthermore, it is more preferable in terms of uniform operation inside the semiconductor to have a structure in which one end of the electric resistance region is connected to the control electrode and the other end is connected to a plurality of control wiring end portions via low resistance wiring. .
[0009]
According to the present invention, by incorporating a gate resistor inside a semiconductor element, nonuniform operation between the semiconductor elements can be suppressed. Also, the uniformity of the operation inside the semiconductor element is improved.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following examples.
[0011]
FIG. 2 is a partial cross-sectional view and a bird's eye view of a planar IGBT implementing the present invention. A p-conductivity type semiconductor layer 11 and an n-type semiconductor layer 12 are formed on one surface of an n-type semiconductor substrate 1 made of silicon. On the surface of the n-type semiconductor substrate 1, a gate oxide film 21 made of silicon oxide (SiO 2 ) and polycrystalline silicon are sandwiched between adjacent p-type semiconductor layers 11. A control wiring film 22 is formed. An interlayer insulating film 23 is formed of phosphorus glass (PSG) so as to cover the entire surface of the gate oxide film 21 and the control wiring film 22. Further, an emitter electrode film 30 made of an Al alloy containing 1 to 3 wt% of Si is formed so as to be in contact with the exposed surfaces of the p-conductivity type semiconductor layer 11 and the n-type semiconductor layer 12. Here, a portion connected to the emitter electrode film and contributing to the energization operation of the semiconductor element is referred to as a semiconductor active region.
[0012]
An annular p + type semiconductor layer 13 and an n + type semiconductor layer 14 are formed so as to surround these regions. On the surface of the n-type semiconductor substrate 1, a field oxide film 24 made of SiO 2 is formed adjacently between the p + -type semiconductor layer 13 and the n + -type semiconductor layer 14. Further, metal layer 31 is formed of an Al alloy containing 1 to 3 wt% of Si so as to be in contact with p + type semiconductor layer 13 and n + type semiconductor layer 14 between field oxide films 24. These areas are particularly called termination areas.
[0013]
Further, an opening is provided in a part of the interlayer insulating film 23 covering the control wiring film 22, and Si is 1 to 3 wt so as to be insulated from the adjacent emitter electrode film and connected to the exposed part of the control wiring film 22. The control wiring electrode film 32 is formed of an Al alloy containing%. The portion of the control wiring film 22 to which the control wiring electrode film 32 is connected has a lower wiring resistance than that of the other portions. Therefore, the control wiring film 22 is formed in the semiconductor active region at a predetermined interval, and the entire semiconductor active region is formed. The transmission of signals to the unit elements becomes even. The control wiring for controlling the operation of the semiconductor region may have a composite structure of the control wiring film 22 and the control wiring electrode film 32. Further, in order to connect the control wiring film 22 and the external terminal, the adjacent emitter electrode film is insulated and the control electrode 33 is formed of an Al alloy containing 1 to 3 wt% of Si. Further, an electrical resistance region 40 made of polycrystalline silicon is connected between the control electrode 33 and the control wiring film 22. Further, the other surface of the n-type semiconductor substrate 1 has a p-conductivity-type semiconductor layer 2, and a back electrode film 3 is formed on the exposed surface of the p-conductivity-type semiconductor layer 2. Yes. Here, in this embodiment, the electric resistance regions 40 are individually provided and formed. However, for example, a part of the control wiring film 22 not connected to the control wiring electrode film 32 may be used. In this embodiment, when the connection position between the electric resistance region 40 and the control wiring film 22 is set as a reference position, the electric resistance value up to the control electrode 33 is larger than the maximum wiring resistance value of the control wiring film 22. The electric resistance region 40 is provided so as to be. Here, the wiring resistance value is an electric resistance value of the control wiring film 22 between the reference position and a position where the active region is present.
[0014]
In this way, by creating the electrical resistance region in the semiconductor element, there is no increase in the number of mounting steps for external parts, and no external chip resistance parts are required, so that a semiconductor element excellent in parallel operation can be obtained at low cost. be able to. When polycrystalline silicon is used as the material of the electric resistance region, a desired resistance value can be obtained by adjusting the shape such as the width and thickness of the electric resistance region. In addition, silicide-based materials and the like TiSi 2, MoSi 2, WSi 2 , it is also possible to use a RuO 2, SnO 2, Ta- N, ceramic material such as Ta-Si. Furthermore, a semiconductor layer formed by diffusing impurities in a semiconductor substrate can be used as the electric resistance region.
[0015]
FIG. 3 shows a plan view of a semiconductor device embodying the present invention. FIG. 3A is a plan view in the case where the control electrode 33 is disposed at the corner portion of the semiconductor element and the electric resistance region 40 is provided between the control wiring film 22 and the control electrode 33. FIG. 3B is a plan view in the case where the control electrode 33 is arranged at the center of one side of the semiconductor element. FIG. 3C is a plan view when the control electrode 33 is arranged at the center. At this time, the gate signal input to the control electrode is distributed to the entire chip by the control wiring through each electric resistance region and transmitted to the semiconductor active region.
[0016]
FIG. 1 is a cross-sectional / bird's-eye view of a planar IGBT embodying the present invention, and a plurality of locations where an electric resistance region 40 and a control wiring film 22 are connected are composed of an Al alloy containing 1 to 3 wt% of Si. The low resistance wiring 41 is integrally connected. In this case, when the gate signal is transmitted from the electric resistance region 40 to each control wiring film 22, the gate signal is once made uniform by the low resistance wiring 41, so that the operation of each semiconductor active region can be made more uniform.
[0017]
The equivalent circuit of FIG. 1 is shown in FIGS. 4 (a) and 4 (b), and the equivalent circuit of FIG. 2 is shown in FIG. 4 (c). rg1, rg2, rg3, and rg4 each represent an electric resistance region. Further, igbt1, igbt2, igbt3, and igbt4 represent a group of unit elements that are mainly controlled by gate signals passing through rg1, rg2, rg3, and rg4 in the same chip. When there is no low resistance wiring 41 as shown in FIG. 2, for example, when rg1 changes from a prescribed resistance value due to a change in manufacturing conditions, the igbt1 to which rg1 is connected is compared with the other igbt2, igbt3, and igbt4. There may be variations in operation. On the other hand, when the low resistance wiring 41 is provided as shown in FIG. 1, the high electrical resistance regions rg1, rg2, rg3, and rg4 are once connected in parallel by the low resistance wiring 41 shown in FIG. After that, they are distributed and connected to the respective igbt1, igbt2, igbt3, and igbt4. In this case, for example, even if the resistance value of rg1 deviates from the specified value, only the operation of igbt1 does not deviate, and each igbt operates as if the combined resistor Rg is connected (FIG. 4B). It is possible to suppress nonuniform operation within the semiconductor element.
[0018]
FIG. 5 shows a plan view of a semiconductor device embodying the present invention. FIG. 5A is a plan view in the case where the control electrode 33 is disposed at the corner portion of the semiconductor element and the electric resistance region 40 is provided between the control wiring film 22 and the control electrode 33. FIG. 5B is a plan view in the case where the control electrode 33 is arranged at the center of one side of the semiconductor element. FIG. 5C is a plan view when the control electrode is arranged at the center. Further, even when the electrical resistance region 40 is provided between the low resistance wiring 41 and the control electrode 33 as shown in FIG. 5D, the gate signal is once made uniform by the low resistance wiring 41. Further, even when there is only one electric resistance region 40 as shown in FIG. 5 (e), the gate signal is made uniform by the low resistance wiring 41, and the signal is equally distributed to the plurality of control wiring films 22 connected thereto. Can be transmitted and non-uniform operation can be improved. Incidentally, smaller than the electric resistance between the electrical resistance wire of low resistance wiring and the control electrode.
[0019]
Next, an embodiment regarding the arrangement of the electric resistance region will be described. As shown in FIG. 3, the arrangement of the semiconductor active region, the control electrode, and the control wiring of the semiconductor element generally has a certain symmetry in view of its shape or electrical. In addition to facilitating the design of a photomask for manufacturing semiconductor elements, the chip shape is necessarily square or rectangular in order to efficiently obtain multiple semiconductor elements from a single wafer. This is because it is preferable to have a symmetrical structure along the outer shape in order to operate. With respect to the arrangement of the electric resistance regions, for example, the electric resistance regions are preferably arranged symmetrically with respect to the symmetry axis of the semiconductor active region arrangement, which is effective and preferable for uniform operation inside the semiconductor element. Thereby, uniform operation inside the semiconductor element can be achieved by equalizing the distance from the control electrode to the farthest part of the semiconductor active region. FIG. 3A shows an arrangement example in the case where there is an axis of symmetry in the oblique direction. FIG. 3B shows an arrangement example in the case where the symmetry axis is in the horizontal direction, and FIG. 3C shows an arrangement example in the case where the symmetry axis is in the vertical and horizontal directions.
[0020]
In addition, it is effective for the uniform operation inside the element that the electric resistance regions are arranged at opposite positions around the symmetry axis. Therefore, the number of the high electric resistance regions is 2 depending on the number of the symmetry axes. 4, 6... And a multiple of 2 are more preferable.
[0021]
FIG. 6 shows another embodiment of the present invention. In particular, the structure around the control electrode will be described. The present embodiment relates to the shape of the electric resistance region. In order to give the electric resistance region 40 a desired resistance value, it may be formed in an elongated shape. However, for example, when connected radially from the control electrode 33, the structure becomes complicated, such as deeply entering the semiconductor active region. Therefore, by arranging this elongated resistor so that the longitudinal direction thereof follows the outer peripheral shape of the control electrode 33 as shown in FIG. 6A, the electric resistance region 40 can be concentrated in the vicinity of the control electrode 33. There is an advantage that the structure of the region is simplified and the design becomes easy. Further, in consideration of the symmetry of the electric resistance region as described above, the central portion in the longitudinal direction of the electric resistance region 40 and the control electrode 33 are electrically connected by a conductor as shown in FIG. 6B. Is also preferable.
[0022]
Next, an embodiment in which a plurality of semiconductor elements are connected in parallel will be described. The present embodiment relates to the resistance value design of the electric resistance region. FIG. 7 shows an equivalent circuit in the case where two IBGT chips (inside the dotted line) are connected in parallel, and the respective control electrodes and emitter electrodes are short-circuited. Rg is a resistance value of an electric resistance region built in the semiconductor element, Cie is an input capacitance between the gate and the emitter of the semiconductor element, and L is an inductance of the emitter wiring between the respective semiconductor elements. In general, in a series circuit of a resistor R, a capacitor C, and an inductor L, R 2 <4L / C (1)
When the above relationship is established, current oscillation occurs. Here, oscillation of the gate current is caused, which leads to malfunction or destruction of the semiconductor element. To prevent this gate current oscillation,
R 2 > 4L / C (2)
It is necessary to satisfy the above relationship so that current oscillation does not occur.
[0023]
In the case of the circuit of FIG. 7, R = 2 · Rg, C = Cie / 2 in the equation (2),
(2.Rg) 2> 4L / (Cie / 2) (3)
Rg 2 > 2 (L / Cie) (4)
Therefore, by providing an electric resistance region having an Rg value satisfying this (4) between the connection between the control electrode and the control wiring in each semiconductor element, the gate current does not oscillate between a plurality of chips and high reliability is achieved. Thus, a semiconductor element having good characteristics can be obtained at low cost.
[0024]
According to each of the above embodiments, an external chip resistor can be made unnecessary by incorporating an electric resistance region in the semiconductor element. However, as shown in FIG. 8, it is also effective to connect the external chip resistor Rge and the electric resistance region Rg at the same time so that the gate resistance values of the respective semiconductor elements are made equal to achieve uniform operation. At this time, for example, if an external resistor capable of trimming is provided and the resistance value is finely adjusted, a semiconductor device with more improved operation uniformity can be obtained.
[0025]
In the embodiments so far, IGBTs have been mainly described as semiconductor elements. However, the present invention can obtain the same effect when applied to other MOS control type semiconductor elements, and is limited to IGBTs. It is not something.
[0026]
Next, FIG. 9 shows an example in which a plurality of semiconductor elements obtained by the present invention are incorporated in a flat semiconductor device, and this flat semiconductor device is applied to a power converter as a main conversion element. This is shown in a circuit diagram of FIG. The IGBT 51 and the diode 52 serving as the main conversion elements are arranged in antiparallel, and n of them are connected in series. Each IGBT 51 and diode 52 in the figure represents a flat semiconductor device in which a large number of semiconductor elements according to the present invention are mounted in parallel. In the case of the reverse conducting IGBT flat semiconductor device as shown in FIG. 9, the IGBT 51 and the diode 52 in the drawing are collectively contained in one package. This is provided with a snubber circuit 53 and a current limiting circuit.
[0027]
FIG. 10 shows a configuration of a self-excited converter in which the three-phase bridge of FIG. 9 is multiplexed four times. The semiconductor device of the present invention is mounted in a form called a stack structure in which a plurality of semiconductor devices are connected in series with a water-cooled electrode sandwiched between them in surface contact with the outside of the main electrode plate, and pressurizes the entire stack at once. Of course, it is possible not only as a flat type semiconductor device but also as a semiconductor device with a mounting form called a module type. In the case of a module type semiconductor device, it is preferable to connect the devices in parallel rather than in series.
[0028]
The semiconductor device of the present invention is not limited to the above example and is widely used in various converters. In particular, flat semiconductor devices are suitable for self-excited large-capacity converters used in power systems, large-capacity converters used as converters for mills, etc. It can also be used for transformers for electric railways, sodium sulfur (NaS) battery systems, and converters for vehicles. On the other hand, the module type semiconductor device can be widely used in various fields such as vehicles, ground equipment for electric railways, industrial large converters such as steel, home appliances using medium / small capacity converters, and automobiles.
[0029]
【The invention's effect】
According to the present invention, a semiconductor device with improved uniform operability can be obtained.
[Brief description of the drawings]
FIG. 1 is a partial bird's-eye view of a second embodiment of the present invention.
FIG. 2 is a partial bird's-eye view of the first embodiment of the present invention.
FIG. 3 is a plan view of the first embodiment of the present invention.
FIG. 4 is an equivalent circuit diagram of the first and second embodiments of the present invention.
FIG. 5 is a plan view of a second embodiment of the present invention.
FIG. 6 is a plan view of a third embodiment of the present invention.
FIG. 7 is an equivalent circuit diagram when two semiconductor elements are connected in parallel.
FIG. 8 is an equivalent circuit diagram when two semiconductor elements in the embodiment of the present invention are connected in parallel.
FIG. 9 is an equivalent circuit diagram of a fifth embodiment of the present invention.
FIG. 10 is a configuration circuit diagram for one bridge using the semiconductor device of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... n-type semiconductor substrate, 2 ... p conductive type semiconductor layer, 3 ... Back electrode film, 11 ... p conductive type semiconductor layer, 12 ... n type semiconductor layer, 13 ... p + type semiconductor layer, 14 ... n + type semiconductor Layers 21... Gate oxide film 22. Control wiring film 23. Interlayer insulating film 24. Field oxide film 30. Emitter electrode film 31 Metal layer 32 Control wiring electrode film 33 Control electrode 40 DESCRIPTION OF SYMBOLS ... Electrical resistance area | region 41 ... Low resistance wiring, 51 ... IGBT, 52 ... Diode, 53 ... Snubber circuit, 60 ... Semiconductor active area | region, 61 ... Termination area | region.

Claims (6)

半導体基板の一方の主表面上に、
通電動作に関与する半導体能動領域と、
半導体基板から絶縁されて、前記半導体能動領域を制御するための制御配線膜、及び、前記制御配線膜の少なくとも一部に接続され、前記制御配線膜の配線抵抗を低くするための制御配線電極膜とで構成される制御配線と、
前記制御配線と電気的に接続され、外部制御端子と接続するために設けられた制御電極と、
前記制御配線と前記制御電極との間に電気的に接続される電気抵抗領域と、を有し、
前記電気抵抗領域が、前記電気抵抗領域と前記制御配線膜の接続位置を基準位置とした場合に、基準位置から前記制御電極までの電気抵抗値が、前記制御配線膜の最大の配線抵抗値よりも大きくなるように設けられていることを特徴とする半導体素子。On one main surface of the semiconductor substrate,
A semiconductor active region involved in energization operation;
A control wiring film that is insulated from the semiconductor substrate and controls the semiconductor active region, and a control wiring electrode film that is connected to at least a part of the control wiring film and reduces the wiring resistance of the control wiring film And control wiring composed of
A control electrode electrically connected to the control wiring and provided to connect to an external control terminal;
An electrical resistance region electrically connected between the control wiring and the control electrode,
When the electrical resistance region has a connection position between the electrical resistance region and the control wiring film as a reference position, the electrical resistance value from the reference position to the control electrode is greater than the maximum wiring resistance value of the control wiring film. the semiconductor device characterized in that is also provided to the magnitude Kunar so. 半導体基板の一方の主表面上に、
通電動作に関与する半導体能動領域と、
半導体基板から絶縁されて、前記半導体能動領域を制御するための制御配線膜、及び、前記制御配線膜の少なくとも一部に接続され、当該制御配線膜の配線抵抗を低くするための制御配線電極膜と、
前記制御配線膜と電気的に接続され、かつ外部制御端子と接続するために設けられた制御電極と、
前記制御配線膜と前記制御電極の間に電気的に接続される電気抵抗領域と、を有し、
さらに前記電気抵抗領域と前記制御配線膜とが接続される複数の箇所同士を低抵抗配線で一体に接続した半導体素子。On one main surface of the semiconductor substrate,
A semiconductor active region involved in energization operation;
A control wiring film that is insulated from the semiconductor substrate and controls the semiconductor active region, and a control wiring electrode film that is connected to at least a part of the control wiring film and reduces the wiring resistance of the control wiring film When,
A control electrode electrically connected to the control wiring film and provided to connect to an external control terminal;
An electrical resistance region electrically connected between the control wiring film and the control electrode,
Furthermore, a semiconductor element in which a plurality of locations where the electrical resistance region and the control wiring film are connected are integrally connected by a low resistance wiring. 半導体基板の一方の主表面上に、
通電動作に関与する半導体能動領域と、
半導体基板から絶縁されて、前記半導体能動領域を制御するための制御配線膜、及び、前記制御配線膜の少なくとも一部に接続され、当該制御配線膜の配線抵抗を低くするための制御配線電極膜と、
前記制御配線膜と電気的に接続され、かつ外部制御端子と接続するために設けられた制御電極と、
前記制御配線膜と前記制御電極の間に電気的に接続される複数の電気抵抗領域と、
前記制御配線膜と前記複数の電気抵抗領域との間において、前記複数の電気抵抗領域を接続する低抵抗配線と、を有する半導体素子。On one main surface of the semiconductor substrate,
A semiconductor active region involved in energization operation;
A control wiring film that is insulated from the semiconductor substrate and controls the semiconductor active region, and a control wiring electrode film that is connected to at least a part of the control wiring film and reduces the wiring resistance of the control wiring film When,
A control electrode electrically connected to the control wiring film and provided to connect to an external control terminal;
A plurality of electrical resistance regions electrically connected between the control wiring film and the control electrode;
A low resistance wiring connecting the plurality of electrical resistance regions between the control wiring film and the plurality of electrical resistance regions. 前記半導体基板の一方の主表面上に形成された、前記半導体能動領域と、前記制御配線と、
前記制御電極とが、
平面的に見て、少なくとも一つの対称軸を有する形状に配置されており、かつ前記電気抵抗領域が、前記対称軸に対して対称となる形状に配置されている請求項１乃至３のいずれか１項に記載の半導体素子。The semiconductor active region formed on one main surface of the semiconductor substrate, the control wiring,
The control electrode;
4. The device according to claim 1, wherein the electrical resistance region is disposed in a shape that is symmetrical with respect to the symmetry axis, when viewed in a plan view. 2. The semiconductor element according to item 1. 請求項１乃至４のいずれか１項に記載の半導体素子を複数個、外部配線を用いて並列接続し、
前記電気抵抗領域の抵抗値をＲｇ、前記半導体能動領域のゲート・エミッタ間入力容量をＣｉｅ、それぞれの隣接する二つの半導体素子のエミッタ電極間の配線インダクタンスをＬとした場合に、
Ｒｇ2＞２（Ｌ／Ｃｉｅ）
を満たす半導体装置。A plurality of semiconductor elements according to any one of claims 1 to 4 are connected in parallel using external wiring,
When the resistance value of the electrical resistance region is Rg, the gate-emitter input capacitance of the semiconductor active region is Cie, and the wiring inductance between the emitter electrodes of two adjacent semiconductor elements is L,
Rg 2 > 2 (L / Cie)
A semiconductor device that satisfies the requirements. 請求項１乃至４のいずれか１項の半導体素子または請求項５の半導体装置を主変換素子として用いた電力変換器。  A power converter using the semiconductor element according to claim 1 or the semiconductor device according to claim 5 as a main conversion element.
JP2000274991A 2000-09-06 2000-09-06 Semiconductor element and semiconductor device and converter using the same Expired - Fee Related JP4032622B2 (en)

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