JP2010135676A - Drive circuit for insulated-gate semiconductor device, and semiconductor device suitable for the drive circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a drive circuit for an insulated-gate semiconductor device capable of suppressing a turn-on surge and capable of reducing switching loss while maintaining a high withstand voltage. <P>SOLUTION: A control gate electrode 7b is provided on an outer edge of a cell region, and voltage can be applied to the control gate electrode 7b separately from a gate electrode 7a. Magnitude relationship of resistance values of resistors 32-34 in a passage from a supply side (power supply side) of IGBT drive circuit to the gate electrode 7a and the control gate electrode 7b is set so that the resistance value Rg2 of the second resistor 33 existing in the passage extending to the control gate electrode 7b is smaller than a total value Rg1+Rg3 of the resistance values Rg1 and Rg3 of the first and the third resistors 32 and 34 existing in the passage extending to the gate electrode 7a. When being turned on, the control gate electrode 7b is charged earlier than the gate electrode 7a. Thus, furious oscillation of the gate voltage and the electric current can be suppressed, and the turn-on surge can be suppressed. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a drive circuit for an insulated gate semiconductor device such as an insulated gate transistor (hereinafter referred to as IGBT) having a trench gate structure, and a semiconductor device suitable for the drive circuit.

  Conventionally, as an IGBT having a trench gate structure, there is one shown in Patent Document 1. The IGBT disclosed in this document has a structure in which an n-type emitter layer is selectively formed instead of all the p-type base regions located between a plurality of trench gates. With such a structure, the IGBT has a configuration in which a p-type base region connected to the emitter electrode and a dummy base region covered with an insulating film are separated by a trench gate.

In such a structure, in the ON state, discharge of holes to the emitter electrode is restricted, and holes are accumulated in the dummy base region. For this reason, conductivity modulation is promoted and a low on-voltage can be realized.
JP 2001-308327 A

  However, in the IGBT having the structure shown in Patent Document 1, minority carriers are rapidly accumulated in the drift layer (buffer layer) at the time of turn-on, and a large surge is generated by the minority carriers affecting the gate. There is.

  That is, when turning on, minority carriers are rapidly accumulated in the dummy base region, thereby causing a timing (so-called negative capacitance characteristic) at which the gate carrier shifts from charging to discharging. This causes a surge at turn-on (hereinafter referred to as turn-on surge) to increase. The location that causes vibration is the location facing the dummy base region of the trench where the gate electrode is disposed and the end of the trench, and it has been confirmed by experiment that the end of the trench is the main cause of vibration. Yes. This is presumably because minority carriers injected from the back surface of the outer peripheral region gather at a stretch toward the cell region. Due to such a turn-on surge, there is a problem that the switching loss increases.

  In order to suppress such a turn-on surge, the p-type diffusion layer deeper than the p-type base region in the outer peripheral region arranged so as to surround the cell region is sufficiently separated from the end portion of the trench in which the gate electrode is arranged. I think that. However, the breakdown voltage is reduced by that amount, and the turn-on surge can be reduced by separating the p-type diffusion layer and the like deeper than the p-type base region from the end portion of the trench. However, the minority carriers are accumulated in the end portion. Sudden potential changes remain.

  The present invention has been made in view of the above points, and it is an object of the present invention to provide a drive circuit for an insulated gate semiconductor device capable of suppressing a turn-on surge and reducing switching loss while maintaining a high breakdown voltage, and a semiconductor device suitable for the same. .

  In order to achieve the above object, according to the first aspect of the present invention, the first trench (4a) is disposed on the end side in the longitudinal direction so as to be separated from the first trench (4a), and the base region (3) is provided. A second trench (4b) formed so as to penetrate to the drift region (2), a second gate insulating film (6b) formed on the surface of the second trench (4b), and a second trench ( 4b), a predetermined voltage is applied to the first control gate electrode (7b) formed on the second gate insulating film (6b), and to the gate electrode (7a) and the first control gate electrode (7b). The second switch for extracting the charged carriers from the first switch element (30) for charging carriers and the gate electrode (7a) and the first control gate electrode (7b). Switching means (30, 31) having a switch element (31), and a first resistor (32) provided in a path for extracting carriers from the gate electrode (7a) through the second switch element (31) A second resistor (33) provided in a path for applying a predetermined voltage to the first control gate electrode (7b) through the first switch element (30), the first switch element (30), and the second switch element (31) provides a path for applying a predetermined voltage to the gate electrode (7a) through the first switch element (30), and from the first control gate electrode (7b) through the second switch element (31). And a third resistor (34) provided at a position serving as a path for extracting the carrier.

  In the first aspect of the present invention, the first switch element (30) is turned on and the second switch element (31) is turned off, whereby the predetermined voltage is changed to the gate electrode (7a) and the first control gate electrode (7b). And the carrier charged in the gate electrode (7a) and the first control gate electrode (7b) by turning off the first switch element (30) and turning on the second switch element (31). The resistance value (Rg2) of the second resistor (33) is the sum of the resistance value (Rg1) of the first resistor (32) and the resistance value (Rg3) of the third resistor (34). It is characterized by being made smaller than (Rg1 + Rg3).

  In such a drive circuit, a first control gate electrode (7b) is provided at the outer edge of the cell region, and voltage is applied to the first control gate electrode (7b) separately from the gate electrode (7a). I can do it. Then, regarding the magnitude relationship of the resistance values of the resistors (32 to 34) in the path from the supply side (power supply side) of the drive circuit to the gate electrode (7a) and the first control gate electrode (7b), the gate electrode (7a ) Present in the path leading to the first control gate electrode (7b) rather than the total value (Rg1 + Rg3) of the resistance values (Rg1, Rg3) of the first and third resistors (32, 34) existing in the path leading to The resistance value (Rg2) of the resistor (33) is made smaller. For this reason, at the time of turn-on, the first control gate electrode (7b) can be charged earlier than the gate electrode (7a). Thereby, it is possible to suppress the gate voltage / current from vigorously oscillating, and it is possible to suppress the turn-on surge.

  According to the second aspect of the present invention, the carrier is charged by applying a predetermined voltage to the gate electrode (7a), and the carrier charged in the gate electrode (7a) is extracted by stopping the application of the predetermined voltage. A predetermined voltage is applied to the first gate drive circuit (37) and the first control gate electrode (7b) to charge carriers, and the application of the predetermined voltage is stopped to charge the first control gate electrode (7b). And a second gate drive circuit (38) for extracting the generated carrier, and the second gate drive is more time consuming than the timing at which the first gate drive circuit (37) applies a predetermined voltage to the gate electrode (7a). The timing at which the circuit (38) applies the predetermined voltage to the first control gate electrode (7b) is earlier. It is characterized.

  Even in such a configuration, at the time of turn-on, the dummy gate electrode (7b) can be charged earlier than the gate electrode (7a). Thereby, the same effect as that of claim 1 can be obtained.

  In the invention according to claim 3, the first switch element (30) and the gate electrode (for charging carriers by applying a predetermined voltage to the gate electrode (7a) and the first control gate electrode (7b)). 7a) and switching means (30, 31) having a second switch element (31) for extracting carriers charged to the first control gate electrode (7b), and a second switch element (31) A predetermined voltage is applied to the first control gate electrode (7b) through the first resistor (32) provided in the path for extracting carriers from the gate electrode (7a) through the first switch element (30). The first switch is provided between the second resistor (33) provided in the path and the first switch element (30) and the second switch element (31). A position that becomes a path for applying a predetermined voltage to the gate electrode (7a) through the element (30) and a path for extracting carriers from the first control gate electrode (7b) through the second switch element (31). The zener diodes (39a, 39b) are arranged with the cathode facing the first switch element (30) and the anode facing the second switch element (31). (39b) is provided.

  Even in such a configuration, at the time of turn-on, the dummy gate electrode (7b) can be charged earlier than the gate electrode (7a). Thereby, the same effect as that of claim 1 can be obtained.

  In the invention according to claim 4, in the float layer (3b), the third trench (2) penetrating the base region (3) and reaching the drift layer (2) is arranged opposite to the first trench (4a). 4c), a third gate insulating film (6c) formed on the surface of the third trench (4c), and formed on the third gate insulating film (6c) in the third trench (4c), And a second control gate electrode (7c) electrically connected to one control gate electrode (7b).

  In such a structure provided with the second control gate electrode (7c), it is possible to prevent sudden minority carrier accumulation in the portion of the float layer (3b) facing the gate electrode (7a). Thereby, generation | occurrence | production of the turn-on surge which a more intense vibration of gate voltage and electric current can be suppressed. Therefore, the effect shown in claim 1 can be further obtained.

  In the invention according to claim 5, the region where the base region (3), the first trench (4a), the gate electrode (7a) and the emitter region (5) are arranged is defined as a cell region, and the periphery of the cell region is surrounded. As described above, the surface layer portion of the drift layer (2) is provided with the first conductivity type diffusion layer (20) deeper than the first conductivity type base layer (3), and the emitter electrode (13) serves as the first control. The gate electrode (7b) is formed so as to extend to the opposite side with respect to the cell region, and is electrically connected to the diffusion layer (20) on the outer peripheral side of the cell region from the first control gate electrode (7b). It is characterized by being.

  Thus, the emitter electrode (13) is electrically connected to the diffusion layer (20) of the first conductivity type deeper than the base layer (3) on the outer peripheral side of the cell region from the first control gate electrode (7b). Structure. For this reason, after minority carriers injected from the back surface of the outer peripheral region flow in the vertical direction toward the surface side of the outer peripheral region, and then flow in the lateral direction through the diffusion layer (20), before reaching the cell region The emitter electrode (13) can be extracted. Furthermore, by biasing the first control gate electrode (7b) located at the terminal portion of the gate electrode (7a), it becomes possible to further suppress the oscillation of the gate voltage.

  A sixth aspect of the present invention relates to an insulated gate semiconductor device suitable for the drive circuit according to the first aspect of the present invention. The application of the insulated gate semiconductor device to the drive circuit allows each of the above claims. The effect described in (1) can be obtained.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First Embodiment)
A first embodiment of the present invention will be described. FIG. 1 is a partial cross-sectional schematic diagram showing an IGBT portion in cross section in an IGBT drive circuit including the IGBT according to the present embodiment. FIG. 2 is a top surface layout diagram of a semiconductor device having an IGBT provided in the IGBT drive circuit shown in FIG. 1 corresponds to a cross section taken along the line AA′-A ″ of FIG. Further, FIG. 2 is not a cross-sectional view, but is partially hatched for easy understanding of the drawing. Hereinafter, the IGBT drive circuit according to the present embodiment will be described with reference to these drawings.

First, a configuration of a semiconductor device having an IGBT provided in the IGBT drive circuit will be described. As shown in FIG. 1, in the semiconductor device of this embodiment, a cell region provided with an IGBT and an outer peripheral region configured to surround the outer periphery thereof are formed. the p ⁺ -type collector layer 1 of a surface, a high concentration n-type impurity layer FS layer formed of the (field stop layer) with 2a is provided, Ya p ⁺ -type collector layer 1 on top of the FS layer 2a An n ⁻ type drift layer 2 having a lower impurity concentration than the FS layer 2a is provided. The FS layer 2a is not necessarily required, but is provided to improve the breakdown voltage and steady loss performance by preventing the depletion layer from spreading.

Such a structure in which the p ⁺ -type collector layer 1, the FS layer 2 a, and the n ⁻ -type drift layer 2 are sequentially arranged will be described later, for example, on the surface layer portion of the n-type FZ substrate constituting the n ⁻ -type drift layer 2. After the element structure is formed, the p ⁺ -type collector layer 1 and the FS layer 2a are formed by ion implantation and thermal diffusion of n-type impurities and p-type impurities after the rear surface side is shaved. Alternatively, the FS layer 2 a and the n ⁻ -type drift layer 2 can be epitaxially grown on the p-type semiconductor substrate constituting the p ⁺ -type collector layer 1.

A p-type base region 3 having a predetermined thickness is formed in the surface layer portion of the n ⁻ -type drift layer 2 in the cell region. Furthermore, a plurality of gate trenches (first trenches) 4a are formed so as to penetrate the p-type base region 3 and reach the n ⁻ -type drift layer 2, and the p-type base region 3 is formed by the trench 4a. It is separated into a plurality. Specifically, a plurality of trenches 4a are formed at equal intervals in the cross section on the right side of the drawing (A′-A ″ cross section in FIG. 2) in FIG. 1 in the depth direction of FIG. After the trenches 4a are extended in parallel in the (perpendicular to the plane of the drawing), as shown in FIG. 2, the two opposite ends are connected to each other to form an annular structure.

The p-type base region 3 is separated by each trench 4a. The p-type base region 3 disposed between each adjacent pair with each connected trench 4a as one set is a channel p layer 3a constituting the channel region, and is formed on the surface layer portion of the channel p layer 3a. , N ⁺ -type emitter region 5 is formed.

The n ⁺ -type emitter region 5 has a higher impurity concentration than the n ⁻ -type drift layer 2, terminates in the p-type base region 3, and is disposed in contact with the side surface of the trench 4 a. More specifically, the structure extends in a rod shape along the longitudinal direction of the trench 4a and terminates inside the tip of the trench 4a.

  Each trench 4a is configured by a gate insulating film (first gate insulating film) 6a formed so as to cover the inner wall surface of each trench 4a, doped Poly-Si formed on the surface of the gate insulating film 6a, and the like. Embedded with the gate electrode 7a. As shown in FIGS. 1 and 2, the gate electrode 7a is electrically connected to a gate wiring 11 to which a gate voltage is applied.

The p-type base region 3 surrounded by each set of trenches 4a is a float layer 3b in which the n ⁺ -type emitter region 5 is not formed. Each float layer 3b may be electrically connected to a float wiring (not shown), but is in a floating state in this embodiment.

  Further, a control gate trench (second trench) 4b is formed at the outer edge of the cell region, and each gate trench 4a is surrounded by the control gate trench 4b. In the present embodiment, one trench 4b is formed, and the p-type base region 3 is disposed on the side surface of each trench 4b. The trench 4b also includes a gate insulating film (second gate insulating film) 6b formed so as to cover the inner wall surface of each trench 4b, and doped poly-Si formed on the surface of the gate insulating film 6b. Embedded in a control gate electrode (first control gate electrode) 7b. As shown in FIGS. 1 and 2, the control gate electrode 7b is electrically connected to a control gate line 12 to which a control voltage is applied.

  The electrical connection with the gate electrode 7a and the control gate electrode 7b may be any structure as long as the wirings are not short-circuited. In this embodiment, the electrical connection is realized by the structure shown in FIG. is doing.

  That is, the surface of the channel p layer 3a and each float layer 3b is also covered with the insulating film 8 formed when the gate insulating films 6a and 6b are formed, and the doped poly- which constitutes the gate electrode 7a through the insulating film. By making Si 9a partially extend above the trench 4a, the gate electrode 7a is electrically connected to the doped Poly-Si 9a at the tip position of each trench 4a. Then, each part is insulated by the interlayer insulating film 10, a part of the doped Poly-Si 9 a is exposed through the contact hole 10 a formed in the interlayer insulating film, and the gate wiring 11 is disposed thereon, whereby each gate electrode 7a and the gate wiring 11 are electrically connected.

  Further, the doped poly-Si 9b constituting the control gate electrode 7b extends over a part of the trench 4b through the insulating film 8, so that the control gate electrode 7b is electrically connected to the doped poly-Si 9b. To be connected. Then, each part is insulated by the interlayer insulating film 10, a part of the doped Poly-Si 9 b is exposed through the contact hole 10 b formed in the interlayer insulating film 10, and the control gate wiring 12 is disposed thereon, The control gate electrode 7b and the control gate wiring 12 are electrically connected.

  The doped Poly-Si 9a connected to the gate electrode 7a and the doped Poly-Si 9b connected to the control gate electrode 7b are formed simultaneously, but are electrically separated by patterning as shown in FIG. It has become a state. Further, the layout of doped Poly-Si 7a connected to the gate electrode 7a is shown by a broken line in FIG. 1, but the doped Poly-Si 7a is adjacent to the control gate electrode 7b in a different cross section from FIG. Are also electrically connected to the end portions of the gate electrodes 7a.

The emitter electrode 13 is electrically connected to the n ⁺ -type emitter region 5 and the channel p layer 3a through a contact hole 10c formed in the interlayer insulating film 10. As shown in FIG. 2, the emitter electrode 13 is formed so as to substantially cover the entire cell region, and the gate wiring 11 and the control gate described above are formed on the remaining part of the cell region and a part of the outer peripheral region. Wiring 12 is arranged.

Furthermore, a collector electrode 14 is formed on the back side of the p ⁺ -type collector layer 1. In this way, the IGBT provided in the cell region is configured.

On the other hand, a p-type diffusion layer 20 deeper than the p-type base region 3 is formed in the outer peripheral region so as to surround the outer periphery of the cell region in the surface layer portion of the n ⁻ -type drift layer 2, and p A p-type guard ring layer 21 is formed as a multiple ring structure so as to surround the outer periphery of the mold diffusion layer 20.

  The p-type diffusion layer 20 is electrically connected to the emitter electrode 13 through a contact hole 10 d formed in the interlayer insulating film 10 so that carriers can be extracted through the emitter electrode 13. Each p-type guard ring layer 21 is electrically connected to an outer peripheral electrode 22 disposed corresponding to each p-type guard ring layer 21 through a contact hole 10 e formed in the interlayer insulating film 10. Yes. Each outer peripheral electrode 22 is electrically isolated from each other and has a multiple ring structure like the p-type guard ring layer 21.

  With the above structure, a semiconductor device having an IGBT is configured. The IGBT in the semiconductor device configured as described above is connected to the IGBT drive circuit shown in FIG. In FIG. 3, the IGBT and the control gate electrode are shown as an integrated symbol. That is, the capacitance is configured by disposing the gate insulating film 6b between the control gate electrode 7b and the gate electrode 7a. For this reason, the IGBT having the above-described structure is represented by using a symbol arranged in a state where a capacitance is arranged between the control gate electrode 7b and the gate electrode 7a.

  As shown in FIG. 3, the switch circuit corresponding to the switch means including the NPN transistor 30 and the PNP transistor 31 is connected to the first to third resistors 32 to 34 having resistance values Rg1 to Rg3. A gate drive circuit is configured. Specifically, the base terminals of the NPN transistor 30 and the PNP transistor 31 are electrically connected to each other, a predetermined voltage generated by the power source 35 is applied to the collector terminal of the NPN transistor 30, and the collector of the PNP transistor 31 A GND is connected to the terminal.

  The emitter terminal of the PNP transistor 31 is electrically connected to the gate line 11 via the first resistor 32 and the emitter terminal of the NPN transistor 30 is connected to the control gate line 12 via the second resistor 33. Are electrically connected. Further, a third resistor 34 is provided on the wiring connecting the emitter terminals of the NPN transistor 30 and the PNP transistor 31. The resistance values Rg1 to Rg3 of the first to third resistors 32 to 34 are values in consideration of the turn-on surge, and Rg2 <Rg1 + Rg3 and Rg1 <Rg2 + Rg3 are established. With such a circuit configuration, the IGBT drive circuit according to the present embodiment is configured.

  Next, the driving operation of the IGBT by the IGBT driving circuit of the present embodiment configured as described above will be described in comparison with a conventional IGBT driving circuit.

  FIG. 4 is a schematic cross-sectional view of a semiconductor device having a conventional IGBT. FIG. 5 is a top surface layout diagram of the semiconductor device having the IGBT shown in FIG. 4 corresponds to a cross section taken along line B-B′-B ″ in FIG. 5. Further, FIG. 5 is not a cross-sectional view, but is partially hatched for easy understanding of the drawing.

  As shown in FIGS. 4 and 5, the IGBT element structure is the same as that of the present embodiment, but the control gate electrode 7b is not provided. Further, although not shown in the figure for a conventional IGBT drive circuit, for example, a predetermined voltage generated by a power source is applied to the gate wiring 11 connected to each gate electrode 7a through an input resistor.

  FIG. 6 is a timing chart showing characteristic waveforms in each turn-on time zone of the conventional IGBT drive circuit. Hereinafter, the operation of the conventional IGBT drive circuit when it is turned on will be described with reference to FIG.

  First, before the time T0, a predetermined voltage generated by the power source is not applied to the gate electrode 7a of the IGBT, and the gate is off and no current flows between the collector and the emitter. From this state, when the predetermined voltage generated by the power source is applied at time T0, + carrier starts to be charged into the gate electrode 7a.

In the subsequent period from time T0 to time T1, the parasitic capacitance between the gate and the emitter is charged, and the portion of the p-type base region 3 facing the gate electrode 7a is depleted and heads for inversion.
Specifically, during the period from time T0 to time T1, a portion of the p-type base region 3 that is depleted and inverted by facing the gate electrode 7a is as shown in FIG. n ⁺ -type emitter region 5 is not present float layer 3b, (2) n ⁺ -type channel p layer 3a emitter region 5 is present, of the p-type base region 3 is absent (3) n ⁺ -type emitter region 5 There are three outer edge portions (portions adjacent to the outer peripheral region).

  At time T1, the portion of the p-type base region 3 facing the gate electrode 7a is inverted, and current starts to flow between the collector and the emitter.

  During the period from time T1 to time T2 after the current starts to flow, the gate-collector is charged. During this period, the gate voltage is ideally fixed at a constant voltage due to the capacitance variation between the gate and the collector.

  However, in the case of the conventional IGBT drive circuit, it is out of this ideal state and vibrates violently immediately after the time T1 when the current starts to flow. It is known that this is due to a sudden charge variation in the portion of the float layer 3b facing the gate electrode 7a. In addition to this, the present inventors have a sudden change in the terminal portion of the gate electrode 7a. It was found that there was a large amount due to a large charge variation.

Thereafter, at time T1, a large amount of holes are injected from the collector side at the same time as the collector-emitter current begins to flow, and a part of the portion of the float layer 3b facing the gate electrode 7a or the n ⁻ type drift layer 2 Is rapidly accumulated in the portion facing the gate electrode 7a. In the channel p layer 3a, holes are not accumulated because they pass through the emitter electrode 13. A large variation current is generated in the gate electrode 7a by a series of processes in which a large amount of holes are accumulated in a short time from the depleted state first, and the charging is changed to the discharging. This leads to severe vibration of the gate voltage / current.

  FIG. 7 is a graph showing the results of examining the change in surge voltage with respect to the distance D from the terminal portion of the gate electrode 7a to the p-type diffusion layer 20 deeper than the p-type base region 3. As shown in the figure, the surge voltage increases as the distance D decreases, and the surge voltage decreases as the distance D increases. Also from this experimental result, it can be confirmed that the terminal portion of the gate electrode 7a has a large effect on the surge voltage.

  That is, when the p-type diffusion layer 20 deeper than the p-type base region 3 is close to the terminal portion of the gate electrode 7a (when the distance D is small), the minority carriers injected from the back surface of the outer peripheral region are once on the surface of the outer peripheral region. Then, it flows along the p-type diffusion layer 20 deeper than the p-type base region 3 on the surface side, and flows toward the cell region. For this reason, it is considered that minority carriers tend to concentrate at the terminal portion of the gate electrode 7a. On the other hand, when the p-type diffusion layer 20 deeper than the p-type base region 3 is far from the terminal portion of the gate electrode 7a (when the distance D is large), minority carriers injected from the back surface of the outer peripheral region are extracted directly through the emitter electrode 12. It is. For this reason, minority carriers are relatively difficult to concentrate on the terminal portion of the gate electrode 7a. From these facts, it can be said that the minority carriers at the terminal portion of the gate electrode 7a are greatly effective as a cause of the occurrence of turn-on surge.

  As described above, in the conventional IGBT drive circuit, a turn-on surge in which the gate voltage / current vibrates vigorously occurs, causing problems such as an operation imbalance when the elements are used in parallel.

  On the other hand, the IGBT drive circuit of this embodiment operates as follows. FIG. 8 is a timing chart showing characteristic waveforms in each turn-on time zone of the IGBT drive circuit of the present embodiment. Hereinafter, with reference to this figure, the operation at the time of turn-on of the IGBT drive circuit of this embodiment will be described.

  First, since the NPN transistor 30 is turned off before time T0, a predetermined voltage generated by the power source 35 is not applied to the gate electrode 7a of the IGBT, and the collector-emitter current flows when the gate is off. Absent. From this state, when the NPN transistor 30 is turned on based on the gate drive voltage at time T0, a predetermined voltage generated by the power source 35 is applied, so that + carriers are supplied to the gate electrode 7a and the control gate electrode 7b. Both begin to be charged.

  At this time, the magnitude relationship between the resistance values of the resistors 32 to 34 in the path from the supply side (power supply side) of the IGBT drive circuit to the gate electrode 7a and the control gate electrode 7b exists in the path to the gate electrode 7a. 1, the resistance value Rg2 of the second resistor 33 existing in the path to the control gate electrode 7b is smaller than the total value Rg1 + Rg3 of the resistance values Rg1 and Rg3 of the third resistors 32 and 34 (Rg2 <Rg1 + Rg3). . For this reason, the control gate electrode 7b is charged earlier than the gate electrode 7a.

  In the subsequent period from time T0 to time T1, the gate electrode 7a is charged with respect to the parasitic capacitance between the gate and the emitter, and the portion of the channel p layer 3a facing the gate electrode 7a and the gate electrode of the float layer 3b The part facing the gate electrode 7a among the part facing the 7a and further the part located at the outer edge of the cell region in the p-type base region 3 is depleted and goes inversion.

  However, the depletion does not proceed as much as the channel p layer 3a and the float layer 3b in the portion facing the gate electrode 7a in the portion located at the outer edge portion of the cell region in the p-type base region 3, for the reason described later. The target hole is left.

  That is, the charge of the control gate electrode 7b progresses faster than the gate electrode 7a, and the charge is almost completed before reaching the time point T1 at which current starts to flow between the collector and the emitter. The positive charge to the control gate electrode 7b is a hole in the portion of the p-type base region 3 facing the control gate electrode 7b, and the outer edge of the cell region in the channel p layer 3a, the float layer 3b and the p-type base region 3. Of the portion located at, the portion is driven toward the portion facing the gate electrode 7a. Therefore, depletion of the portion of the p-type base region 3 located at the outer edge of the cell region facing the gate electrode 7a does not proceed as much as the channel p layer 3a and the float layer 3b, and relatively holes are left. It will be in the state.

  Due to the mutated current generated at this time, the gate electrode 7a is not only charged based on a predetermined voltage generated by the power source 35, but also has a discharge element, but gradually, over the process of progressing the charge of the control gate electrode 7b. The gate voltage / current does not vibrate vigorously because it is a mutated current.

  Next, at time T1, the channel p layer 3a in contact with the gate electrode 7a is inverted, and current starts to flow between the collector and the emitter. At the same time as the collector-emitter current starts to flow, a large amount of holes are injected from the collector side, and a part of the holes is formed in the portion facing the gate electrode 7a in the portion located at the outer edge of the cell region in the p-type base region 3. In the direction of accumulation, the portion facing the gate electrode 7a in the portion located at the outer edge of the cell region in the p-type base region 3 already has a certain amount of holes. Are relatively few.

  For this reason, in the IGBT drive circuit according to the present embodiment, a large variation current immediately after the time T1 as seen in the conventional IGBT drive circuit does not occur, and the oscillation of the gate voltage / current is suppressed.

  Therefore, in the IGBT drive circuit of the present embodiment, it is possible to suppress the occurrence of turn-on surge that causes severe vibration of the gate voltage and current, and to prevent problems such as operation imbalance even if the elements are used in parallel. It becomes possible to do.

  As described above, in the IGBT drive circuit according to the present embodiment, the control gate electrode 7b is provided at the outer edge of the cell region, and voltage can be applied to the control gate electrode 7b separately from the gate electrode 7a. I am doing so. Then, regarding the magnitude relationship of the resistance values of the resistors 32 to 34 in the path from the supply side (power supply side) of the IGBT drive circuit to the gate electrode 7a and the control gate electrode 7b, the first existing in the path to the gate electrode 7a. The resistance value Rg2 of the second resistor 33 existing in the path to the control gate electrode 7b is smaller than the total value Rg1 + Rg3 of the resistance values Rg1 and Rg3 of the third resistors 32 and 34. Therefore, at the time of turn-on, the control gate electrode 7b can be charged earlier than the gate electrode 7a. Thereby, it is possible to suppress the gate voltage / current from vigorously oscillating, and it is possible to suppress the turn-on surge.

  Thus, it becomes possible to make low switching loss by suppressing turn-on surge. In addition, such a turn-on surge is not suppressed because the p-type diffusion layer 20 or the like deeper than the p-type base region 3 is not sufficiently separated from the end portion of the trench 4a where the gate electrode 7a is disposed. Further, it is possible to suppress a decrease in breakdown voltage. Therefore, it is possible to provide an IGBT driving circuit that can suppress the turn-on surge and reduce the switching loss while maintaining a high breakdown voltage.

(Second Embodiment)
A second embodiment of the present invention will be described. In the IGBT drive circuit of this embodiment, the structure of the IGBT is changed from that of the first embodiment, and the other parts are the same as those of the first embodiment. Therefore, only the parts different from the first embodiment will be described. .

  FIG. 9 is a partial cross-sectional schematic diagram showing the IGBT portion in cross section in the IGBT drive circuit provided with the IGBT according to the present embodiment. FIG. 10 is a top surface layout diagram of a semiconductor device having an IGBT provided in the IGBT drive circuit shown in FIG. 9 corresponds to a cross section taken along line C-C′-C ″ in FIG. 10. In addition, FIG. 10 is not a cross-sectional view, but is partially hatched for easy understanding of the drawing. Hereinafter, the IGBT drive circuit according to the present embodiment will be described with reference to these drawings.

  As shown in FIG. 9, the semiconductor device having the IGBT according to the present embodiment has a control gate trench (third trench) 4c in the float layer 3b so as to face the gate electrode 7a, and a gate insulating film. A control gate electrode (second control gate electrode) 7c is provided via a (third gate insulating film) 6c. As shown in FIG. 10, each control gate electrode 7c is arranged in each set of gate electrodes 7a having a ring structure, and the terminal portions of adjacent control gate electrodes 7c are connected to each other to form a ring. It is structured. For this reason, a double ring structure is constituted by each set of gate electrodes 7a and the control gate electrode 7c disposed inside thereof.

  In such a structure provided with the control gate electrode 7c, it is possible to prevent a sudden accumulation of minority carriers in the portion of the float layer 3b facing the gate electrode 7a. Thereby, generation | occurrence | production of the turn-on surge which a more intense vibration of gate voltage and electric current can be suppressed. Therefore, it is possible to obtain more effects shown in the first embodiment.

(Third embodiment)
A third embodiment of the present invention will be described. In the IGBT drive circuit of this embodiment, the structure of the IGBT is changed from that of the first embodiment, and the other parts are the same as those of the first embodiment. Therefore, only the parts different from the first embodiment will be described. .

  FIG. 11 is a partial cross-sectional schematic diagram showing the IGBT portion in cross section in the IGBT drive circuit provided with the IGBT according to the present embodiment. FIG. 12 is a top surface layout diagram of the semiconductor device having the IGBT provided in the IGBT drive circuit shown in FIG. FIG. 11 corresponds to a cross section taken along line D-D′-D ″ in FIG. 12. Further, FIG. 12 is not a cross-sectional view, but is partially hatched for easy understanding of the drawing. Hereinafter, the IGBT drive circuit according to the present embodiment will be described with reference to these drawings.

  As shown in FIG. 11, the semiconductor device having the IGBT of this embodiment has a p-type diffusion layer deeper than the p-type base region 3 in the direction perpendicular to the longitudinal direction of the gate electrode 7a (the arrangement direction of the gate electrodes 7a). 20 is configured to be electrically connected to the emitter electrode 13. Further, as shown in FIGS. 11 and 12, the emitter electrode 13 is routed from the control gate wiring 12 to the outer peripheral side of the cell region. However, the structure is such that it is electrically connected to the p-type diffusion layer 20 deeper than the p-type base region 3 on the outer peripheral side of the cell region relative to the control gate electrode 7b. That is, the p-type diffusion layer 20 deeper than the p-type base region 3 and the emitter electrode 13 are connected on the terminal end side of the gate electrode 7a.

  As described above, in the IGBT having the conventional structure, when the p-type diffusion layer 20 deeper than the p-type base region 3 is close to the terminal portion of the gate electrode 7a (when the distance D is small), the IGBT is implanted from the back surface of the outer peripheral region. Minority carriers once flow in the vertical direction toward the surface side of the outer peripheral region, then flow through the p-type diffusion layer 20 deeper than the p-type base region 3 on the surface side, and flow toward the cell region. For this reason, minority carriers tend to concentrate on the terminal portion of the gate electrode 7a.

  On the other hand, in this embodiment, the emitter electrode 13 is electrically connected to the p-type diffusion layer 20 deeper than the p-type base region 3 on the outer peripheral side of the cell region than the control gate electrode 7b. Therefore, when minority carriers injected from the back surface of the outer peripheral region flow in the vertical direction toward the front surface side of the outer peripheral region, and then flow in the lateral direction through the p-type diffusion layer 20 deeper than the p-type base region 3. In addition, the emitter electrode 13 can be extracted before reaching the cell region. Furthermore, by biasing the control gate electrode 7b located at the end of the gate electrode 7a, it becomes possible to further suppress the gate voltage oscillation.

(Fourth embodiment)
A fourth embodiment of the present invention will be described. In the IGBT drive circuit of this embodiment, the structure of the IGBT is the same as that of the first to third embodiments, and the other circuit portions are different. Therefore, only the portions that are different from the first to third embodiments are described. explain.

  FIG. 13 is a diagram showing the IGBT drive circuit of the present embodiment. As shown in this figure, the IGBT drive circuit according to the present embodiment includes a first gate drive circuit 37 for applying a gate voltage to the gate electrode 7a via the first resistor 32, and a control gate electrode 7b. The second gate drive circuit 38 for applying a gate voltage via the two resistors 33 is provided. As described above, the first and second gate drive circuits 37 and 38 are separately provided, so that the gate voltage can be applied to the gate electrode 7a and the control gate electrode 7b at different timings. The resistance values of the first resistor 32 and the second resistor 33 are arbitrary, but in this embodiment, the resistance value Rg2 of the second resistor 33 is smaller than the resistance value Rg1 of the first resistor 32. As a result, the control gate electrode 7b is charged earlier than the gate electrode 7a.

  In addition to this structure, at the time of turn-on, the second gate drive circuit 38 applies a gate voltage at an earlier timing than the first gate drive circuit 37, and the control gate electrode 7b is earlier than the gate electrode 7a. I am trying to be charged. Thereby, similarly to the first to third embodiments, it is possible to suppress the gate voltage / current from vibrating violently and to suppress the turn-on surge.

  As described above, the first and second gate drive circuits 37 and 38 are separately provided in order to apply the gate voltage to the gate electrode 7a and the control gate electrode 7b, and the application timing of each gate voltage is made different. Thus, it is possible to obtain the same effects as those of the first to third embodiments.

(Fifth embodiment)
A fifth embodiment of the present invention will be described. The IGBT drive circuit of this embodiment is also the same as that of the first to third embodiments with respect to the structure of the IGBT, and is different with respect to the other circuit portions. Therefore, only the portions that are different from the first to third embodiments are described. explain.

  FIG. 14 is a diagram showing an IGBT drive circuit according to the present embodiment. As shown in this figure, in the IGBT drive circuit according to the present embodiment, instead of the third resistor 34 in the first embodiment, a Zener diode 39a reversely connected so that the anodes (or cathodes) face each other. , 39b. Specifically, the Zener diode 39a has the anode directed to the PNP transistor 31 side and the cathode directed to the NPN transistor 30 side, and the Zener diode 39b has the anode directed to the NPN transistor 30 side and the cathode directed to the PNP transistor 31. It is arranged with the side facing.

  In the IGBT drive circuit configured as described above, since the NPN transistor 30 is turned on at the time of turn-on, a predetermined voltage generated by the power source 35 is applied to the control gate electrode 7b via the second resistor 33, and the gate electrode 7a Is applied via the Zener diodes 39a and 39b and the first resistor 32. Therefore, the gate electrode 7a is charged only after the Zener breakdown voltage of the Zener diode 39b is exceeded, and the control gate electrode 7b can be charged earlier than the gate electrode 7a. Thereby, similarly to the first to third embodiments, it is possible to suppress the gate voltage / current from vibrating violently and to suppress the turn-on surge.

  As described above, by providing the Zener diodes 39a and 39b reversely connected between the NPN transistor 30 and the PNP transistor 31, it is possible to obtain the same effects as those of the first to third embodiments.

(Other embodiments)
In the first and fifth embodiments, the switching means is a push-pull type using a bipolar transistor including the NPN transistor 30 corresponding to the first switch element and the PNP transistor 31 corresponding to the second switch element. And explained. However, this is only an example of the switching means, and for example, a switching means that can be applied by a MOSFET or other methods may be adopted.

  In the above embodiment, an n-channel type IGBT in which the first conductivity type is p-type and the second conductivity type is n-type has been described as an example. However, the p-channel type in which the conductivity type of each part is inverted is described. The present invention can also be applied to an IGBT.

In the IGBT drive circuit provided with the IGBT according to the first embodiment of the present invention, FIG. FIG. 2 is a top surface layout diagram of a semiconductor device having an IGBT provided in the IGBT drive circuit shown in FIG. 1. It is the figure which showed the IGBT drive circuit provided with IGBT shown in FIG. It is a cross-sectional schematic diagram of a semiconductor device having a conventional IGBT. FIG. 5 is a top surface layout diagram of the semiconductor device having the IGBT shown in FIG. 4. It is the timing chart which showed the characteristic waveform in each time slot | zone of the turn-on of the conventional IGBT drive circuit. It is a graph which shows the result of having investigated the change of the surge voltage with respect to the distance D from the termination | terminus part of the gate electrode 7a to the p-type diffusion layer 20 deeper than the p-type base region 3. FIG. 4 is a timing chart showing characteristic waveforms in each turn-on time zone of the IGBT drive circuit shown in FIG. 3. In the IGBT drive circuit provided with IGBT according to the second embodiment of the present invention, it is a partial cross-sectional schematic view showing the IGBT portion in cross section. FIG. 10 is a top surface layout diagram of a semiconductor device having an IGBT provided in the IGBT drive circuit shown in FIG. 9. In the IGBT drive circuit provided with IGBT according to the third embodiment of the present invention, it is a partial cross-sectional schematic diagram showing the IGBT portion in cross section. FIG. 12 is a top surface layout diagram of a semiconductor device having an IGBT provided in the IGBT drive circuit shown in FIG. 11. It is the figure which showed the IGBT drive circuit concerning 4th Embodiment of this invention. It is the figure which showed the IGBT drive circuit concerning 5th Embodiment of this invention.

Explanation of symbols

1 p ⁺ type substrate 2 n ⁻ type drift layer 2a FS layer 3 p type base region 3a channel p layer 3b float layer 4a to 4c trench 5 n ⁺ type emitter region 6a to 6c gate insulating film 7a gate electrode 7b and 7c control gate Electrode 7c Control gate electrode 10 Interlayer insulating film 11 Gate wiring 12 Control gate wiring 13 Emitter electrode 14 Collector electrode 20 P-type diffusion layer 21 P-type guard ring layer 22 Peripheral electrode 30 NPN transistor 31 PNP transistor 32-34 First to third Each resistor 37, 38 First and second gate drive circuits 39a, 39b Zener diode

Claims (8)

A collector layer (1) of a first conductivity type;
A second conductivity type drift layer (2) disposed on the collector layer (1);
A first conductivity type base region (3) formed on the drift layer (2);
The first trench is formed to penetrate the base region (3) and reach the drift region (2), thereby separating the base region (3) into a plurality and extending in one direction as a longitudinal direction. (4a) and
A second conductivity type emitter region (formed in a part of the base region (3) separated into a plurality of regions and in contact with the side surface of the first trench (4a) in the base region (3)). 5) and
A first gate insulating film (6a) formed on the surface of the first trench (4a);
A gate electrode (7a) formed on the first gate insulating film (6a) in the first trench (4a);
An emitter electrode (13) electrically connected to the emitter region (5);
A collector electrode (14) formed on the back side of the semiconductor substrate (1),
Among the plurality of base regions (3), the one in which the emitter region (5) is formed functions as a channel layer (3a), and the one in which the emitter region (5) is not formed is a float layer (3b). ), And the channel layer (3a) and the float layer (3b) are repeatedly arranged in a certain arrangement order, and the drive circuit of the insulated gate semiconductor device,
On the end side in the longitudinal direction of the first trench (4a), the first trench (4a) is spaced apart from the first trench (4a), passes through the base region (3), and reaches the drift region (2). A formed second trench (4b);
A second gate insulating film (6b) formed on the surface of the second trench (4b);
A first control gate electrode (7b) formed on the second gate insulating film (6b) in the second trench (4b);
A first switch element (30) for charging a carrier by applying a predetermined voltage to the gate electrode (7a) and the first control gate electrode (7b), and the gate electrode (7a) and the first control gate electrode (7b) Switching means (30, 31) having a second switch element (31) for extracting charged carriers from one control gate electrode (7b);
A first resistor (32) provided in a path for extracting carriers from the gate electrode (7a) through the second switch element (31);
A second resistor (33) provided in a path for applying the predetermined voltage to the first control gate electrode (7b) through the first switch element (30);
A path for applying the predetermined voltage to the gate electrode (7a) through the first switch element (30) between the first switch element (30) and the second switch element (31); and A third resistor (34) provided at a position serving as a path for extracting carriers from the first control gate electrode (7b) through the second switch element (31);
By turning on the first switch element (30) and turning off the second switch element (31), the predetermined voltage is applied to the gate electrode (7a) and the first control gate electrode (7b). And pulling out the carriers charged in the gate electrode (7a) and the first control gate electrode (7b) by turning off the first switch element (30) and turning on the second switch element (31). Configured to do
The resistance value (Rg2) of the second resistor (33) is smaller than the total value (Rg1 + Rg3) of the resistance value (Rg1) of the first resistor (32) and the resistance value (Rg3) of the third resistor (34). A drive circuit for an insulated gate semiconductor device, wherein: A collector layer (1) of a first conductivity type;
A second conductivity type drift layer (2) disposed on the collector layer (1);
A first conductivity type base region (3) formed on the drift layer (2);
The first trench is formed to penetrate the base region (3) and reach the drift region (2), thereby separating the base region (3) into a plurality and extending in one direction as a longitudinal direction. (4a) and
A second conductivity type emitter region (formed in a part of the base region (3) separated into a plurality of regions and in contact with the side surface of the first trench (4a) in the base region (3)). 5) and
A first gate insulating film (6a) formed on the surface of the first trench (4a);
A gate electrode (7a) formed on the first gate insulating film (6a) in the first trench (4a);
An emitter electrode (13) electrically connected to the emitter region (5);
A collector electrode (14) formed on the back side of the semiconductor substrate (1),
Among the plurality of base regions (3), the one in which the emitter region (5) is formed functions as a channel layer (3a), and the one in which the emitter region (5) is not formed is a float layer (3b). ), And the channel layer (3a) and the float layer (3b) are repeatedly arranged in a certain arrangement order, and the drive circuit of the insulated gate semiconductor device,
On the end side in the longitudinal direction of the first trench (4a), the first trench (4a) is spaced apart from the first trench (4a), passes through the base region (3), and reaches the drift region (2). A formed second trench (4b);
A second gate insulating film (6b) formed on the surface of the second trench (4b);
A first control gate electrode (7b) formed on the second gate insulating film (6b) in the second trench (4b);
A first gate drive circuit that applies a predetermined voltage to the gate electrode (7a) to charge carriers, and stops application of the predetermined voltage to extract carriers charged in the gate electrode (7a). 37)
The carrier is charged by applying a predetermined voltage to the first control gate electrode (7b), and the carrier charged to the first control gate electrode (7b) is extracted by stopping the application of the predetermined voltage. A second gate drive circuit (38),
The second gate drive circuit (38) applies to the first control gate electrode (7b) more than the timing at which the first gate drive circuit (37) applies the predetermined voltage to the gate electrode (7a). A drive circuit for an insulated gate semiconductor device, wherein the timing for applying the predetermined voltage is earlier. A collector layer (1) of a first conductivity type;
A second conductivity type drift layer (2) disposed on the collector layer (1);
A first conductivity type base region (3) formed on the drift layer (2);
The first trench is formed to penetrate the base region (3) and reach the drift region (2), thereby separating the base region (3) into a plurality and extending in one direction as a longitudinal direction. (4a) and
A second conductivity type emitter region (formed in a part of the base region (3) separated into a plurality of regions and in contact with the side surface of the first trench (4a) in the base region (3)). 5) and
A first gate insulating film (6a) formed on the surface of the first trench (4a);
A gate electrode (7a) formed on the first gate insulating film (6a) in the first trench (4a);
An emitter electrode (13) electrically connected to the emitter region (5);
A collector electrode (14) formed on the back side of the semiconductor substrate (1),
Among the plurality of base regions (3), the one in which the emitter region (5) is formed functions as a channel layer (3a), and the one in which the emitter region (5) is not formed is a float layer (3b). ), And the channel layer (3a) and the float layer (3b) are repeatedly arranged in a certain arrangement order, and the drive circuit of the insulated gate semiconductor device,
On the end side in the longitudinal direction of the first trench (4a), the first trench (4a) is spaced apart from the first trench (4a), passes through the base region (3), and reaches the drift region (2). A formed second trench (4b);
A second gate insulating film (6b) formed on the surface of the second trench (4b);
A first control gate electrode (7b) formed on the second gate insulating film (6b) in the second trench (4b);
A first switch element (30) for charging a carrier by applying a predetermined voltage to the gate electrode (7a) and the first control gate electrode (7b), and the gate electrode (7a) and the first control gate electrode (7b) Switching means (30, 31) having a second switch element (31) for extracting charged carriers from one control gate electrode (7b);
A first resistor (32) provided in a path for extracting carriers from the gate electrode (7a) through the second switch element (31);
A second resistor (33) provided in a path for applying the predetermined voltage to the first control gate electrode (7b) through the first switch element (30);
A path for applying the predetermined voltage to the gate electrode (7a) through the first switch element (30) between the first switch element (30) and the second switch element (31); and Zener diodes (39a, 39b) provided at positions serving as paths for extracting carriers from the first control gate electrode (7b) through the second switch element (31),
The Zener diodes (39a, 39b) include a diode (39b) arranged with the cathode facing the first switch element (30) and the anode facing the second switch element (31). A drive circuit for an insulated gate semiconductor device, which is characterized. In the float layer (3b),
A third trench (4c) penetrating the base region (3) to reach the drift layer (2) and disposed opposite the first trench (4a);
A third gate insulating film (6c) formed on the surface of the third trench (4c);
A second control gate electrode (7c) formed on the third gate insulating film (6c) in the third trench (4c) and electrically connected to the first control gate electrode (7b); 4. The drive circuit for an insulated gate semiconductor device according to claim 1, further comprising: The region where the base region (3), the first trench (4a), the gate electrode (7a), and the emitter region (5) are disposed is defined as a cell region, and the drift is formed so as to surround the cell region. The surface layer portion of the layer (2) includes a first conductivity type diffusion layer (20) deeper than the base layer (3),
The emitter electrode (13) is formed so as to wrap around to the opposite side of the cell region with the first control gate electrode (7b) in between, and the emitter electrode (13) is closer to the cell region than the first control gate electrode (7b). 5. The drive circuit for an insulated gate semiconductor device according to claim 1, wherein the drive circuit is electrically connected to the diffusion layer on the outer peripheral side. 6. A collector layer (1) of a first conductivity type;
A second conductivity type drift layer (2) disposed on the collector layer (1);
A first conductivity type base region (3) formed on the drift layer (2);
The first trench is formed to penetrate the base region (3) and reach the drift region (2), thereby separating the base region (3) into a plurality and extending in one direction as a longitudinal direction. (4a) and
A second conductivity type emitter region (formed in a part of the base region (3) separated into a plurality of regions and in contact with the side surface of the first trench (4a) in the base region (3)). 5) and
A first gate insulating film (6a) formed on the surface of the first trench (4a);
A gate electrode (7a) formed on the first gate insulating film (6a) in the first trench (4a);
An emitter electrode (13) electrically connected to the emitter region (5);
A collector electrode (14) formed on the back side of the semiconductor substrate (1),
Among the plurality of base regions (3), the one in which the emitter region (5) is formed functions as a channel layer (3a), and the one in which the emitter region (5) is not formed is a float layer (3b). ), And the channel layer (3a) and the float layer (3b) are repeatedly arranged in a certain arrangement order,
On the end side in the longitudinal direction of the first trench (4a), the first trench (4a) is spaced apart from the first trench (4a), passes through the base region (3), and reaches the drift region (2). A formed second trench (4b);
A second gate insulating film (6b) formed on the surface of the second trench (4b);
An insulated gate semiconductor device comprising: a first control gate electrode (7b) formed on the second gate insulating film (6b) in the second trench (4b). In the float layer (3b),
A third trench (4c) penetrating the base region (3) to reach the drift layer (2) and disposed opposite the first trench (4a);
A third gate insulating film (6c) formed on the surface of the third trench (4c);
A second control gate electrode (7c) formed on the third gate insulating film (6c) in the third trench (4c) and electrically connected to the first control gate electrode (7b); The insulated gate semiconductor device according to claim 6, further comprising: The region where the base region (3), the first trench (4a), the gate electrode (7a), and the emitter region (5) are disposed is defined as a cell region, and the drift is formed so as to surround the cell region. The surface layer of the layer (2) includes a first conductivity type diffusion layer (20) deeper than the first conductivity type base layer (3),
The emitter electrode (13) is formed so as to wrap around to the opposite side of the cell region with the first control gate electrode (7b) in between, and the emitter electrode (13) is closer to the cell region than the first control gate electrode (7b). The insulated gate semiconductor device according to claim 6 or 7, wherein the insulated gate semiconductor device is electrically connected to the diffusion layer (20) on an outer peripheral side.

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