JP2019003997A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP2019003997A JP2019003997A JP2017116094A JP2017116094A JP2019003997A JP 2019003997 A JP2019003997 A JP 2019003997A JP 2017116094 A JP2017116094 A JP 2017116094A JP 2017116094 A JP2017116094 A JP 2017116094A JP 2019003997 A JP2019003997 A JP 2019003997A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- semiconductor device
- sealing
- film
- suction hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Moulds For Moulding Plastics Or The Like (AREA)
- Injection Moulding Of Plastics Or The Like (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Dicing (AREA)
Abstract
Description
Claims (2)
- 複数の半導体素子を基材に搭載して一括樹脂封止し、個片化する半導体装置の製造方法において、
半導体素子を基材に搭載した半導体素子搭載基材を準備する工程と、
第一の封止金型と、前記第一の封止金型と対になりキャビティに吸引孔が開口する第二の封止金型を準備する工程と、
前記吸引孔から吸引することにより、フィルムを前記キャビティの内面側に密着させ、前記半導体素子搭載基材を前記第一の封止金型と前記第二の封止金型で挟持し、前記キャビティ内に封止樹脂を充填し、樹脂封止部を形成する工程と、
前記樹脂封止部および前記基材を切断し、個々の半導体装置に個片化する工程と、を含み、
前記吸引孔を、前記樹脂封止部の切断予定領域内に配置することと、
前記封止樹脂部の切断予定領域を切断し、半導体装置に個片化することを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、前記吸引孔を隣接する半導体装置形成領域の切断予定領域に相応する前記キャビティの内面に開口するように配置し、前記吸引孔に前記フィルムを吸引させ、凸状に変形して形成される前記フィルムの凸部に充填される前記封止樹脂からなる樹脂突起部は、前記個片化のための切断により除去することを特徴とする半導体装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017116094A JP6984808B2 (ja) | 2017-06-13 | 2017-06-13 | 半導体装置の製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017116094A JP6984808B2 (ja) | 2017-06-13 | 2017-06-13 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2019003997A true JP2019003997A (ja) | 2019-01-10 |
JP6984808B2 JP6984808B2 (ja) | 2021-12-22 |
Family
ID=65006267
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2017116094A Active JP6984808B2 (ja) | 2017-06-13 | 2017-06-13 | 半導体装置の製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP6984808B2 (ja) |
-
2017
- 2017-06-13 JP JP2017116094A patent/JP6984808B2/ja active Active
Also Published As
Publication number | Publication date |
---|---|
JP6984808B2 (ja) | 2021-12-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20080286901A1 (en) | Method of Making Integrated Circuit Package with Transparent Encapsulant | |
TWI690096B (zh) | 導線架、封裝體及發光裝置、與該等之製造方法 | |
JP2008004570A (ja) | 樹脂封止型半導体装置の製造方法、樹脂封止型半導体装置の製造装置、および樹脂封止型半導体装置 | |
JP2015046578A (ja) | リードフレーム、樹脂付きリードフレーム、樹脂パッケージ、発光装置及び樹脂パッケージの製造方法 | |
US6645792B2 (en) | Lead frame and method for fabricating resin-encapsulated semiconductor device | |
US20170221802A1 (en) | Semiconductor Device Packaging Assembly, Lead Frame Strip and Unit Lead Frame with Molding Compound Channels | |
JP6984808B2 (ja) | 半導体装置の製造方法 | |
KR101598688B1 (ko) | 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스 | |
US20190371713A1 (en) | Semiconductor device and method of manufacturing the same | |
JP6856199B2 (ja) | 半導体装置の製造方法 | |
JP6034078B2 (ja) | プリモールドリードフレームの製造方法、および、半導体装置の製造方法 | |
JP2010141261A (ja) | 半導体装置の中間構造体及び中間構造体の製造方法 | |
TWI740350B (zh) | 半導體裝置之製造方法 | |
JP6981617B2 (ja) | 半導体装置の製造方法 | |
TWI689063B (zh) | 半導體裝置及其製造方法 | |
JP2011192683A (ja) | 半導体装置用パッケージ、半導体装置およびそれらの製造方法 | |
JP2020009976A (ja) | 樹脂封止金型および半導体装置の製造方法 | |
JP5660801B2 (ja) | 樹脂封止型半導体パッケージおよびその製造方法 | |
JP2012221964A (ja) | Ledパッケージ用基板の製造方法 | |
KR100526846B1 (ko) | 반도체패키지용 금형 | |
JP2008060193A (ja) | リードフレームおよびそれを用いた半導体装置の製造方法 | |
JP2008252005A (ja) | バリ取り方法および半導体装置の製造方法 | |
KR101816368B1 (ko) | 칩스케일 led 패키지 및 그 제조방법 | |
TWI502653B (zh) | 半導體晶片封裝方法 | |
KR200177346Y1 (ko) | 반도체 패키지(semiconductor package) |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20200430 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20210323 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20210325 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20210506 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20211026 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20211110 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6984808 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |