JP2018534847A - マルチレーンn階乗符号化通信システムおよび他のマルチワイヤ通信システム - Google Patents

マルチレーンn階乗符号化通信システムおよび他のマルチワイヤ通信システム Download PDF

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Publication number
JP2018534847A
JP2018534847A JP2018517310A JP2018517310A JP2018534847A JP 2018534847 A JP2018534847 A JP 2018534847A JP 2018517310 A JP2018517310 A JP 2018517310A JP 2018517310 A JP2018517310 A JP 2018517310A JP 2018534847 A JP2018534847 A JP 2018534847A
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JP
Japan
Prior art keywords
symbols
sequence
clock signal
clock
symbol
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Pending
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JP2018517310A
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English (en)
Japanese (ja)
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JP2018534847A5 (ru
Inventor
センゴク、ショウイチロウ
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Qualcomm Inc
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Qualcomm Inc
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Priority claimed from US14/875,592 external-priority patent/US9735948B2/en
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of JP2018534847A publication Critical patent/JP2018534847A/ja
Publication of JP2018534847A5 publication Critical patent/JP2018534847A5/ja
Pending legal-status Critical Current

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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/0008Synchronisation information channels, e.g. clock distribution lines
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/14Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/38Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40Transmitting circuits; Receiving circuits
    • H04L25/49Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP2018517310A 2015-10-05 2016-09-09 マルチレーンn階乗符号化通信システムおよび他のマルチワイヤ通信システム Pending JP2018534847A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/875,592 US9735948B2 (en) 2013-10-03 2015-10-05 Multi-lane N-factorial (N!) and other multi-wire communication systems
US14/875,592 2015-10-05
PCT/US2016/051131 WO2017062132A1 (en) 2015-10-05 2016-09-09 Multi-lane n-factorial encoded and other multi-wire communication systems

Publications (2)

Publication Number Publication Date
JP2018534847A true JP2018534847A (ja) 2018-11-22
JP2018534847A5 JP2018534847A5 (ru) 2019-09-26

Family

ID=56997556

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018517310A Pending JP2018534847A (ja) 2015-10-05 2016-09-09 マルチレーンn階乗符号化通信システムおよび他のマルチワイヤ通信システム

Country Status (8)

Country Link
EP (1) EP3360278A1 (ru)
JP (1) JP2018534847A (ru)
KR (1) KR102520096B1 (ru)
CN (1) CN108141346A (ru)
AU (1) AU2016335548A1 (ru)
BR (1) BR112018006874A2 (ru)
TW (1) TW201714443A (ru)
WO (1) WO2017062132A1 (ru)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11437998B2 (en) 2020-04-30 2022-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit including back side conductive lines for clock signals
CN113192950A (zh) * 2020-04-30 2021-07-30 台湾积体电路制造股份有限公司 集成电路及其制造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9711041B2 (en) * 2012-03-16 2017-07-18 Qualcomm Incorporated N-phase polarity data transfer
JP2013110554A (ja) * 2011-11-21 2013-06-06 Panasonic Corp 送信装置、受信装置及びシリアル伝送システム
US8996740B2 (en) * 2012-06-29 2015-03-31 Qualcomm Incorporated N-phase polarity output pin mode multiplexer
IN2015DN02408A (ru) * 2012-10-26 2015-09-04 Hitachi Int Electric Inc
US9363071B2 (en) * 2013-03-07 2016-06-07 Qualcomm Incorporated Circuit to recover a clock signal from multiple wire data signals that changes state every state cycle and is immune to data inter-lane skew as well as data state transition glitches
US9582457B2 (en) 2013-06-12 2017-02-28 Qualcomm Incorporated Camera control interface extension bus
US9755818B2 (en) * 2013-10-03 2017-09-05 Qualcomm Incorporated Method to enhance MIPI D-PHY link rate with minimal PHY changes and no protocol changes
US20150220472A1 (en) * 2014-02-05 2015-08-06 Qualcomm Incorporated Increasing throughput on multi-wire and multi-lane interfaces
CN106063181B (zh) 2014-03-06 2018-03-13 高通股份有限公司 接收机电路和在接收机电路上操作的方法

Also Published As

Publication number Publication date
KR20180066065A (ko) 2018-06-18
KR102520096B1 (ko) 2023-04-07
CN108141346A (zh) 2018-06-08
EP3360278A1 (en) 2018-08-15
WO2017062132A1 (en) 2017-04-13
TW201714443A (zh) 2017-04-16
AU2016335548A1 (en) 2018-04-12
BR112018006874A2 (pt) 2018-10-16

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