JP2018534847A - マルチレーンn階乗符号化通信システムおよび他のマルチワイヤ通信システム - Google Patents
マルチレーンn階乗符号化通信システムおよび他のマルチワイヤ通信システム Download PDFInfo
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- JP2018534847A JP2018534847A JP2018517310A JP2018517310A JP2018534847A JP 2018534847 A JP2018534847 A JP 2018534847A JP 2018517310 A JP2018517310 A JP 2018517310A JP 2018517310 A JP2018517310 A JP 2018517310A JP 2018534847 A JP2018534847 A JP 2018534847A
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- 230000006854 communication Effects 0.000 title claims abstract description 77
- 238000004891 communication Methods 0.000 title claims abstract description 77
- 230000007704 transition Effects 0.000 claims abstract description 158
- 238000000034 method Methods 0.000 claims abstract description 82
- 238000012545 processing Methods 0.000 claims description 113
- 230000011664 signaling Effects 0.000 claims description 80
- 230000002457 bidirectional effect Effects 0.000 claims description 44
- 230000001131 transforming effect Effects 0.000 claims description 2
- 230000005540 biological transmission Effects 0.000 description 54
- 230000006870 function Effects 0.000 description 37
- 230000008569 process Effects 0.000 description 20
- 238000010586 diagram Methods 0.000 description 12
- 230000002441 reversible effect Effects 0.000 description 10
- 230000003287 optical effect Effects 0.000 description 8
- 238000013461 design Methods 0.000 description 7
- 230000003111 delayed effect Effects 0.000 description 5
- 238000011084 recovery Methods 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 238000004590 computer program Methods 0.000 description 4
- 238000007726 management method Methods 0.000 description 4
- 238000013507 mapping Methods 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 238000011112 process operation Methods 0.000 description 4
- 230000001052 transient effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005070 sampling Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000001360 synchronised effect Effects 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 238000013459 approach Methods 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 230000007175 bidirectional communication Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000000284 extract Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000005022 packaging material Substances 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- RZILCCPWPBTYDO-UHFFFAOYSA-N fluometuron Chemical compound CN(C)C(=O)NC1=CC=CC(C(F)(F)F)=C1 RZILCCPWPBTYDO-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/14—Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Power Engineering (AREA)
- Spectroscopy & Molecular Physics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Dc Digital Transmission (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/875,592 US9735948B2 (en) | 2013-10-03 | 2015-10-05 | Multi-lane N-factorial (N!) and other multi-wire communication systems |
US14/875,592 | 2015-10-05 | ||
PCT/US2016/051131 WO2017062132A1 (en) | 2015-10-05 | 2016-09-09 | Multi-lane n-factorial encoded and other multi-wire communication systems |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2018534847A true JP2018534847A (ja) | 2018-11-22 |
JP2018534847A5 JP2018534847A5 (ru) | 2019-09-26 |
Family
ID=56997556
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2018517310A Pending JP2018534847A (ja) | 2015-10-05 | 2016-09-09 | マルチレーンn階乗符号化通信システムおよび他のマルチワイヤ通信システム |
Country Status (8)
Country | Link |
---|---|
EP (1) | EP3360278A1 (ru) |
JP (1) | JP2018534847A (ru) |
KR (1) | KR102520096B1 (ru) |
CN (1) | CN108141346A (ru) |
AU (1) | AU2016335548A1 (ru) |
BR (1) | BR112018006874A2 (ru) |
TW (1) | TW201714443A (ru) |
WO (1) | WO2017062132A1 (ru) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11437998B2 (en) | 2020-04-30 | 2022-09-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit including back side conductive lines for clock signals |
CN113192950A (zh) * | 2020-04-30 | 2021-07-30 | 台湾积体电路制造股份有限公司 | 集成电路及其制造方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9711041B2 (en) * | 2012-03-16 | 2017-07-18 | Qualcomm Incorporated | N-phase polarity data transfer |
JP2013110554A (ja) * | 2011-11-21 | 2013-06-06 | Panasonic Corp | 送信装置、受信装置及びシリアル伝送システム |
US8996740B2 (en) * | 2012-06-29 | 2015-03-31 | Qualcomm Incorporated | N-phase polarity output pin mode multiplexer |
IN2015DN02408A (ru) * | 2012-10-26 | 2015-09-04 | Hitachi Int Electric Inc | |
US9363071B2 (en) * | 2013-03-07 | 2016-06-07 | Qualcomm Incorporated | Circuit to recover a clock signal from multiple wire data signals that changes state every state cycle and is immune to data inter-lane skew as well as data state transition glitches |
US9582457B2 (en) | 2013-06-12 | 2017-02-28 | Qualcomm Incorporated | Camera control interface extension bus |
US9755818B2 (en) * | 2013-10-03 | 2017-09-05 | Qualcomm Incorporated | Method to enhance MIPI D-PHY link rate with minimal PHY changes and no protocol changes |
US20150220472A1 (en) * | 2014-02-05 | 2015-08-06 | Qualcomm Incorporated | Increasing throughput on multi-wire and multi-lane interfaces |
CN106063181B (zh) | 2014-03-06 | 2018-03-13 | 高通股份有限公司 | 接收机电路和在接收机电路上操作的方法 |
-
2016
- 2016-09-09 KR KR1020187009328A patent/KR102520096B1/ko active IP Right Grant
- 2016-09-09 CN CN201680058575.6A patent/CN108141346A/zh active Pending
- 2016-09-09 AU AU2016335548A patent/AU2016335548A1/en not_active Abandoned
- 2016-09-09 WO PCT/US2016/051131 patent/WO2017062132A1/en active Application Filing
- 2016-09-09 TW TW105129387A patent/TW201714443A/zh unknown
- 2016-09-09 EP EP16770840.3A patent/EP3360278A1/en not_active Withdrawn
- 2016-09-09 JP JP2018517310A patent/JP2018534847A/ja active Pending
- 2016-09-09 BR BR112018006874A patent/BR112018006874A2/pt not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
KR20180066065A (ko) | 2018-06-18 |
KR102520096B1 (ko) | 2023-04-07 |
CN108141346A (zh) | 2018-06-08 |
EP3360278A1 (en) | 2018-08-15 |
WO2017062132A1 (en) | 2017-04-13 |
TW201714443A (zh) | 2017-04-16 |
AU2016335548A1 (en) | 2018-04-12 |
BR112018006874A2 (pt) | 2018-10-16 |
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