JP2018534847A - Multi-lane N-factorial coding communication system and other multi-wire communication systems - Google Patents

Abstract

  Systems, methods, and apparatus are described that facilitate communication of data over a multi-wire data communication link, particularly between two devices in an electronic device. A receiving device receives a sequence of symbols over a multi-wire link. The receiving device further receives a clock signal via a dedicated clock line, which is separate and parallel to the multi-wire link. The receiving device uses the clock signal to decode the sequence of symbols. In an aspect, the second clock signal is embedded in a guaranteed transition between pairs of consecutive symbols in the sequence of symbols. Thus, the receiving device ignores the second clock signal while using the clock signal received via the dedicated clock line to decode the sequence of symbols.

Description

Cross-reference of related applications
[0001] This application claims the priority and benefit of non-provisional application No. 14 / 875,592, filed with the US Patent and Trademark Office on October 5, 2015, which non-provisional application is This is a continuation-in-part application of US Non-Provisional Application No. 14 / 250,119 entitled “Multi-Lane N-Factorial (N!) And Other Multi-Wire Communication Systems” filed on April 10, 2013. Filed on Apr. 14, 2014 claiming priority of US Provisional Application No. 61 / 886,567 entitled “N Factory Clock And Data Recovery With Negative Hold Time Sampling” filed Oct. 3, “N Factory Dual Dat It is also a continuation-in-part of US Non-Provisional Application No. 14 / 252,450 entitled “Rate Clock And Data Recovery”, and further, “Method To Enhancement MIPI D-PHY Link Rate” filed on October 3, 2013. “Method To Enhancing MIPI D-PHY Link Rate Rate” filed on September 19, 2014 claiming priority from US Provisional Application No. 61 / 886,556 entitled “With Minimal PHY Changes And No Protocol Changes”. This is a continuation-in-part of US Non-Provisional Application No. 14 / 491,884 entitled “PHY Changes And No Protocol Changes” Is incorporated herein by reference.

  [0002] This disclosure relates generally to data communication interfaces, and more specifically to multi-lane multi-wire data communication interfaces.

  [0003] Manufacturers of mobile devices such as cell phones may obtain mobile device parts from various sources, including different manufacturers. For example, the application processor in a mobile phone can be obtained from a first manufacturer, while the display of the mobile phone can be obtained from a second manufacturer. Application processors and displays or other devices may be interconnected using standard-based or proprietary physical interfaces. For example, the display may provide an interface that conforms to the Display System Interface (DSI) standard specified by the Mobile Industry Processor Interface Alliance (MIPI).

  [0004] In one example, a multi-signal data transfer system may utilize multi-wire differential signaling, such as three-phase or N-factorial (N!) Low voltage differential signaling (LVDS), and each symbol Transcoding (eg, digital-to-digital data conversion from one encoding type to another encoding type) may be performed to embed symbol clock information by causing symbol transitions in a cycle. Embedding clock information by transcoding minimizes the skew between the clock and the data signal, as well as eliminates the need for a phase locked loop (PLL) to recover the clock information from the data signal. It is an effective method.

  [0005] There is a continuing demand for optimized communication and improved data transfer rates over multi-signal communication links.

  [0006] Embodiments disclosed herein provide systems, methods, and apparatus for multi-lane, multi-wire interfaces.

  [0007] In certain aspects of the present disclosure, a method of data communication at a receiving device includes receiving a sequence of symbols over a multi-wire link. Each symbol in the sequence of symbols corresponds to the signaling state of N wires of the multi-wire link, where N is an integer greater than one. The method further includes receiving a clock signal via a dedicated clock line, wherein the dedicated clock line is separate and parallel to the multi-wire link and uses the clock signal to decode a sequence of symbols. Including.

  [0008] In certain aspects of the present disclosure, a second clock signal is embedded in a guaranteed transition between pairs of consecutive symbols in a sequence of symbols. Thus, the method decodes the sequence of symbols using the clock signal received via the dedicated clock line while ignoring the second clock signal.

  [0009] In certain aspects of the present disclosure, decoding includes converting a sequence of symbols into a set of data bits using a clock signal. In a further aspect of the disclosure, converting the sequence of symbols into a set of data bits includes using a transcoder to convert the sequence of symbols into a set of transition numbers, and converting the set of transition numbers into a set of data bits. Converting to a set.

  [0010] In certain aspects of the present disclosure, at least one line of the multi-wire link is bidirectional. The method further includes transmitting a second sequence of symbols over at least one bi-directional line based on a clock signal received via the dedicated clock line.

  [0011] In certain aspects of the present disclosure, the dedicated clock line is bidirectional and can be driven from any device transmitting over a multi-wire link. The method further includes transmitting a third clock signal via a dedicated clock line. The third clock signal may be associated with a transmit clock used to encode the data bits into a sequence of symbols transmitted over at least one bi-directional line.

  [0012] In certain aspects of the present disclosure, the receiving device includes processing circuitry. A memory may be coupled to the processing circuit. The processing circuit receives a sequence of symbols over a multi-wire link and receives a clock signal over a dedicated clock line, where the dedicated clock line is separate from and parallel to the multi-wire link. And configured to decode a sequence of symbols.

  [0013] In certain aspects of the present disclosure, an apparatus includes: means for receiving a sequence of symbols over a multi-wire link; means for receiving a clock signal via a dedicated clock line; Includes means for decoding a sequence of symbols using a clock signal that is separate and parallel to the multi-wire link.

  [0014] In certain aspects of the present disclosure, a processor-readable storage medium stores or maintains one or more instructions. When executed by at least one processing circuit, the instructions cause at least one processing circuit to receive a sequence of symbols over a multi-wire link and receive a clock signal over a dedicated clock line, where the dedicated clock line However, a sequence of symbols is decoded using a clock signal that is separate and parallel to the multi-wire link.

  [0015] In certain aspects of the present disclosure, a method of data communication at a transmitting device includes encoding data bits into a sequence of symbols and optionally embedding a second clock signal in the sequence of symbols. Including, where the second clock signal is embedded in a guaranteed transition between pairs of consecutive symbols in the sequence of symbols. Each symbol in the sequence of symbols corresponds to the signaling state of N wires of the multi-wire link, where N is an integer greater than one. The method further includes transmitting a sequence of symbols over the multi-wire link and transmitting a clock signal associated with the sequence of symbols over the dedicated clock line, where the dedicated clock line is the multi-wire link. Are separate and parallel.

  [0016] In certain aspects of the present disclosure, encoding the data bits includes using a transcoder to convert the data bits into a set of transition numbers and determining the number of transitions to obtain a sequence of symbols. Converting the set.

  [0017] In certain aspects of the present disclosure, at least one of the multi-wire links is bidirectional. The method further includes receiving a second sequence of symbols over at least one bidirectional line based on a clock signal transmitted over the dedicated clock line.

  [0018] In certain aspects of the present disclosure, the dedicated clock line is bidirectional and can be driven from any device transmitting over a multi-wire link. The method further includes receiving a third clock signal via a dedicated clock line. The third clock signal may be associated with a transmit clock used to encode the data bits into a sequence of symbols received over at least one bi-directional line.

  [0019] In certain aspects of the present disclosure, the transmitting device includes processing circuitry. Processing circuitry may be coupled to the memory. The processing circuit encodes the data bits into a sequence of symbols, and optionally embeds a second clock signal in the sequence of symbols, where the second clock signal is a sequence of symbols in the sequence of symbols. Send a sequence of symbols over a multi-wire link, embedded in a guaranteed transition between pairs, and send a clock signal associated with the sequence of symbols over a dedicated clock line, where the dedicated clock line is , Configured to be separate and parallel to the multi-wire link.

  [0020] In certain aspects of the present disclosure, an apparatus uses a clock signal to encode data bits into a sequence of symbols, and optionally to embed a second clock signal in the sequence of symbols. Means for transmitting a sequence of symbols over a multi-wire link, wherein a second clock signal is embedded in a guaranteed transition between pairs of consecutive symbols in the sequence of symbols. Means and means for transmitting a clock signal associated with the sequence of symbols via a dedicated clock line, wherein the dedicated clock line is separate and parallel to the multi-wire link.

  [0021] In certain aspects of the present disclosure, a processor-readable storage medium stores or maintains one or more instructions. When executed by at least one processing circuit, the instructions cause the at least one processing circuit to encode the data bits into a sequence of symbols and optionally embed a second clock signal into the sequence of symbols, where A second clock signal is transmitted through a multi-wire link, embedded in a guaranteed transition between pairs of consecutive symbols in the sequence of symbols, via a dedicated clock line A clock signal associated with the sequence of symbols is transmitted, where the dedicated clock line is separate and parallel to the multi-wire link.

[0022] FIG. 7 illustrates an apparatus that utilizes a data link between integrated circuit (IC) devices that selectively operate according to one of a plurality of available standards. [0023] FIG. 7 shows a system architecture of an apparatus that utilizes a data link between IC devices. [0024] N! FIG. 3 shows a CDR circuit that can be used in a communication interface. [0025] FIG. 4 illustrates the timing of several signals generated by the CDR circuit of FIG. 3, in accordance with one or more aspects disclosed herein. [0026] Basic N! The figure which shows the example of a multilane interface. [0027] FIG. 7 illustrates a first example of a multilane interface provided in accordance with one or more aspects disclosed herein. [0028] FIG. 10 illustrates a second example of a multi-lane interface provided in accordance with one or more aspects disclosed herein. [0029] FIG. 10 illustrates a third example of a multi-lane interface provided in accordance with one or more aspects disclosed herein. [0030] FIG. 10 illustrates a fourth example of a multi-lane interface provided in accordance with one or more aspects disclosed herein. [0031] FIG. 9 is a timing diagram illustrating the order of data transmitted over a multilane interface provided in accordance with one or more aspects disclosed herein. [0032] FIG. 8 illustrates a fifth example of a multi-lane interface provided in accordance with one or more aspects disclosed herein. [0033] FIG. 9 is a flowchart of a method for operating a receiver in a multi-lane N-wire interface provided in accordance with one or more aspects disclosed herein. [0034] FIG. 10 illustrates a simplified example of a receiver in a multi-lane N-wire interface provided in accordance with one or more aspects disclosed herein. [0035] FIG. 9 is a flowchart of a method for operating a transmitter in a multi-lane N-wire interface provided in accordance with one or more aspects disclosed herein. [0036] FIG. 10 illustrates a simplified example of a transmitter in a multi-lane N-wire interface provided in accordance with one or more aspects disclosed herein. [0037] FIG. 9 illustrates a further example of a multi-lane interface provided between two devices in accordance with one or more aspects disclosed herein. [0038] FIG. 7 shows an example of transmitting symbols on multiple data lanes using dedicated clock lines. [0039] FIG. 9 is a diagram illustrating an example of multi-wire transcoding using a dedicated clock line. [0040] FIG. 9 is an illustration of an apparatus (receiving device) configured to support operations relating to communicating data bits over a multi-wire link in accordance with one or more aspects disclosed herein. [0041] FIG. 9 is a flowchart illustrating a method of a receiving device for communicating data bits over a multi-wire link. [0042] FIG. 10 is an illustration of an apparatus (transmitting device) configured to support operations relating to communicating data bits over a multi-wire link in accordance with one or more aspects disclosed herein. [0043] A flowchart illustrating a method of a transmitting device for communicating data bits over a multi-wire link.

  [0044] Various aspects are now described with reference to the drawings. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more aspects. It will be apparent, however, that such embodiments can be practiced without these specific details.

  [0045] The terms "component", "module", "system", etc. used in this application include, but are not limited to, hardware, firmware, a combination of hardware and software, software, or running software It is intended to include computer related entities such as. For example, a component can be, but is not limited to being, a process running on a processor, a processor, an object, an executable, an execution thread, a program, and / or a computer. By way of illustration, both an application running on a computing device and the computing device can be a component. One or more components can exist within a process and / or thread of execution, and one component can be localized on one computer and / or distributed between two or more computers There is. In addition, these components can execute from various computer readable media having various data structures stored thereon. These components interact via signals from one component that interacts with another component in the local system, distributed system, and / or interacts with other systems over a network such as the Internet. Communication may be via a local process and / or a remote process, such as by following a signal having one or more data packets, such as data.

  [0046] Furthermore, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or”. That is, unless otherwise specified or apparent from the context, the phrase “X uses A or B” is intended to mean any of the natural global permutations. That is, the phrase “X uses A or B” is used when: X uses A, X uses B, or X uses both A and B Satisfied by any of the. Moreover, from the context that the articles “a” and “an”, as used in the present application and the appended claims, should be directed to the singular unless otherwise specified. Unless otherwise apparent, it should normally be taken to mean “one or more”.

  [0047] Some aspects of the invention are applicable to communication links deployed between electronic devices that may include subcomponents of equipment such as telephones, mobile computing devices, consumer electronics, automotive electronics, avionics systems, etc. It can be. FIG. 1 illustrates an apparatus that may utilize a communication link between IC devices. In one example, apparatus 100 may include a wireless communication device that communicates with a radio access network (RAN), a core access network, the Internet, and / or another network through a radio frequency (RF) transceiver. Apparatus 100 may include a communication transceiver 106 operably coupled to processing circuit 102. The processing circuit 102 may comprise one or more IC devices, such as an application specific integrated circuit (ASIC) 108. The ASIC 108 may include one or more processing devices, logic circuits, and the like. The processing circuit 102 may include and / or be coupled to a processor readable storage such as a memory 112 that may maintain instructions and data that may be executed by the processing circuit 102. The processing circuit 102 is controlled by one or more of an operating system and application programming interface (API) 110 layer that supports and enables execution of software modules residing in a storage medium, such as the memory device 112 of the wireless device. Can be done. Memory device 112 may be read only memory (ROM) or random access memory (RAM), electrically erasable programmable ROM (EEPROM®), flash card, or any memory that can be used in processing systems and computing platforms. Devices can be included. The processing circuit 102 may include or access a local database 114 that may maintain operating parameters and other information used to configure and operate the apparatus 100. The local database 114 may be implemented using one or more of a database module, flash memory, magnetic media, EEPROM, optical media, tape, soft disk or hard disk. The processing circuitry may also be operatively coupled to external devices such as operator controls such as antenna 122, display 124, buttons 128 and keypad 126, among other components.

  [0048] FIG. 2 is a block schematic diagram illustrating some aspects of an apparatus 200 connected to a communication bus, which includes a wireless mobile device, a mobile phone, a mobile computing system, a wireless telephone, a notebook computer. , Tablet computing devices, media players, s-game devices, etc. The apparatus 200 may comprise a plurality of IC devices 202 and 230 that exchange data and control information over the communication link 220. Communication link 220 may be used to connect IC devices 202 and 230 that are located in close proximity to each other or physically located in different parts of apparatus 200. In one example, communication link 220 may be provided on a chip carrier, substrate, or circuit board that carries IC devices 202 and 230. In another example, the first IC device 202 may be located on the keypad portion of the foldable phone, while the second IC device 230 may be located on the display portion of the foldable phone. is there. In another example, a portion of communication link 220 may comprise a cable connection or an optical connection.

  [0049] The communication link 220 may include a plurality of channels 222, 224, and 226. One or more channels 226 may be bidirectional and may operate in half-duplex mode and / or full-duplex mode. One or more channels 222 and 224 may be unidirectional. Communication link 220 may be asymmetric and provides greater bandwidth in one direction. In one example described herein, the first communication channel 222 may be referred to as the forward link 222, while the second communication channel 224 may be referred to as the reverse link 224. Even if both IC devices 202 and 230 are configured to transmit and receive over communication link 222, first IC device 202 may be designated as a host system or transmitter, while The second IC device 230 may be designated as a client system or receiver. In one example, the forward link 222 may operate at a higher data rate when communicating data from the first IC device 202 to the second IC device 230, while the reverse link 224 may be When communicating data from one IC device 230 to the first IC device 202, it may operate at a lower data rate.

  [0050] Each IC device 202 and 230 may have a processor or other processing and / or computing circuit or device 206, 236. In one example, the first IC device 202 can perform the main functions of the apparatus 200, including maintaining wireless communication through the wireless transceiver 204 and the antenna 214, while the second IC device 230 A user interface for managing or operating the display controller 232 may be supported. The first IC device 202 or the second IC device 230 may use the camera controller 234 to control the operation of the camera or video input device. Other features supported by one or more of IC devices 202 and 230 may include a keyboard, voice recognition components, and other input or output devices. Display controller 232 may include circuitry and software drivers that support displays such as liquid crystal display (LCD) panels, touch screen displays, indicators, and the like. Storage media 208 and 238 may be temporary and / or non-transitory adapted to maintain instructions and data used by respective processors 206 and 236 and / or other components of IC devices 202 and 230. A temporary storage device may be included. Communication between each processor 206, 236, its corresponding storage media 208 and 238, and other modules and circuits may be facilitated by one or more buses 212 and 242, respectively.

  [0051] The reverse link 224 may operate in the same manner as the forward link 222, and the forward link 222 and the reverse link 224 may be capable of transmitting at equal or different rates. Here, the speed may be expressed as a data transfer rate and / or a clocking rate. The forward data rate and the reverse data rate may be substantially the same or may differ in digit depending on the application. In some applications, a single bidirectional link 226 may support communication between the first IC device 202 and the second IC device 230. Forward link 222 and / or reverse link 224 may operate in a bidirectional mode, for example, when forward link 222 and reverse link 224 share the same physical connection and operate in a half-duplex manner. Composed. In one example, the communication link 220 operates to communicate control information, command information, and other information between the first IC device 202 and the second IC device 230 in accordance with industry standards or other standards. Can do.

  [0052] In one example, the forward link 222 and the reverse link 224 are configured or adapted to support a 80 video per second LCD driver with a wide video graphics array (WVGA) without a frame buffer for display refresh. Therefore, pixel data can be distributed at 810 Mbps. In another example, forward link 222 and reverse link 224 are configured or adapted to allow communication with synchronous random access memory (DRAM), such as double data rate synchronous dynamic random access memory (SDRAM). Can be done. Encoding devices 210 and / or 240 can encode multiple bits per clock transition and are used by multiple sets of wires to send and receive data from SDRAM, control signals, address signals, etc. Can be done.

  [0053] Forward link 222 and reverse link 224 may conform to or be compatible with application-specific industry standards. In one example, the MIPI standard defines a physical layer interface between an application processor IC device 202 and an IC device 230 that supports a mobile device camera or display. The MIPI standard includes specifications that govern the operational characteristics of products that conform to the MIPI specification for mobile devices. The MIPI standard may define an interface that utilizes complementary metal oxide semiconductor (CMOS) parallel buses.

  [0054] In one example, the communication link 220 of FIG. 2 may be implemented as a wired bus including a plurality of signal wires (denoted as N wires). The N wires may be configured to carry data encoded as symbols, where clock information is embedded in a sequence of symbols transmitted over multiple wires.

[0055] FIG. 3 shows an example of a clock and data recovery (CDR) circuit 300 that may be utilized to recover embedded clock information in an N-wire system. FIG. 4 is a timing diagram 400 illustrating some signals generated through the operation of the CDR circuit 300. The CDR circuit 300 and its timing diagram 400 are provided by a generalized example, but in some cases other variations of the CDR circuit 300 and / or other CDR circuits may be used. The signals received from the N wires 308 are first processed by a number ( _N C ₂ ) of receivers 302 that produce a corresponding number of raw signals as outputs. In the example shown, N = 4 wires 308 produce ₄ C ₂ = 6 receptions that produce a first state transition signal (SI signal) 320 that includes 6 raw signals representing the received symbols. Processed by machine 302. For each raw signal output from each different receiver, a symbol during which the corresponding signal state is undefined, indeterminate, transient, or otherwise unstable There may be a setup time 408 provided between S ₀ 402, S ₁ 404 and S ₂ 406. Level latch 310, comparator 304, set reset latch 306, one-shot circuit 326, analog delay element 312, and (bus-connected) level latch 310 are level latched signals that represent delayed instances of SI signal 320 ( The delay until the SI signal 320 is captured by the level latch 310 to provide an updated S signal 322 may be configured to generate a delay element (Delay S) 312. May be selected by configuring.

  [0056] In operation, the comparator 304 compares the SI signal 320 with the S signal 322 and outputs a binary comparison signal (NE signal) 314. The set-reset latch 306 can receive the NE signal 314 from the comparator 304 and output a signal (NEFLT signal) 316, which is a filtered version of the NE signal 314. The operation of set-reset latch 306 may be configured to remove any transient instability in NE signal 314, where the transient instability is shown as spike 410 in NE signal 314. The NEFLT signal 316 may be used to control an output latch 324 that captures the S signal 322 as the output data signal 328.

  [0057] The one-shot circuit 326 receives the NEFLT signal 316 and produces a fixed width pulse 412, which can then be delayed by a delay element 312 to produce a clock signal (SDRCLK) 318. . In some cases, the SDRCLK signal 318 may be used by external circuitry to sample the CDR 300 data output 328. In one example, the SDRCLK signal 318 can be provided to a decoder circuit or a deserializer circuit. The level latch 310 receives the SI signal 320 and outputs the S signal 322, where the level latch 310 is triggered or otherwise controlled by the SDRCLK signal 318.

  In operation, the comparator 304 compares the SI signal 320 with the S signal 322, and the S signal 322 is output from the level latch 310. Comparator 304 sets NE signal 314 to a first state (eg, logic low) when SI signal 320 and S signal 322 are equal, and the second state (when SI signal 320 and S signal 322 are not equal). For example, it is driven to logic high). NE signal 314 is in the second state when SI signal 320 and S signal 322 represent different symbols. Thus, the second state indicates that a transition has occurred.

  [0059] As can be seen from the timing diagram 400, the S signal 322 is essentially a delayed and filtered version of the SI signal 320, and the transient or anomaly 408 may be described as a SI signal 320 and an S signal 322. The delay 414 during the period has been removed. Multiple transitions 408 in the SI signal 320 may be reflected as spikes 410 in the NE signal 314, but these spikes 410 are hidden in the NEFLT signal 316 through the operation of the set reset circuit. In addition, SDRCLK 318 is tolerant to line skew and anomalies in symbol transitions based on the use of delays 326a, 312 provided to level latch 310 and set reset latch 306 in the feedback path, which causes the SDRCLK signal Reference numeral 318 controls the reset function of the set / reset latch 306.

[0060] At the beginning of the transition 416 between the first symbol value S ₀ 402 and the next symbol value S ₁ 404, the SI signal 320 begins to change state. The state of SI signal 320 may differ from S ₁ 404 due to the possibility of intermediate states or indeterminate state 408 during the transition between S ₀ 402 and S ₁ 404. These intermediate or indeterminate states 408 can be caused by, for example, wire-to-wire skew, over / undershoot, crosstalk, etc.

  [0061] The NE signal 314 goes high as soon as the comparator 304 detects a difference in value between the SI signal 320 and the S signal 322, and the transition of the NE signal 314 to high is asynchronously set and reset. Set the output of 306 to drive the NEFLT signal 316 high. The NEFLT signal 316 remains high until the set reset latch 306 is reset by the high state of the SDRCLK signal 318. The SDRCLK signal 318 is a delayed version of the NE1SHOT signal 324, and the NE1SHOT signal 324 is a version of the NEFLT signal 316 with a limited pulse width. The SDRCLK signal 318 may be delayed with respect to the NE1SHOT signal 324, for example through the use of an analog delay circuit 312.

[0062] The intermediate state or indeterminate state 408 of SI 320 may represent invalid data. These intermediate or indeterminate states 408 may include the previous symbol value S ₀ 402 for a short period of time and may cause the NE signal 314 to return low for a short period of time. A transition of the SI signal 320 may generate a spike 410 in the NE signal 314. Spike 410 is substantially filtered and does not appear in NEFLT signal 316.

  [0063] Due to the high state of the NEFLT signal 316, the SDRCLK signal 318 transitions high after a delay period 340 caused by the delay circuit 312. A high state of SDRCLK signal 318 resets the output of set reset latch 306 and causes NEFLT signal 316 to transition to a low state. The high state of SDRCLK signal 318 also enables level latch 310, and the value of SI signal 320 can be output on S signal 322.

[0064] Comparator 304 detects that S signal 322 (for symbol S ₁ 402) matches symbol S ₁ 402 appearing in SI signal 320 and switches the output (NE signal 314) to low. . Due to the low state of NEFLT signal 316, SDRCLK signal 318 goes low after a delay period 342 caused by analog delay 312. This cycle repeats for each transition of SI signal 320. At a certain time after the falling edge of the SDRCLK signal 318, there is a new symbol S ₂ 406 is received, a new symbol S ₂ 406 is the SI signal 320, to switch the value following the symbol S ₂ 406 Sometimes.

FIG. 5 is a diagram illustrating an example of a multilane interface 500 provided between two devices 502 and 532. At transmitter 502, transcoders 506, 516 may transmit data 504 to symbols to be transmitted over a set of N wires on each lane 512, 522, using, for example, N factorial (N!) Coding. Can be used to encode 514 and clock information. Clock information is derived from the respective transmit clocks 524, 526, and _N signals by ensuring that a signaling state transition occurs on at least one of the _N C ₂ signals between consecutive symbols. Can be encoded in a sequence of symbols transmitted in _N C ₂ differential signals over a number of wires. N! When encoding is used to drive N wires, each bit of the symbol is transmitted as a differential signal by one of a set of line drivers 510, 520, where line drivers 510, 520 The differential drivers in the set are coupled to different pairs of N wires. The number of available combinations of wire pairs and signals can be calculated as _N C ₂ , where the number of available combinations is the number of signals that can be transmitted over the N wires. To decide. The number of data bits 504, 514 that can be encoded in a symbol can be calculated based on the number of available signaling states available for each symbol transmission interval.

  [0066] A termination impedance (usually resistive) couples each of the N wires to a common midpoint in termination network 528,530. It will be appreciated that the signaling state of the N wires reflects the combination of currents in the termination network 528, 530 due to the differential drivers 510, 520 coupled to each wire. It will be further understood that the midpoint of the termination networks 528, 530 is a null point so that the currents in the termination networks 528, 530 cancel each other at the midpoint.

[0067] Since at least one of the _N C ₂ signals in the link transitions between consecutive symbols, N! The encoding scheme does not need to use a separate clock channel and / or decoding that does not return to zero. In effect, each transcoder 506, 516 produces a transition between each pair of symbols transmitted over N wires by producing a sequence of symbols where each symbol is different from the previous symbol. Make sure you do. In the example shown in FIG. 5, each lane 512, 522 has N = 4 wires, and each set of ₄ wires can carry ₄ C ₂ = 6 differential signals. Transcoders 506, 516 may utilize a mapping scheme to generate raw symbols for transmission on the N wires available on lanes 512, 522. Transcoders 506 and 516 and serializers 508 and 518 cooperate to produce raw symbols for transmission based on input data bits 504 and 514. At receiver 532, transcoders 540, 550 may utilize the mapping, for example, to determine the number of transitions that characterize the difference between consecutive raw symbol pairs and symbols in the lookup table. The transcoders 506, 516, 540, 550 operate on the basis that each successive pair of raw symbols includes two different symbols.

[0068] Transcoders 506, 516 at transmitter 502 can use N! In every single symbol transition. -You can choose from one state. In one example, 4! The system 4! For the next symbol to be transmitted in each symbol transition. −1 = 23 signaling states are provided. The bit rate may be calculated as log ₂ (available state) per cycle of the transmit clock 524, 526. In systems that use double data rate (DDR) clocking, symbol transitions occur on both the rising and falling edges of the transmit clocks 524, 526. In one example, since two or more symbols can be transmitted word by word (ie, every transmit clock cycle), the overall available state in the transmit clock cycle is ( _{NC 2} −1) ^2. = (23) ² = 529, and the number of data bits 504 that can be transmitted per symbol can be calculated as log ₂ (529) = 9.047 bits.

[0069] The receiver device 532 receives a sequence of symbols using a set of line receivers 534, 544, where each receiver in the set of line receivers 534, 544 is N wires. The difference in signaling state in one pair is determined. Thus, _N C ₂ receivers are used in each lane 512, 522, where N represents the number of wires in the corresponding lane 512, 522. _N C ₂ receivers 534, 544 produce a corresponding number of raw symbols as outputs.

[0070] In the illustrated example, each lane 512, 522 has N = 4 wires, and the signals received on the four wires of each lane 512, 522 are the corresponding CDRs 536, 546 and deserializer 538. Processed by a corresponding set of line receivers 534 or 544 including six receivers ( ₄ C ₂ = 6) to produce the state transition signal provided to 548. The CDRs 536 and 546 can generally operate in the same manner as the CDR 300 of FIG. 3, and each CDR 536 and 546 produces a receive clock signal 554, 556 that can be used by the corresponding deserializer 538, 548. obtain. Clock signal 554 may include a DDR clock signal that can be used by external circuitry to receive data provided by transcoders 540, 550. Each transcoder 540, 550 decodes a block of received symbols from the corresponding deserializer 538, 548 by comparing each next symbol with its immediately preceding one. Transcoders 540, 550 produce output data 542 and 552 corresponding to data 504, 514 provided to transmitter 502.

  [0071] As shown in the example of FIG. 5, each lane 512, 522 may operate independently, but in a typical application, data 504 transmitted through one lane 512 is transmitted through the other lane 522. Data 514 can be synchronized. In one example, the data bits 504 for transmission over the first lane (lane X in this example) 512 are transmitted over at least four wires of the first lane 512 when transmitted in a predetermined sequence. Received by a first transcoder 506 that generates a set of raw symbols that ensures that a signaling state transition occurs in one signal. The serializer 508 produces a sequence of symbol values that is provided to the line driver 510 that determines the signaling state of the four wires of the first lane 512 for each symbol interval. At the same time, data bits 514 are received by the second transcoder 516 in the second lane (lane Y in this example) 522. The second transcoder 516 converts the set of transition numbers into a sequence of symbol values provided to a line driver 520 that determines the signaling state of the four wires of the second lane 522 for each symbol interval. Generate a set of transition numbers that are serialized by 518. The sequence of raw symbols ensures that a signaling state transition occurs in at least one signal transmitted on the four wires of the second lane 522 between each pair of consecutive symbols.

  [0072] FIG. 6 illustrates a first example of a multi-lane interface 600 provided in accordance with certain aspects disclosed herein. The multi-lane interface 600 has clock information encoded in symbols transmitted on the first lane (here, lane X) 612 encoded on one or more other lanes including lane Y622. When used to receive symbols transmitted without clock information, it results in improved data throughput and reduced circuit complexity. In the illustrated example, each lane 612, 622 includes four wires.

  [0073] Data for transmission may be divided into two portions 604 and 614, where each portion is transmitted on a different lane 612,622. On the first lane 612, information regarding the data 604 and transmit clock 624 is encoded using the transcoder / serializer 608 to obtain the raw symbols to be serialized as described with respect to FIG. obtain. At receiver 632, the output of receiver 634 associated with first lane 612 is provided to CDR 636. The CDR 636 may be configured to detect signaling state transitions to generate a receive clock 654 that is used by both the deserialization and transcoding circuits 638 and 648 for both lanes 612, 622. The first deserialization and transcoding circuit 638 extracts data 642 from the raw symbols received from the first lane 612, while the second deserialization and transcoding circuit 648 Data 652 is extracted from the raw symbols received from lane 622.

  [0074] For the second lane 622, transmission data 614 may be provided to the transcoding and serialization circuit 618 and transmitted on the second lane 622 without the encoded clock information. The transcoding circuit used to produce a raw symbol for the second lane 622 is used to produce a raw symbol with embedded clock information for transmission on the first lane 612. It may be much less complex than the transcoding circuit used. For example, the transcoding circuit for the second lane 622 may not need to perform some arithmetic operations and logic functions to guarantee state transitions at every symbol boundary.

[0075] In the example shown in FIG. 6, DDR clocked 4-wire first lane 612 provides (4! -1) ² = (23) ² = 529 signaling states and is received. Log ₂ 529 = 9.047 bits of data per word 604, 614 can be encoded, while the DDR clocked 4-wire second lane 622 has (4!) ² = (24) ² = 576 signaling states can be provided and log ₂ 576 = 9.170 bits of data per word can be encoded. In another example, the interface may have two 3-wire lanes where the clock information is encoded in the first lane but not in the second lane. In this latter example, seven symbols per word may be transmitted, and the first three-wire lane provides (3! -1) ⁷ = (5) ⁷ = 78125 signaling states. , Log ₂ 78125 = 16.253 bits of data can be encoded, while the second lane of 3 wires provides (3!) ⁷ = (6) ⁷ = 279936 signaling states In each clock cycle, log ₂ 279936 = 18.095 bits of data can be encoded. Multilane N! By encoding the clock information in a single lane, a higher overall throughput can be achieved with less hardware.

  [0076] FIG. 7 illustrates another example of a multilane interface 700 provided in accordance with one or more aspects disclosed herein. The multilane interface 700 provides improved design flexibility in addition to optimizing data throughput and reducing circuit complexity. Here, the clock information encoded in the symbols transmitted in one lane (here, lane X) 712 receives the symbols transmitted in one or more other lanes 722 having different numbers of wires. Can be used for.

  [0077] In the illustrated example, the data for transmission may be divided into multiple portions 704 and 714, where each portion will be transmitted on a different lane 712,722. On the first lane 712, data 704 and transmission clock 724 may be converted by a transcoding and serialization circuit 708 to obtain a sequence of raw symbols as described with respect to FIGS. On the second lane 722, the received data 714 can be provided to the transcoding and serialization circuit 718 and then transmitted without embedded clock information.

  [0078] At the receiver 732, the output of the receiver 734 associated with the first lane 712 is provided to the CDR 736. The CDR 736 detects the transition of the signaling state of the three wires in the first lane 712, and is used by both the deserialization circuit and the transcoding circuits 738 and 748 for both lanes 712, 722. A clock 754 may be configured to be generated. The first deserialization circuit and transcoding circuit 738 extracts data 742 from the raw symbols received from the first lane 712, while the second deserialization circuit and transcoding circuit 748 Data 752 is extracted from the raw symbols received from the lane 722.

[0079] In the example, the first lane 712 is 3! It contains 3 wires configured for operation, but the second lane 722 is 4! Includes four wires configured for operation. The first lane 712 can provide (3! -1) ² = (5) ² = 25 signaling states for a system with 2 symbols per word, so that log ₂ 25 = 4. 644 bits of data can be encoded word by word. The 4-wire second lane 722 provides (4!) ² = (24) ² = 576 signaling states and can log ₂ 576 = 9.170 bits of data per word. .

  [0080] Great efficiency can be obtained when a single lane 712 encodes clock information and a variable number of wires can be assigned to other lanes 722. In an example where 10 interconnects (wires or connectors) are available between two devices, the conventional 3! The system may configure three 3-wire lanes, where clock information is encoded on each lane. Each of the three lanes provides 5 signaling states per symbol for a total of 15 states per symbol. However, systems provided according to some aspects described herein are two 3! Lane and one 4! Ten interconnects can be used to provide lanes, where the clock information is the first 3! Encoded in the lane. This combination of lanes is the first 3! Which provides 5 states per symbol and clock information. A second 3 providing 6 states per lane, symbol! Provides 24 lanes and 24 states per symbol! Based on the lane, it provides a total of 5 × 6 × 24 = 720 signaling states per symbol.

  [0081] FIG. 8 illustrates another example of a multilane interface 800 provided in accordance with one or more aspects disclosed herein. The multilane interface 800 provides various advantages including improved decoding reliability, which may allow higher transmission rates. The configuration and operation of the multi-lane interface 800 in this example, except that the CDR 836 is configured to generate the receive clock 854 from transitions detected in either the first lane 812 or the second lane 822. This is the same as the configuration and operation of the multilane interface 600 of FIG. Accordingly, CDR 836 receives the outputs of receivers 834 and 844. Since CDR 836 generates a clock from the first detected transition in either lane 812 or 822, variations in delay between symbol boundaries and the edge of received clock 854 can be reduced. This approach can reduce the effects of variable transition times and / or variable switching times on the wires of line drivers 810, 820 or receivers 834, 844.

  [0082] In operation, data for transmission may be received in two or more portions 804 and 814, where portions 804, 814 are for transmission on different lanes 812, 822. is there. As described with respect to FIG. 5, the combination of the transcoder circuit and the serializer circuit 808 encodes data bits X804 and embeds information about the transmission clock 824 in the sequence of symbols to be transmitted in the first lane 812. Can do. At receiver 832, the outputs of both sets of receivers 834 and 844 are provided to CDR 836, which detects a signaling state transition in either lane 812, 822 and based on the transition, receives clock 854. Configured to generate. Receive clock 854 is used by both deserialization / transcoding circuits 838 and 848, which produce a first lane data output 842 and a second lane data output 852, respectively. .

  [0083] FIG. 9 illustrates another example of a multilane interface 900 provided in accordance with one or more aspects disclosed herein. In this example, the multi-lane interface 900 is improved by ensuring that a continuous symbol interval and a signaling state transition between symbol intervals occurs in any one of the multiple lanes 912, 922. Data throughput and encoding efficiency. Thus, the percentage overhead associated with encoding clock information may be reduced relative to a system where clock information is embedded in a sequence of symbols transmitted on a single lane. In the multi-lane interface 900, the first lane (here, lane X) 912 is 3! The second lane (here, lane Y) 922 contains 4 wires, including 3 wires carrying 1 encoded signal, 4! Configured for encoding. Different numbers and configurations of lanes may be utilized, and the specific example illustrated in FIG. 9 is provided for illustrative purposes only. Transcoder 906 may be adapted to combine data 904 and clock information in symbols to be transmitted over two or more lanes 912 and / or 922.

[0084] Encoding efficiency may be achieved by embedding clock information based on a combination of available signaling states for all lanes 912, 922. The clock information is embedded by ensuring that a signaling state transition occurs in at least one lane 912, 922 between successive symbol intervals. In operation, transcoder 906 may be configured to produce a different set of symbols for each lane 912, 922. In one example, data 904 received by transmitter 902 according to clock signal 924 is 3! The first sequence of symbols encoded into the three signals transmitted in the first lane 912 of the first and 4! May be transmitted as a second sequence of symbols that are encoded into six signals transmitted simultaneously in the second lane 922 of the first lane 922. Transcoder 906 embeds clock information by ensuring that signaling state transitions occur in at least one of lanes 912 and 922 between consecutive symbols. The total number of states per symbol interval is the product of the number of states per symbol transmitted on the first lane 912 and the number of states per symbol transmitted on the second lane 922. Accordingly, the number of states available to the transcoder in each symbol interval can be calculated as follows when clock information is embedded across both lanes 912, 922.
(N _lane1 ! × N _lane2 !)-1 = (3! × 4!)-1 = (6 × 24) -1 = 143
In another example, the number of states available to the transcoder in each symbol interval is 3! Can be computed as follows when embedded over two lanes encoded into three signals using:
(N _laneX ! × N _laneY !) − 1 = (3! × 3!) − 1 = (6 × 6) −1 = 35

  [0085] The number of states available to the transcoder at each symbol transition governs the number of bits that can be transmitted in each received data cycle.

  [0086] Tables 1 and 2 show that N! Fig. 5 shows the coding efficiency improvement when embedded by a transcoder across lanes. Table 1 relates to the multilane interface 900 of FIG. As can be seen from the table, maximum coding efficiency is obtained when the transcoder 906 embeds clock information by considering the sequence of symbols transmitted in both lanes 912, 922.

Table 2 shows two 3! This relates to an example of a multi-lane interface with lanes.

  [0087] In the example of FIG. 9, the receiver 932 includes a CDR 936 that generates a receive clock 954 by detecting transitions in both lanes 912, 922. Deserializers 938, 948 provide symbols received from respective lanes 912, 922 to transcoder 940 that inverts the transcoding performed by transcoder 906 in the transmitter. Transcoder 940 in receiver 932 operates by examining the synthesized sequence of received symbols to produce output data 942, which is converted to data 904 received at transmitter 902. Correspond. The set of line drivers 910, 920 and receivers 934, 944 is N! May be provided according to the number of wires in lanes 912, 922.

  [0088] The multilane interface 900 may be configured to provide additional advantages over conventional interfaces. FIG. 10 shows an example where a transcoder 1024 can be used to control the order of delivery of data to a receiver. A multi-lane interface 1000, such as multi-lane interface 500 of FIG. 5, independently places two or more sets of data bits 1002, 1004 into a sequence of symbols 1006, 1008 for transmission over a corresponding number of lanes. Can be encoded. Data may be provided to the multi-lane interface 1000 pre-divided into sets of data bits 1002, 1004 and / or the set of data bits 1002, 1004 may be divided by the multi-lane interface 1000. is there. Data bits may be arbitrarily allocated between two or more sets of data bits 1002, 1004 according to function, design preference, or for convenience and / or other reasons.

  [0089] In the illustrated multilane interface 1000, each word, byte, or other data element received in the first clock cycle is ordered in pairs of symbol intervals 1012a-1012g in one of the two lanes. Can be encoded into two or more symbols to be transmitted. The receiver can decode the data element when two or more symbols are received from a pair of symbol intervals 1012a-1012g.

  [0090] A multilane interface 1020, such as the multilane interface 900 of FIG. 9, encodes data 1022 and clock information into a plurality of sequences 1026, 1028 of symbols transmitted simultaneously over two or more lanes. A coder 1024 may be included. Transcoder 1024 may control the order of delivery of data to the receiver by transmitting symbols simultaneously for transmission on two lanes. In one example, data bits 1022 (Bits (0)) received in the first clock cycle may be transcoded into two symbols and transmitted in parallel on two lanes during a first symbol interval 1030. . Data bits 1022 (Bits (1)) received in the second clock cycle may be transmitted as two symbols in parallel in two lanes during the second symbol interval 1032. The transmission of data on two parallel data lanes can provide certain benefits in timing sensitive applications such as camera shutter and / or flash control, control signals associated with gaming applications, and the like.

  [0091] FIG. 11 illustrates another example of a multilane interface 1100 provided in accordance with one or more aspects disclosed herein. In this example, the multilane interface 1100 has at least one N! It includes a lane 1112 to be encoded and a serial data link 1122. Serial data link 1122 may be a single-ended serial link (as shown) or a differentially encoded serial data link. The serial data link 1122 may include a serial bus, such as an inter-integrated circuit (I2C) bus, a camera control interface (CCI) serial bus, or a derivative of these serial bus technologies. In the example shown, the clock signal 1124 is N! Used by link serializer 1108 and serial link 1122 serializer 1118, clock signal 1124 need not be transmitted to receiver 1132 over separate clock signal lanes. Instead, transcoder 1106 is N! The clock information is embedded in the sequence of symbols provided to the differential line driver in the lane 1112 through the serializer.

  [0092] At the receiver 1132, the CDR 1136 generates a receiver clock signal 1154 from the transitions detected at the output of the receiver 1134. Receiver clock signal 1154 is N! Used by lane deserializer 1138 and serial link deserializer 1148. In some cases, CDR 1136 may monitor the output of line receiver 1144 associated with serial link 1122 to improve detection of symbol intervals and transitions between symbol intervals. N! The lane deserializer 1138 provides the deserialized symbol information to the transcoder 1140, and the transcoder 1140 receives N! Output data 1142 representing input data 1104 transmitted through lane 1112 to be encoded is produced.

[0093] In one example, transmitter 1102 is 3! Transmit symbols in three signals in the first lane 1112 to be encoded. The symbol includes embedded clock information, and 5 signaling states per symbol are available on the first lane 1112. The transmitter may also transmit data on the second lane using four serial signals transmitted over the serial link 1122 wires. The receiver 1132 can generate a clock signal 1154 from the symbols transmitted in the first lane 1112, where the clock is used to decode / deserialize the data transmitted in both lanes 1112, 1122. used. Thus, the serial link 1122 provides 2 ⁴ = 16 states per symbol when the clock 1154 provided by the CDR 1136 is used by the deserializer 1148 for the second lane serial link 1122. When the clock 1154 provided by CDR 1136 is used, a total of 5 × 16 = 80 states per symbol is achieved.

[0094] As a comparison, a conventional or regular 4-wire serial link 1122 may dedicate one of the four wires to carry the clock signal, and data transmission may be performed on four wires. It may be limited to the other three signals. In this latter configuration, 2 ³ = 8 signaling states per symbol can be provided on the serial link 1122 and the data is 3! When transmitted also in the encoded first lane 1112, a total of 5 × 8 = 40 signaling states are obtained per symbol.

  [0095] FIG. 12 is a flowchart 1200 illustrating a method for data communication over an N-wire communication link. The communication link is N! Multiple connectors may be included that carry symbols that are encoded using a suitable encoding scheme such as encoding, multiphase encoding, multi-wire differential encoding, and the like. The connector may include conductive wires, optical signal conductors, semiconductor interconnects, and the like. The method may be performed by one or more processors of the receiving device.

  [0096] In step 1202, a first sequence of symbols is received from a first lane of a multi-lane interface. Each symbol in the sequence of symbols may correspond to the signaling state of the N wires of the first lane.

  [0097] In step 1204, a clock signal is recovered or extracted from the multilane interface. The clock signal may include edges corresponding to multiple transitions in the signaling state of the N wires between pairs of consecutive symbols in the first sequence of symbols.

  [0098] In step 1206, a first sequence of symbols is converted into a first set of data bits using a clock signal. The first sequence of symbols uses a transcoder to convert the first sequence of symbols into a set of transition numbers, and converts the set of transition numbers to obtain a first set of data bits. Can be converted into a first set of data bits.

  [0099] In step 1208, a second set of data bits is derived from one or more signals received from the second lane of the multi-lane interface using a clock signal. The second set of data bits may be derived without using a transcoder.

According to some embodiments [00100] disclosed herein, a first sequence of symbols, _N C ₂ pieces of differential signals received from the _N C ₂ pieces of different pairs of the N wires Can be encoded. The second lane may contain M of wires, wherein the second sequence of symbols, _M C ₂ pieces of differential signals received from _M C ₂ pieces of different pairs M of wires Is encoded. M and N can have equal or different values.

  [00101] According to some aspects disclosed herein, deriving the second set of data bits includes receiving a serial signal from each of the M wires of the serial interface, and a clock. Extracting a second set of data bits by sampling the serial signal according to the signal. Deriving the second set of data bits includes receiving M / 2 differential signals from the M wires of the serial interface and sampling the M / 2 differential signals according to the clock signal. Extracting a second set of data bits.

  [00102] According to some aspects disclosed herein, a clock signal is transmitted to a transition detected in the signaling state of the N wires or the signaling state of one or more wires in the second lane. By providing corresponding clock signal transitions, they can be recovered or extracted. The clock signal may include an edge corresponding to one or more transitions in the signaling state of at least one wire of the second lane of the multilane interface.

[00103] According to some aspects disclosed herein, the first sequence of symbols is encoded into _N C ₂ differential signals. Each of the _N C ₂ differential signals may be received from a different pair of N wires. The second sequence of symbols may be encoded into _M C ₂ differential signals received from the _M wires of the second lane. Each of the _M C ₂ differential signals may be received from a different pair of M wires. The first sequence of symbols may be converted to a first set of data bits using a transcoder circuit. The second sequence of symbols can be converted to a second set of data bits using the same transcoder circuit.

  [00104] According to some aspects disclosed herein, a transition of one or more signaling states of the N wires and the M wires is performed in a first sequence of symbols. Occurs between each sequential pair of symbols. Each of the first sequence of symbols may be transmitted in a different symbol interval. The first set of data bits and the second set of data bits received in each symbol interval may be combined to obtain a complete data element from each symbol interval.

  [00105] FIG. 13 is a diagram illustrating a simplified example of a hardware implementation for an apparatus 1300 that utilizes a processing circuit 1302. The processing circuitry generally includes a processor 1316 that may include one or more of a microprocessor, microcontroller, digital signal processor, sequencer, and state machine. Processing circuit 1302 may be implemented using a bus architecture generally represented by bus 1320. Bus 1320 may include any number of interconnect buses and bridges depending on the specific application of processing circuit 1302 and the overall design constraints. Bus 1320 includes processor 1316, modules and / or circuits 1304, 1306, and 1308, line interface circuitry 1312 that can be configured to communicate through connectors or wires (multi-lane interface) 1314, and processor-readable / computer-readable storage medium 1318. Various circuits including one or more processors and / or hardware modules represented by are coupled together. Bus 1320 may also connect various other circuits, such as timing sources, peripherals, voltage regulators, and power management circuits, but these circuits are well known in the art and therefore no more. Not explained.

  [00106] The processor 1316 is responsible for general processing, including execution of software stored on the computer-readable storage medium 1318. The software, when executed by the processor 1316, causes the processing circuitry 1302 to perform the various functions described above for any particular device. The computer-readable storage medium 1318 may also be used for storing data that is manipulated by the processor 1316 when executing software, including data decoded from symbols transmitted through the connector 1314. Processing circuit 1302 further includes at least one of modules and / or circuits 1304, 1306, and 1308. Modules and / or circuits 1304, 1306, and 1308 are software modules operating on processor 1316 or coupled to processor 1316 that reside / store on computer-readable storage medium 1318. Or some combination thereof. Modules and / or circuits 1304, 1306, and / or 1308 may include microcontroller instructions, state machine configuration parameters, or some combination thereof.

  [00107] In one configuration, an apparatus 1300 for wireless communication includes modules and / or circuits 1306, 1312 configured to receive a first sequence of symbols from a first lane of a multi-lane interface 1314; A module and / or circuit 1306 configured to recover a clock signal from the multilane interface 1314, wherein the clock signal is N between successive pairs of symbols in the first sequence of symbols. A module configured to convert a first sequence of symbols into a first set of data bits using a clock signal, including generating edges corresponding to a plurality of transitions in the signaling state of the book wire; And / or circuits 1304 and / or 1308 A module configured to derive a second set of data bits from one or more signals received from a second lane of multi-lane interface 1314 using a clock signal and / or circuit 1304 and / or Or 1308. In one example, the circuits shown in FIGS. 6-9 and 11 provide logic that implements various functions performed by the processing circuit 1302.

  [00108] In certain aspects of the present disclosure, the computer-readable storage medium 1318 stores or maintains one or more instructions. When executed by at least one processor 1316 of processing circuit 1302, the instructions cause processing circuit 1302 to receive a first sequence of symbols from a first lane of multilane interface 1314 and to receive a clock signal from multilane interface 1314. Where the clock signal includes edges corresponding to a plurality of transitions in the signaling state of the N wires between the pair of consecutive symbols in the first sequence of symbols. To convert the first sequence of symbols into a first set of data bits and use data signals from one or more signals received from the second lane of the multi-lane interface 1314 using a clock signal. A second set of can be derived. Each symbol in the sequence of symbols may correspond to a signaling state of N wires.

  [00109] The foregoing means may be implemented using, for example, some combination of processors 206 or 236, physical layer drivers 210 or 240, and storage media 208 and 238.

  [00110] FIG. 14 is a flowchart 1400 illustrating a method for data communication over an N-wire communication link. The communication link is N! Multiple connectors may be included that carry symbols that are encoded using a suitable encoding scheme such as encoding, multiphase encoding, multi-wire differential encoding, and the like. The connector may include conductive wires, optical signal conductors, semiconductor interconnects, and the like. The method may be performed by one or more processors of the receiving device.

  [00111] At step 1402, clock information is embedded in a first sequence of symbols encoding the first data bit. Each of the first sequence of symbols may correspond to the signaling state of the N wires of the first lane of the multilane interface. The clock information may be encoded by using a transcoder to convert the first data bits into a set of transition numbers, and the set of transition numbers to obtain a first sequence of symbols. Can be converted. The second data bits can be encoded into a second sequence of symbols without using a transcoder.

  [00112] In step 1404, a first sequence of symbols is transmitted on the first lane.

  [00113] At step 1406, a second sequence of symbols is transmitted on the second lane of the multi-lane interface. The second sequence of symbols may be encoded with the second data bits and without embedded clock information.

According to some aspects disclosed [00114] herein, first the sequence, N of wires of _N C ₂ pieces of different symbols in the _N C ₂ pieces of differential signals on a pair of symbols May be transmitted by transmitting the first sequence of The second lane may include M wires. Second sequence of symbols may be sent in _M C ₂ pieces of differential signals on _M C ₂ pieces of different pairs of M of wires. The values of M and N may be equal or different.

  [00115] According to some aspects disclosed herein, the second sequence of symbols may be transmitted on the M wires of the serial bus. Transmitting the second sequence of symbols may include transmitting a second set of data in M / 2 differential signals.

  [00116] According to some aspects disclosed herein, each of the first sequence of symbols is transmitted in a different symbol interval. Embedding clock information may be in the signaling state of N wires or the signaling state of one or more wires in the second lane between each pair of consecutive symbols in the first sequence of symbols. Can include causing a transition.

  [00117] According to some aspects disclosed herein, a single transcoder circuit encodes a first data bit into a first sequence of symbols and a second of symbols. Can be used to encode the second data bit in the sequence.

  [00118] In accordance with certain aspects disclosed herein, embedding clock information is the signaling state of N wires between each pair of consecutive symbols in the first sequence of symbols. Or causing a transition in the signaling state of the M wires in the second lane between each pair of consecutive symbols in the second sequence of symbols. The clock information may relate to a transmit clock that is used to encode both the first sequence of symbols and the second sequence of symbols.

  [00119] According to some aspects disclosed herein, the data elements may be partitioned to obtain a first set of data bits and a second set of data bits. The first symbol corresponding to the first set of data bits may be transmitted on the first lane simultaneously with the transmission of the second symbol corresponding to the second set of data bits on the second lane.

  [00120] FIG. 15 is a diagram illustrating a simplified example of a hardware implementation for an apparatus 1500 that utilizes a processing circuit 1502. The processing circuitry generally includes a processor 1516 that may include one or more of a microprocessor, microcontroller, digital signal processor, sequencer, and state machine. Processing circuit 1502 may be implemented using a bus architecture generally represented by bus 1520. Bus 1520 may include any number of interconnect buses and bridges, depending on the specific application of processing circuit 1502 and the overall design constraints. Bus 1520 is represented by a processor 1516, modules and / or circuits 1504, 1506, and 1508, a line interface circuit 1512 that can be configured to communicate through connectors or wires 1514, and a processor-readable / computer-readable storage medium 1518. Various circuits including one or more processors and / or hardware modules are connected together. Bus 1520 may also connect various other circuits, such as timing sources, peripherals, voltage regulators, and power management circuits, but these circuits are well known in the art and therefore no more. Not explained.

  [00121] The processor 1516 is responsible for general processing, including execution of software stored on the computer-readable storage medium 1518. The software, when executed by the processor 1516, causes the processing circuitry 1502 to perform the various functions described above for any particular device. The computer-readable storage medium 1518 may also be used for storing data that is manipulated by the processor 1516 when executing software, including data decoded from symbols transmitted through the connector 1514. Processing circuit 1502 further includes at least one of modules and / or circuits 1504, 1506, and 1508. Modules and / or circuits 1504, 1506, and 1508 are software modules operating on processor 1516 or coupled to processor 1516 that reside / store on computer-readable storage medium 1518. Or some combination thereof. Modules and / or circuits 1504, 1506, and / or 1508 may include microcontroller instructions, state machine configuration parameters, or some combination thereof.

  [00122] In one configuration, an apparatus 1500 for wireless communication includes a module and / or circuit 1504 configured to embed information along with a first data bit encoded in a first sequence of symbols, Module and / or circuits 1506, 1512 configured to transmit a first sequence of symbols in a first lane of a lane interface first lane, and a second of symbols in a second lane of a multi-lane interface Modules and / or circuits 1504, 1506, and / or 1508 configured to transmit the sequence are included. In one example, the circuits shown in FIGS. 6-9 and 11 provide logic that implements various functions performed by the processing circuit 1502.

  [00123] In certain aspects of the present disclosure, the processor-readable / computer-readable storage medium 1518 stores or maintains one or more instructions. When executed by at least one processor 1516 of processing circuit 1502, the instructions cause processor 1516 to embed clock information along with a first data bit encoded in a first sequence of symbols, A first sequence of symbols may be transmitted on the first lane and a second sequence of symbols may be transmitted on the second lane of multilane interface 1514. Each of the first sequence of symbols may correspond to the signaling state of the N wires of the first lane of multilane interface 1514. The second sequence of symbols may be encoded with the second data bits and without embedded clock information.

  [00124] The foregoing means may be implemented using, for example, some combination of processors 206 or 236, physical layer drivers 210 or 240, and storage media 208 and 238.

Exemplary Description of Multi-Wire Symbol Transition Link with Dedicated Clock
[00125] As described above, multi-wire symbol transition clocking may be implemented by embedding a clock into the symbol transition. However, the embedded clock requires clock and data recovery (CDR) logic / circuits at the receiving device to recover the embedded clock from symbol transitions. Such CDR logic / circuits can be complex or expensive to implement with some receiving devices. Embedded clocks can also suffer symbol slip errors due to excessive jitter, lane-to-lane skew, signal spikes, and other causes.

  [00126] In certain aspects of the disclosure, N! Multi-wire bus / link facilitates transmission of symbols such that embedded clocks are encoded / embedded in guaranteed symbol transitions while dedicated clock lines are used to transmit dedicated clocks Can be used for. In other aspects of the present disclosure, the bus / link may be a single-ended multi-wire bus / link. A dedicated clock transmitted over a dedicated clock line allows the receiver to decode symbols transmitted over the multi-wire bus / link without using CDR logic / circuits and without having to rely on embedded clocks. To make it easier. Thus, the use of dedicated clock lines to receive dedicated clocks eliminates the need for receivers to implement CDR logic / circuits, thereby minimizing the complexity and cost associated with such implementations. As well as reducing the symbol slip error associated with the embedded clock.

  [00127] In another aspect, in systems that use dedicated clock lines to transmit / receive clock signals, a separate clock needs to be encoded / embedded in symbol transitions of the sequence of symbols to be transmitted There is no. Therefore, it is not essential for the system to guarantee transitions between each symbol in a sequence of symbols, so the system will interspers different types of symbols on the data lane and across multiple data lanes. Is possible. Moreover, in such systems no clock recovery from symbol transitions can occur, so that circuits / modules for converting raw symbols to symbols with guaranteed transitions may be omitted at the transmitter. , Circuitry / modules for converting symbols with guaranteed transitions to raw symbols may be omitted at the receiver, thus reducing the complexity and cost associated with implementing such circuits / modules. Minimize.

  [00128] In a further aspect, in a system that uses a dedicated clock line to transmit / receive a clock signal, the clock signal is transmitted separately from the data signal, so the direction of the data signal transmission is Unconstrained by direction. Thus, such a system allows a clock signal to be transmitted from a first device to a second device over a dedicated clock line while data / symbols associated with the clock signal are transmitted from the second device to the first device. Allows to be sent. Moreover, such systems can now utilize multiwire bus / link and / or dedicated clock lines for bi-directional transmission. Thus, both the first device and the second device can interleave the lines of the multi-wire bus / link and / or alternately transmit a dedicated clock through the dedicated clock line, thereby transmitting the multi-wire for transmission. Bus / link can be used.

[00129] FIG. 16 is a diagram illustrating a further example of a multilane interface 1600 provided between two devices 1602 and 1632. At transmitter 1602, transcoder 1606 may transmit symbols to be transmitted over a set of N wires on lanes (or “multi-wire links”) 1612 using, for example, N factorial (N!) Coding. It may be used to encode data 1604 and clock information, where N is an integer greater than 2. The clock information is derived from a first transmission clock (eg, DDRCLK X) 1624 or a second transmission clock (eg, DDRCLK Y) 1626 and is at least one of _N C ₂ signals between consecutive symbols. Thus, by ensuring that signaling state transitions occur, it can be encoded in a sequence of symbols transmitted in _N C ₂ differential signals over _N wires. N! When encoding is used to drive N wires, each bit of the symbol is transmitted as a differential signal by one of the set of line drivers 1610, where in the set of line drivers 1610 The differential drivers are coupled to different pairs of N wires. The number of available combinations of wire pairs and signals can be calculated as _N C ₂ , where the number of available combinations is the number of signals that can be transmitted over the N wires. To decide. The number of data bits 1604 that can be encoded in a symbol can be calculated based on the number of available signaling states available for each symbol transmission interval.

  [00130] A termination impedance (usually resistive) couples each of the N wires to a common midpoint in termination network 1628. It will be appreciated that the signaling state of the N wires reflects the combination of currents in the termination network 1628 due to the differential driver 1610 coupled to each wire. It will be further understood that the midpoint of the termination network 1628 is a null point so that the currents in the termination network 1628 cancel each other at the midpoint.

[00131] At least one of the _N C ₂ signals in the link transitions between consecutive symbols. In effect, the transcoder 1606 generates a transition between each pair of symbols transmitted over N wires by producing a sequence of symbols where each symbol is different from the previous symbol. to be certain. In the example shown in FIG. 16, lane 1612 has N = 4 wires and a set of ₄ wires can carry ₄ C ₂ = 6 differential signals. Transcoder 1606 may utilize a mapping scheme to generate raw symbols for transmission on the N wires available on lane 1612. Transcoder 1606 and serializer 1608 cooperate to produce raw symbols for transmission based on input data bits 1604. At receiver 1632, transcoder 1640 may utilize the mapping, for example, to determine the number of transitions that characterize the difference between consecutive raw symbol pairs and symbols in the lookup table. The transcoders 1606, 1640 operate on the basis that each successive pair of raw symbols includes two different symbols.

[00132] The transcoder 1606 in the transmitter 1602 is available for each symbol transition N! -You can choose from one state. In one example, 4! The system 4! For the next symbol to be transmitted in each symbol transition. −1 = 23 signaling states are provided. The bit rate may be calculated as log ₂ (available state) per cycle of the first transmission clock 1624 or the second transmission clock 1626. In systems that use double data rate (DDR) clocking, symbol transitions occur on both the rising and falling edges of the first transmit clock 1624 or the second transmit clock 1626. In one example, since two or more symbols can be transmitted word by word (ie, every transmit clock cycle), the overall available state in the transmit clock cycle is ( _{NC 2} −1) ^2. = (23) ² = 529, and the number of data bits 1604 that can be transmitted per symbol can be calculated as log ₂ (529) = 9.047 bits.

  [00133] In an aspect, the second transmit clock 1626 used to encode the data 1604 may be transmitted to the receiver 1632 using the line driver 1620. For example, the line driver 1620 may generate a clock signal based on the second transmission clock 1626 and transmit the clock signal through the dedicated clock line 1622. Dedicated clock line 1622 is separate and parallel to lane / multi-wire link 1612 and may be limited to communicating clock signals between transmitter 1602 and receiver 1632.

[00134] The receiver 1632 receives a sequence of symbols using a set of line receivers 1634, where each receiver in the set of line receivers 1634 is on one pair of N wires. To determine the difference in signaling state. Thus, _N C ₂ receivers are used in lane 1612, where N represents the number of wires in lane 1612. _N C ₂ receivers 1634 produce a corresponding number of raw symbols as outputs.

  [00135] Receiver 1632 receives a clock signal transmitted over dedicated clock line 1622 using line receiver 1644. When receiving a clock signal through dedicated clock line 1622, line receiver 1644 generates a receive clock (eg, DDRCLK Y) 1656 corresponding to second transmit clock 1626.

[00136] In the illustrated example, lane 1612 has N = 4 wires, and the signal received on the four wires of lane 1612 generates a state transition signal that is provided to deserializer 1638. , Processed by a set of line receivers 1634 including 6 receivers ( ₄ C ₂ = 6). The deserializer 1638 deserializes the symbol based on the state transition signal from the set of line receivers 1634 and the reception clock 1656 (corresponding to the second transmission clock 1626). Receive clock 1656 may be used by external circuitry to receive data provided by transcoder 1640. Transcoder 1640 decodes the block of received symbols from deserializer 1638 by comparing each next symbol with its immediately preceding one. Transcoder 1640 produces output data 1642 that corresponds to data 1604 provided to transmitter 1602. Accordingly, receiver 1632 may utilize a second transmit clock 1626 provided via dedicated clock line 1622 to decode received symbols corresponding to data 1604, so that receiver 1632 is received. It does not require that the CDR logic / circuits recover the first transmit clock 1624 that can be embedded in the transitions between symbols. Thus, the receiver 1632 can ignore the first transmission clock 1624.

  [00137] As shown in the example of FIG. 16, a lane (or "multi-wire link") 1612 may operate according to the following example. In one example, data bits 1604 for transmission through lane (lane X in this example) 1612 are signaled in at least one signal transmitted on the four wires of lane 1612 when transmitted in a predetermined sequence. Received by a transcoder 1606 that generates a set of raw symbols that ensures that the transitions of. The serializer 1608 produces a sequence of symbol values that is provided to a line driver 1610 that determines the signaling state of the four wires in lane 1612 for each symbol interval.

  [00138] In another example, data bits 1604 are received by transcoder 1606 in lane (lane X in this example) 1612. The transcoder 1606 is serialized by a serializer 1608 that converts the set of transition numbers into a sequence of symbol values provided to a line driver 1610 that determines the signaling state of the four wires in lane 1612 for each symbol interval. Generate a set of transition numbers. The sequence of raw symbols ensures that a signaling state transition occurs in at least one signal transmitted on the four wires in lane 1612 between each pair of consecutive symbols.

  [00139] In some embodiments, at least one line / wire of lanes (or "multi-wire links") 1612 is bidirectional. Accordingly, transmitter 1602 may be configured to receive a sequence of symbols transmitted from receiver 1632 over at least one bidirectional line / wire in lane 1612. In a further aspect, dedicated clock line 1622 is bi-directional and can be driven by either transmitter 1602 or receiver 1632 transmitting through lane 1612. For example, transmitter 1602 may be configured to receive a dedicated clock signal from receiver 1632 through dedicated clock line 1622. The dedicated clock signal may be associated with a transmit clock that is used to encode a sequence of symbols transmitted by the receiver over at least one bidirectional line / wire in lane 1612.

  [00140] FIG. 17 illustrates an example of transmitting symbols on multiple data lanes using dedicated clock lines. In example 1700, a first type of symbol 1710 is transmitted on a first data lane (data lane 1) 1704, a second type of symbol 1712 is transmitted on a second data lane (data lane 2) 1706, A third type of symbol 1714 is transmitted on the third data lane (data lane 3) 1708. First type 1710, second type 1712, and third type 1714 symbols may all be transmitted on their respective data lanes according to a clock signal transmitted separately on dedicated clock line 1702.

  [00141] As described above, in systems that use dedicated clock lines to transmit / receive clock signals, a separate clock is encoded into the symbol transition of the sequence of symbols to be transmitted / There is no need to be embedded. Thus, the transmitter may not guarantee signaling state transitions between each symbol in the sequence of symbols. Thus, with reference to example 1750, the transmitter can intersperse different types of symbols over the data lane and across multiple data lanes. For example, a first type symbol 1760, a second type symbol 1762, and a third type symbol 1764 may be interspersed and transmitted on the first data lane (data lane 1) 1754. Moreover, second type symbol 1762, third type symbol 1764, and first type symbol 1760 may be interspersed and transmitted on second data lane (data lane 2) 1756. Also, a third type symbol 1764, a first type symbol 1760, and a second type symbol 1762 may be interspersed and transmitted on the third data lane (data lane 3) 1758.

  [00142] In an aspect, the second type symbol 1762 and the third type symbol 1764 are transmitted on a data lane (eg, the first data lane 1754) without a transition of signaling state between symbols. (See 1766). Moreover, first type symbol 1760 and second type symbol 1762 may be transmitted on a data lane (eg, second data lane 1756) without a transition of signaling state between symbols (see 1768). ). Also, the second type symbol 1762, the third type symbol 1764, and the first type symbol 1760 may be data lanes (e.g., first lanes) without any signaling state transitions between any pair of symbols. 3 data lanes 1758) (see 1770 and 1772). First type symbol 1760, second type symbol 1762, and third type 1764 symbol may all be transmitted on each of the data lanes according to a clock signal transmitted separately on dedicated clock line 1752.

  [00143] FIG. 18 illustrates an example of multi-wire transcoding using dedicated clock lines. In a first example 1800, data bits to be transmitted are received at a transmitter by a bit-to-transition symbol converter (Bits to T) 1802. Based on the data bits, Bits to T 1802 generates a set of raw transition symbols 1804 for transmission over multi-wire link 1820. The set of raw transition symbols 1804 is provided to a transition symbol to symbol converter (T to S) 1806. T to S 1806 selects raw transition symbols for transmission so that signaling state transitions are guaranteed between each symbol, thus allowing clock information to be encoded / embedded in symbol transitions. To do. A symbol output by T to S 1806 may be serialized by a serializer (SER) 1808 based on a clock signal transmitted on dedicated clock line 1812. The SER 1808 produces a sequence of symbols that determines the wire signaling state of the multi-wire link 1820. The sequence of symbols 1814 is provided to the line driver 1810 for transmission over the multiwire link 1820.

  [00144] Still referring to the first example 1800, the process described above with respect to the transmitter is reversed at the receiver. A deserializer (DES) 1824 receives a sequence of symbols 1814 via a line receiver 1822. The DES 1824 deserializes the received symbol based on the clock signal received by the dedicated clock line 1812. The output of DES 1824 is provided to a symbol to transition symbol converter (S to T) 1826. S to T 1826 recovers raw transition symbols 1804 based on the transitions that exist between each deserialized symbol. A transition symbol-to-bit converter (T to Bits) 1828 then converts the recovered raw transition symbols into data bits (Bits).

  [00145] As described above, in systems that use dedicated clock lines to transmit / receive clock signals, separate clocks are encoded into symbol transitions of a sequence of symbols to be transmitted / There is no need to be embedded. Thus, referring to the second example of multi-wire transcoding 1850 using dedicated clock lines, if the clock information is not to be encoded / embedded in symbol transitions, the transmitter may It is not necessary to guarantee the transition between symbols. Moreover, since the clock information is not embedded in the symbol transition at the transmitter or is not recovered from the symbol transition at the receiver, a circuit / module to convert the raw symbol to a symbol with guaranteed transition is transmitted. Circuits / modules for converting symbols with guaranteed transitions to raw symbols may be omitted at the receiver and thus associated with implementing such circuits / modules. Minimize complexity and cost.

  [00146] For example, in the second example 1850, data bits to be transmitted are received by a bit-to-transition symbol converter (Bits to T) 1852 at the transmitter. Based on the data bits, Bits to T 1852 generates a set of raw transition symbols 1854 for transmission over multi-wire link 1870. Since the clock information will not be encoded / embedded in the symbol transitions, the transmitter may not guarantee signaling state transitions between each symbol of the set of symbols to be transmitted. Thus, a transition symbol-to-symbol converter (eg, T to S 1806 of the first example 1800) may be omitted at the transmitter of the second example 1850 and the raw transition symbol 1854 is fed directly to the serializer (SER) 1858. Can be done. Raw transition symbol 1854 may be serialized by SER 1858 based on a clock signal transmitted on dedicated clock line 1862. SER 1858 produces a sequence of symbols that determines the wire signaling state of multi-wire link 1870. A sequence of symbols 1854 is provided to the line driver 1860 for transmission on the multi-wire link 1870.

  [00147] Still referring to the second example 1850, the process described above with respect to the transmitter is reversed at the receiver. A deserializer (DES) 1874 receives a sequence of symbols 1854 via line receiver 1872. The DES 1874 deserializes the received symbols based on the clock signal received on the dedicated clock line 1862 to restore the set of raw transition symbols 1854. In particular, since the clock information was not encoded / embedded in the symbol transitions, the receiver may not recover the raw transition symbols based on the transitions that exist between each deserialized symbol . Thus, a symbol-to-transition symbol converter (eg, S to T 1826 of the first example 1800) may be omitted at the receiver of the second example 1850. A transition symbol to bit converter (T to Bits) 1878 converts the recovered raw transition symbols into data bits (Bits). In an aspect, the second example 1850 improves throughput because it allows one extra state per symbol to be transmitted.

Exemplary receiving device and method at the receiving device
[00148] FIG. 19 supports operations related to communicating data bits over a multi-wire link in accordance with one or more aspects of the present disclosure (eg, aspects relating to the method of FIG. 20 described below). FIG. 11 is a diagram of a configured apparatus (receiving device) 1900. Apparatus 1900 includes a communication interface (eg, in at least one transceiver) 1902, a storage medium 1904, a user interface 1906, a memory device 1908, and processing circuitry 1910.

  [00149] These components are coupled to each other and / or arranged to be in electrical communication with each other via a signaling bus or other suitable component, represented generally by the connecting lines in FIG. Can be done. The signaling bus may include any number of interconnect buses and bridges depending on the specific application of processing circuit 1910 and the overall design constraints. The signaling bus may be configured such that each of communication interface 1902, storage medium 1904, user interface 1906, and memory device 1908 is coupled to processing circuit 1910 and / or in electrical communication with processing circuit 1910. Connect the circuits together. The signaling bus can also connect various other circuits (not shown) such as timing sources, peripherals, voltage regulators, and power management circuits, which are well known in the art. Therefore, no further explanation will be given.

  [00150] Communication interface 1902 may be adapted to facilitate wireless communication of device 1900. For example, communication interface 1902 may include circuitry and / or code (eg, instructions) adapted to facilitate bidirectional communication of information with respect to one or more communication devices in the network. Communication interface 1902 may be coupled to one or more antennas 1912 for wireless communication within a wireless communication system. Communication interface 1902 may be configured with one or more stand-alone receivers and / or transmitters and one or more transceivers. In the illustrated example, communication interface 1902 includes a transmitter 1914 and a receiver 1916.

  [00151] Memory device 1908 may represent one or more memory devices. As shown, memory device 1908 may maintain network related information 1918 along with other information used by apparatus 1900. In some implementations, the memory device 1908 and the storage medium 1904 are implemented as a common memory component. Memory device 1908 may also be used to store data that is manipulated by processing circuitry 1910 or some other component of apparatus 1900.

  [00152] The storage medium 1904 is one or more computer-readable devices, machines for storing code such as processor-executable code or instructions (eg, software, firmware), electronic data, databases, or other digital information. It may represent a readable device and / or a processor readable device. Storage medium 1904 may also be used to store data that is manipulated by processing circuitry 1910 when executing code. Storage medium 1904 may be accessed by a general purpose or special purpose processor, including a portable or permanent storage device, an optical storage device, and various other media that can store, store, or carry code. It can be an available medium.

  [00153] By way of example, and not limitation, storage medium 1904 can be a magnetic storage device (eg, hard disk, floppy disk, magnetic strip), optical disk (eg, compact disk (CD), or digital versatile disk (DVD). ), Smart card, flash memory device (eg card, stick, or key drive), random access memory (RAM), read only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrical erasure Possible PROM (EEPROM), registers, removable disks, and any other suitable medium for storing code that can be accessed and read by a computer. The storage medium 1904 may be embodied in a manufactured product (eg, a computer program product). By way of example, a computer program product may include a computer readable medium in packaging material. In view of the above, in some implementations, the storage medium 1904 may be a non-transitory (eg, tangible) storage medium.

  [00154] The storage medium 1904 may be coupled to the processing circuit 1910 such that the processing circuit 1910 can read information from and write information to the storage medium 1904. That is, examples in which at least one storage medium is integral with processing circuit 1910 and / or at least one storage medium is separate from processing circuit 1910 (eg, external to apparatus 1900 residing in apparatus 1900). Storage medium 1904 may be coupled to processing circuit 1910 such that storage medium 1904 is at least accessible by processing circuit 1910.

  [00155] Code and / or instructions stored by the storage medium 1904, when executed by the processing circuitry 1910, process one or more of the various functions and / or process operations described herein. The circuit 1910 is executed. For example, the storage medium 1904 is configured to coordinate operation in one or more hardware blocks of the processing circuit 1910 as well as utilizes a communication interface 1902 for wireless communication utilizing their respective communication protocols. Configured to include operations.

  [00156] The processing circuit 1910 is generally adapted for processing including execution of code / instructions such as stored on the storage medium 1904. The term “code” or “instruction” as used herein is referred to as, but not limited to, software, firmware, middleware, microcode, or hardware description language. Programming, instructions, instruction set, data, code, code segment, program code, program, subprogram, software module, application, software application, software package, routine, subroutine, object, whether or not called otherwise , And should be interpreted broadly to mean executables, threads of execution, procedures, functions, etc.

  [00157] The processing circuitry 1910 is adapted to acquire, process and / or transmit data, control data access and storage, issue commands, and control other desired operations. Processing circuit 1910 may include circuitry configured to implement the desired code provided by a suitable medium in at least one example. For example, the processing circuit 1910 may be implemented as one or more processors, one or more controllers, and / or other structures configured to execute executable code. Examples of processing circuitry 1910 include general purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) or other programmable logic components, individual gate or transistor logic, individual hardware It may include components, or any combination thereof designed to perform the functions described herein. A general purpose processor may include a microprocessor, as well as any conventional processor, controller, microcontroller, or state machine. The processing circuit 1910 may also include a combination of a DSP and a microprocessor, several microprocessors, one or more microprocessors working with a DSP core, an ASIC and a microprocessor, or any other number of different configurations. Can be implemented as a combination of computing components. These examples of processing circuit 1910 are for illustration purposes and other suitable configurations within the scope of this disclosure are also contemplated.

  [00158] In accordance with one or more aspects of the present disclosure, the processing circuitry 1910 may include features, processes, functions, operations, and / or routines for any or all of the devices described herein. May be adapted to perform any or all of As used herein, the term “adapted” with respect to the processing circuit 1910 is used by the processing circuit 1910 in accordance with various features described herein to identify a particular process, function, operation, and / or routine. May be one or more of being configured, utilized, implemented, and / or programmed.

  [00159] In accordance with at least one example of apparatus 1900, processing circuit 1910 may include features, processes, functions, operations, and / or routines described herein (eg, features, processes, functions described with respect to FIG. 20). A symbol receiving circuit / module 1920, a clock receiving circuit / module 1922, a symbol decoding circuit / module 1924, a symbol transmitting circuit / module 1926, adapted to perform any or all of And one or more of clock transmission circuits / modules 1928.

  [00160] Symbol receiving circuit / module 1920 is adapted to perform several functions related to, for example, receiving a sequence of symbols over a multi-wire link (e.g., in storage medium 1904). Stored symbol receive instructions 1930).

  [00161] Clock receiving circuit / module 1922 is adapted to perform several functions related to, for example, receiving a clock signal via a dedicated clock line (eg, storage medium 1904). Receive clock instructions 1932) stored in a dedicated clock line, separate from the multi-wire link and in parallel.

  [00162] Symbol decoding circuit / module 1924 is adapted to perform several functions related to, for example, decoding a sequence of symbols using a clock signal (e.g., a storage medium). Symbol decode instructions 1934) stored at 1904 may be included. In certain aspects, a second clock signal may be embedded in a guaranteed transition between pairs of consecutive symbols in a sequence of symbols. Accordingly, the symbol decoding circuit / module 1924 ignores the second clock signal, while performing decoding by decoding the sequence of symbols using the clock signal received via the dedicated clock line. Can be configured. Symbol decoding circuit / module 1924 may be configured to perform decoding by converting a sequence of symbols into a set of data bits using a clock signal. The symbol decoding circuit / module 1924 is adapted to perform the conversion by using a transcoder to convert the sequence of symbols into a set of transition numbers, and converting the set of transition numbers into a set of data bits. Can be configured.

  [00163] The symbol transmission circuit / module 1926 relates, for example, to transmitting a second sequence of symbols over at least one bi-directional line of a multi-wire link based on a clock signal received via a dedicated clock line. It may include circuitry and / or instructions (eg, symbol transmission instructions 1936 stored on storage medium 1904) that are adapted to perform several functions.

  [00164] The clock transmission circuit / module 1928 is adapted to perform several functions related to, for example, transmitting a third clock signal over a dedicated clock line (eg, a circuit and / or instructions (eg, Clock transmission instructions 1938) stored in the storage medium 1904 may be included. The third clock signal is associated with a transmit clock used to encode the data bits into a sequence of symbols transmitted by the symbol transmit circuit / module 1926 over at least one bidirectional line of the multi-wire link. obtain.

  [00165] As noted above, instructions stored by the storage medium 1904, when executed by the processing circuitry 1910, are one of various functions and / or process operations described herein. Alternatively, a plurality of processing circuits 1910 are executed. For example, storage medium 1904 may include one or more of receive symbol instructions 1930, receive clock instructions 1932, decode symbol instructions 1934, transmit symbol instructions 1936, and transmit clock instructions 1938.

  [00166] FIG. 20 is a flowchart 2000 illustrating a method of communicating data bits over a multi-wire link. The method may be performed by a receiving device (eg, apparatus 100 of FIG. 1, receiver 1632 of FIG. 16, or apparatus 1900 of FIG. 19).

  [00167] A receiving device receives (2002) a sequence of symbols from a transmitting device (eg, transmitter 1602) over a multi-wire link (eg, multi-wire link 1612). Each symbol in the sequence of symbols may correspond to the signaling state of the N wires of the multiwire link, where N is an integer greater than one. The receiving device further receives a clock signal (eg, DDRCLK Y 1626) via a dedicated clock line (eg, dedicated clock line 1622), where the dedicated clock line is separate and parallel to the multi-wire link ( 2004). The receiving device also decodes the sequence of symbols using the clock signal (2006).

  [00168] In an aspect, a second clock signal (eg, DDRCLK X 1624) may be embedded in a guaranteed transition between pairs of consecutive symbols in a sequence of symbols. Thus, the receiving device decodes the sequence of symbols using the clock signal received via the dedicated clock line, ignoring the second clock signal.

  [00169] In an aspect, a receiving device decodes a sequence of symbols by converting the sequence of symbols into a set of data bits using a clock signal. In a further aspect, the receiving device converts by using a transcoder (eg, transcoder 1640) to convert the sequence of symbols into a set of transition numbers and to convert the set of transition numbers into a set of data bits. Execute.

  [00170] In certain aspects, at least one of the multi-wire links is bidirectional. A receiving device may transmit a second sequence of symbols over at least one bidirectional line based on a clock signal received via a dedicated clock line (2008). In a further aspect, both the receiving device and the transmitting device may utilize the multi-wire link for bidirectional transmission by interleaving the lines of the multi-wire link.

  [00171] In another aspect, the dedicated clock line is bi-directional and can be driven from any device transmitting over a multi-wire link. The receiving device may transmit a third clock signal via a dedicated clock line (2010). The third clock signal may be associated with a transmit clock used to encode the data bits into a sequence of symbols transmitted by the receiving device over at least one bi-directional line. In a further aspect, both the receiving device and the transmitting device may utilize a dedicated clock line by alternately transmitting a dedicated clock signal through the dedicated clock line.

Exemplary transmitting device and method at the transmitting device
[00172] FIG. 21 supports operations related to communicating data bits over a multi-wire link in accordance with one or more aspects of the present disclosure (eg, aspects relating to the method of FIG. 22 described below). FIG. 2 is a diagram of a configured apparatus (transmission device) 2100 Apparatus 2100 includes a communication interface (eg, in at least one transceiver) 2102, a storage medium 2104, a user interface 2106, a memory device 2108, and processing circuitry 2110.

  [00173] These components are coupled to each other and / or arranged to be in electrical communication with each other via a signaling bus or other suitable component, represented generally by the connecting lines in FIG. Can be done. The signaling bus may include any number of interconnect buses and bridges depending on the specific application of the processing circuit 2110 and the overall design constraints. The signaling bus may be configured such that each of the communication interface 2102, the storage medium 2104, the user interface 2106, and the memory device 2108 are coupled to the processing circuit 2110 and / or in electrical communication with the processing circuit 2110. Connect the circuits together. The signaling bus can also connect various other circuits (not shown) such as timing sources, peripherals, voltage regulators, and power management circuits, which are well known in the art. Therefore, no further explanation will be given.

  [00174] Communication interface 2102 may be adapted to facilitate wireless communication of device 2100. For example, the communication interface 2102 may include circuitry and / or code (eg, instructions) adapted to facilitate bidirectional communication of information regarding one or more communication devices in the network. Communication interface 2102 may be coupled to one or more antennas 2112 for wireless communication within a wireless communication system. Communication interface 2102 may be configured with one or more stand-alone receivers and / or transmitters and one or more transceivers. In the illustrated example, communication interface 2102 includes a transmitter 2114 and a receiver 2116.

  [00175] Memory device 2108 may represent one or more memory devices. As shown, memory device 2108 may maintain network related information 2118 along with other information used by apparatus 2100. In some implementations, the memory device 2108 and the storage medium 2104 are implemented as a common memory component. The memory device 2108 may also be used to store data that is manipulated by the processing circuit 2110 or some other component of the apparatus 2100.

  [00176] The storage medium 2104 is one or more computer-readable devices, machines for storing code such as processor-executable code or instructions (eg, software, firmware), electronic data, databases, or other digital information. It may represent a readable device and / or a processor readable device. Storage medium 2104 may also be used to store data that is manipulated by processing circuitry 2110 when executing code. Storage medium 2104 may be accessed by a general purpose or special purpose processor, including a portable or permanent storage device, an optical storage device, and various other media that can store, store, or carry code. Can be any available medium.

  [00177] By way of example, and not limitation, storage medium 2104 includes magnetic storage devices (eg, hard disks, floppy disks, magnetic strips), optical disks (eg, compact disks (CDs) or digital versatile disks (DVDs)), smart cards. Flash memory devices (eg cards, sticks or key drives), random access memory (RAM), read only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM) ), Registers, removable disks, and any other suitable medium for storing code that can be accessed and read by a computer. The storage medium 2104 may be embodied in a manufactured product (eg, a computer program product). By way of example, a computer program product may include a computer readable medium in packaging material. In view of the above, in some implementations, the storage medium 2104 may be a non-transitory (eg, tangible) storage medium.

  [00178] The storage medium 2104 may be coupled to the processing circuit 2110 such that the processing circuit 2110 can read information from and write information to the storage medium 2104. That is, examples in which at least one storage medium is integral with processing circuit 2110 and / or at least one storage medium is separate from processing circuit 2110 (eg, external to apparatus 2100 residing in apparatus 2100 Storage medium 2104 may be coupled to processing circuit 2110 such that storage medium 2104 is accessible by at least processing circuit 2110, including examples of

  [00179] Code and / or instructions stored by the storage medium 2104, when executed by the processing circuitry 2110, process one or more of the various functions and / or process operations described herein. The circuit 2110 is executed. For example, the storage medium 2104 is configured to coordinate operations in one or more hardware blocks of the processing circuit 2110, and utilizes the communication interface 2102 for wireless communication utilizing their respective communication protocols. Configured to include operations.

  [00180] The processing circuitry 2110 is generally adapted for processing that includes the execution of code / instructions as stored on the storage medium 2104. The term “code” or “instruction” as used herein is referred to as, but not limited to, software, firmware, middleware, microcode, or hardware description language. Programming, instructions, instruction set, data, code, code segment, program code, program, subprogram, software module, application, software application, software package, routine, subroutine, object, whether or not called otherwise , And should be interpreted broadly to mean executables, threads of execution, procedures, functions, etc.

  [00181] The processing circuitry 2110 is adapted to obtain, process and / or transmit data, control data access and storage, issue commands, and control other desired operations. Processing circuit 2110 may include circuitry configured to implement the desired code provided by a suitable medium in at least one example. For example, the processing circuit 2110 may be implemented as one or more processors, one or more controllers, and / or other structures configured to execute executable code. Examples of processing circuitry 2110 include general purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) or other programmable logic components, individual gates or transistor logic, individual hardware It may include components, or any combination thereof designed to perform the functions described herein. A general purpose processor may include a microprocessor, as well as any conventional processor, controller, microcontroller, or state machine. The processing circuit 2110 may also include a combination of a DSP and a microprocessor, several microprocessors, one or more microprocessors that work with the DSP core, an ASIC and a microprocessor, or any other number of different configurations. Can be implemented as a combination of computing components. These examples of processing circuit 2110 are for illustration purposes and other suitable configurations within the scope of this disclosure are also contemplated.

  [00182] In accordance with one or more aspects of the present disclosure, the processing circuit 2110 may include features, processes, functions, operations, and / or routines for any or all of the devices described herein. May be adapted to perform any or all of As used herein, the term “adapted” with respect to processing circuit 2110 refers to processing circuit 2110 having a particular process, function, operation, and / or routine according to various features described herein. May be one or more of being configured, utilized, implemented, and / or programmed.

  [00183] In accordance with at least one example of the apparatus 2100, the processing circuitry 2110 may include features, processes, functions, operations, and / or routines described herein (eg, features, processes, functions described with respect to FIG. 22). A clock embedding circuit / module 2120, a symbol transmission circuit / module 2122, a clock transmission circuit / module 2124, a symbol reception circuit / module 2126, adapted to perform any or all of One or more of a clock receiving circuit / module 2128 and an encoding circuit / module 2140 may be included.

  [00184] Encoding circuit / module 2140, for example, is adapted to perform several functions related to encoding data bits into a sequence of symbols (eg, storage medium 2104). The encoding instructions 2142) stored in the Encoding circuit / module 2140 may be configured to perform encoding by converting data bits into a set of transition numbers and converting the set of transition numbers to obtain a sequence of symbols.

  [00185] The clock embedding circuit / module 2120 may be adapted to perform several functions related to, for example, embedding the second clock signal in the sequence of symbols (eg, in the storage medium 2104). Stored clock embedding instructions 2130), where the second clock signal is embedded in a guaranteed transition between pairs of consecutive symbols in the sequence of symbols.

  [00186] Symbol transmission circuit / module 2122 may be adapted to perform several functions related to, for example, transmitting a sequence of symbols over a multi-wire link (e.g., in storage medium 2104). Stored symbol transmission instructions 2132).

  [00187] Clock transmission circuitry / module 2124 is adapted to perform several functions related to, for example, transmitting a clock signal associated with a sequence of symbols via a dedicated clock line, and / or instructions (Eg, a clock transmission instruction 2134 stored in the storage medium 2104), where the dedicated clock line is separate and parallel to the multi-wire link.

  [00188] The symbol receiver circuit / module 2126 relates to receiving a second sequence of symbols over at least one bi-directional line of a multi-wire link, for example, based on a clock signal transmitted via a dedicated clock signal. It may include circuitry and / or instructions (eg, receive symbol instructions 2136 stored in storage medium 2104) that are adapted to perform some functions.

  [00189] The clock receiving circuit / module 2128 is adapted to perform several functions related to, for example, receiving a third clock signal via a dedicated clock line (eg, circuitry and / or instructions (eg, Clock receive instructions 2138) stored in storage medium 2104 may be included. The third clock signal is associated with a transmit clock used to encode the data bits into a sequence of symbols received by symbol receiver circuit / module 2126 over at least one bidirectional line of the multi-wire link. obtain.

  [00190] As noted above, instructions stored by the storage medium 2104, when executed by the processing circuitry 2110, are one of the various functions and / or process operations described herein. Alternatively, a plurality of processing circuits 2110 are executed. For example, the storage medium 2104 may include one or more of a clock embedding instruction 2130, a symbol transmission instruction 2132, a clock transmission instruction 2134, a symbol reception instruction 2136, a clock reception instruction 2138, and an encoding instruction 2142.

  [00191] FIG. 22 is a flowchart 2200 illustrating a method of communicating data bits over a multi-wire link. The method may be performed by a transmitting device (eg, apparatus 100 of FIG. 1, transmitter 1602 of FIG. 16, or apparatus 2100 of FIG. 21).

  [00192] The transmitting device encodes data bits (eg, Bits X 1604) into a sequence of symbols (2202). In addition, or optionally, the transmitting device embeds a second clock signal (eg, DDRCLK X 1624) in the sequence of symbols, where the second clock signal is the number of consecutive symbols in the sequence of symbols. Embedded in guaranteed transitions between pairs (2204). Each symbol in the sequence of symbols may correspond to a signaling state of N wires of a multi-wire link (eg, multi-wire link 1612), where N is an integer greater than one. The transmitting device further transmits (2206) the sequence of symbols over the multi-wire link. The transmitting device also transmits a clock signal (eg, DDRCLK Y 1626) associated with the sequence of symbols via a dedicated clock line (eg, dedicated clock line 1622), where the dedicated clock line is separate from the multi-wire link. And in parallel (2208).

  [00193] In an aspect, a transmitting device may use a transcoder (eg, transcoder 1606) to convert data bits into a set of transition numbers, and convert the set of transition numbers into a sequence of symbols, Encode the data bits into a sequence of symbols.

  [00194] In some embodiments, at least one line of the multi-wire link is bidirectional. The transmitting device may receive a second sequence of symbols from the receiving device over at least one bidirectional line 2210. In a further aspect, both the receiving device and the transmitting device may utilize the multi-wire link for bidirectional transmission by interleaving the lines of the multi-wire link.

  [00195] In another aspect, the dedicated clock line is bidirectional and can be driven from any device transmitting over a multi-wire link. The transmitting device may receive the third clock signal via a dedicated clock line. The third clock signal may be associated with a transmission clock used to encode data bits into a sequence of symbols received by the transmitting device over at least one bidirectional line 2212. In a further aspect, both the receiving device and the transmitting device may utilize a dedicated clock line by alternately transmitting a dedicated clock signal through the dedicated clock line.

  [00196] It is to be understood that the specific order or hierarchy of steps in the disclosed processes is an example of an exemplary approach. It should be understood that a specific order or hierarchy of steps in the process can be reconfigured based on design preferences. The accompanying method claims present elements of the various steps in a sample order, and are not intended to be limited to the specific order or hierarchy presented.

  [00197] The above description is provided to enable any person skilled in the art to perform the various aspects described herein. Various modifications to these aspects should be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Accordingly, the claims are not to be limited to the embodiments shown herein but are to be accorded the maximum scope consistent with the claim language, where reference to singular elements is Unless stated otherwise, it does not mean “one and only”, but “one or more”. Unless otherwise specified, the term “several” means “one or more”. All structural and functional equivalents for the elements of the various aspects described throughout this disclosure that are known to those of skill in the art or that will be known later are set forth herein by reference. And is intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be publicly provided, whether such disclosure is explicitly recited in the claims. No claim element should be construed as a means plus function unless the element is expressly recited using the phrase “means for.”

[00197] The above description is provided to enable any person skilled in the art to perform the various aspects described herein. Various modifications to these aspects should be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Accordingly, the claims are not to be limited to the embodiments shown herein but are to be accorded the maximum scope consistent with the claim language, where reference to singular elements is Unless stated otherwise, it does not mean “one and only”, but “one or more”. Unless otherwise specified, the term “several” means “one or more”. All structural and functional equivalents for the elements of the various aspects described throughout this disclosure that are known to those of skill in the art or that will be known later are set forth herein by reference. And is intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be publicly provided, whether such disclosure is explicitly recited in the claims. No claim element should be construed as a means plus function unless the element is expressly recited using the phrase “means for.”
The invention described in the scope of claims at the beginning of the application of the present application will be added below.
[C1] receiving a sequence of symbols over a multi-wire link,
Receiving a clock signal via a dedicated clock line, wherein the dedicated clock line is separate and parallel to the multi-wire link;
Decode the sequence of symbols using the clock signal
A receiving device comprising a processing circuit configured as follows.
[C2] a second clock signal is embedded in a guaranteed transition between pairs of consecutive symbols in the sequence of symbols;
C1, wherein the processing circuit is configured to decode the sequence of symbols using the clock signal received via the dedicated clock line while ignoring the second clock signal. Receiving device.
[C3] The receiving device of C1, wherein the processing circuit configured to decode is further configured to convert the sequence of symbols into a set of data bits using the clock signal.
[C4] the processing circuit configured to convert the sequence of symbols into the set of data bits;
Using a transcoder to convert the sequence of symbols into a set of transition numbers;
The receiving device of C3, configured to convert the set of transition numbers to the set of data bits.
[C5] The receiving device according to C1, wherein each symbol in the sequence of symbols corresponds to a signaling state of N wires of the multi-wire link, and N is an integer greater than one.
[C6] The receiving device according to C1, wherein at least one of the multi-wire links is bidirectional.
[C7] The processing circuit is further configured to transmit a second sequence of symbols over the at least one bidirectional line based on the clock signal received via the dedicated clock line. The receiving device according to C6.
[C8] The receiving device of C7, wherein the dedicated clock line is bidirectional and can be driven from any device transmitting over the multi-wire link.
[C9] A method of data communication in a receiving device,
Receiving a sequence of symbols over a multi-wire link;
Receiving a clock signal via a dedicated clock line, and the dedicated clock line is separate and parallel to the multi-wire link;
Decoding the sequence of symbols using the clock signal.
[C10] a second clock signal is embedded in a guaranteed transition between pairs of consecutive symbols in the sequence of symbols;
The method of C9, wherein the sequence of symbols is decoded using the clock signal received via the dedicated clock line while ignoring the second clock signal.
[C11] The method of C9, wherein the decoding includes converting the sequence of symbols into a set of data bits using the clock signal.
[C12] converting the sequence of symbols into the set of data bits;
Using a transcoder to convert the sequence of symbols into a set of transition numbers;
Converting the set of transition numbers into the set of data bits.
[C13] The method of C9, wherein each symbol in the sequence of symbols corresponds to a signaling state of N wires of the multi-wire link, and N is an integer greater than one.
[C14] The method of C9, wherein at least one of the multi-wire links is bidirectional.
[C15] The method of C14, further comprising transmitting a second sequence of symbols over the at least one bidirectional line based on the clock signal received via the dedicated clock line.
[C16] The method of C15, wherein the dedicated clock line is bidirectional and can be driven from any device transmitting over the multi-wire link.
[C17] encode the data bits into a sequence of symbols;
Sending a sequence of said symbols over a multi-wire link;
Transmitting a clock signal associated with the sequence of symbols via a dedicated clock line, the dedicated clock line being separate and parallel to the multi-wire link;
A transmitting device comprising a processing circuit configured as follows.
[C18] The processing circuit is further configured to embed a second clock signal in the sequence of symbols, the second clock signal between successive pairs of symbols in the sequence of symbols. The transmitting device according to C17, which is embedded in the guaranteed transition.
[C19] The processing circuit configured to encode the data bits further comprises:
Using a transcoder to convert the data bits into a set of transition numbers;
The transmitting device of C17, configured to convert the set of transition numbers to obtain the sequence of symbols.
[C20] The transmitting device according to C17, wherein each symbol in the sequence of symbols corresponds to a signaling state of N wires of the multi-wire link, and N is an integer greater than one.
[C21] The transmitting device according to C17, wherein at least one of the multi-wire links is bidirectional.
[C22] The processing circuit is further configured to receive a second sequence of symbols over the at least one bidirectional line based on the clock signal transmitted over the dedicated clock line. The transmitting device according to C21.
[C23] The transmitting device according to C22, wherein the dedicated clock line is bidirectional and can be driven from any device transmitting over the multi-wire link.
[C24] A method of data communication in a transmitting device,
Encoding the data bits into a sequence of symbols;
Transmitting the sequence of symbols over a multi-wire link;
Transmitting a clock signal associated with the sequence of symbols via a dedicated clock line, the dedicated clock line being separate and parallel to the multi-wire link.
[C25] further comprising embedding a second clock signal in the sequence of symbols, wherein the second clock signal is in a guaranteed transition between pairs of consecutive symbols in the sequence of symbols. The method of C24, wherein the method is embedded.
[C26] encoding the data bits;
Using a transcoder to convert the data bits into a set of transition numbers;
Transforming the set of transition numbers to obtain the sequence of symbols.
[C27] The method of C24, wherein each symbol in the sequence of symbols corresponds to a signaling state of N wires of the multi-wire link, and N is an integer greater than one.
[C28] The method of C24, wherein at least one of the multi-wire links is bidirectional.
[C29] The method of C28, further comprising receiving a second sequence of symbols over the at least one bidirectional line based on the clock signal transmitted over the dedicated clock line.
[C30] The method of C29, wherein the dedicated clock line is bidirectional and can be driven from any device transmitting over the multi-wire link.

Claims (30)

Receive a sequence of symbols over a multi-wire link,
Receiving a clock signal via a dedicated clock line, wherein the dedicated clock line is separate and parallel to the multi-wire link;
A receiving device comprising processing circuitry configured to decode the sequence of symbols using the clock signal. A second clock signal is embedded in a guaranteed transition between pairs of consecutive symbols in the sequence of symbols;
The processing circuit is configured to decode the sequence of symbols using the clock signal received via the dedicated clock line while ignoring the second clock signal. The receiving device described in.   The receiving device of claim 1, wherein the processing circuitry configured to decode is further configured to convert the sequence of symbols into a set of data bits using the clock signal. The processing circuit configured to convert the sequence of symbols into the set of data bits;
Using a transcoder to convert the sequence of symbols into a set of transition numbers;
4. A receiving device according to claim 3, configured to convert the set of transition numbers into the set of data bits.   The receiving device according to claim 1, wherein each symbol in the sequence of symbols corresponds to a signaling state of N wires of the multi-wire link, where N is an integer greater than one.   The receiving device of claim 1, wherein at least one line of the multi-wire link is bidirectional.   The processing circuit is further configured to transmit a second sequence of symbols over the at least one bidirectional line based on the clock signal received via the dedicated clock line. The receiving device described in.   8. A receiving device according to claim 7, wherein the dedicated clock line is bidirectional and can be driven from any device transmitting over the multi-wire link. A method of data communication in a receiving device, comprising:
Receiving a sequence of symbols over a multi-wire link;
Receiving a clock signal via a dedicated clock line, and the dedicated clock line is separate and parallel to the multi-wire link;
Decoding the sequence of symbols using the clock signal. A second clock signal is embedded in a guaranteed transition between pairs of consecutive symbols in the sequence of symbols;
The method of claim 9, wherein the sequence of symbols is decoded using the clock signal received via the dedicated clock line while ignoring the second clock signal.   The method of claim 9, wherein the decoding comprises converting the sequence of symbols into a set of data bits using the clock signal. Converting the sequence of symbols into the set of data bits;
Using a transcoder to convert the sequence of symbols into a set of transition numbers;
The method of claim 11, comprising converting the set of transition numbers into the set of data bits.   The method of claim 9, wherein each symbol in the sequence of symbols corresponds to a signaling state of N wires of the multi-wire link, where N is an integer greater than one.   The method of claim 9, wherein at least one line of the multi-wire link is bidirectional.   15. The method of claim 14, further comprising transmitting a second sequence of symbols over the at least one bidirectional line based on the clock signal received via the dedicated clock line.   The method of claim 15, wherein the dedicated clock line is bidirectional and can be driven from any device transmitting over the multi-wire link. Encode data bits into a sequence of symbols;
Sending a sequence of said symbols over a multi-wire link;
Transmitting a clock signal associated with the sequence of symbols via a dedicated clock line, the dedicated clock line being separate and parallel to the multi-wire link;
A transmitting device comprising a processing circuit configured as follows.   The processing circuit is further configured to embed a second clock signal in the sequence of symbols, the second clock signal being guaranteed between successive pairs of symbols in the sequence of symbols. The transmitting device of claim 17, embedded in a transition. The processing circuitry configured to encode the data bits further comprises:
Using a transcoder to convert the data bits into a set of transition numbers;
The transmitting device of claim 17, configured to convert the set of transition numbers to obtain the sequence of symbols.   The transmitting device according to claim 17, wherein each symbol in the sequence of symbols corresponds to a signaling state of N wires of the multi-wire link, and N is an integer greater than one.   The transmitting device of claim 17, wherein at least one line of the multi-wire link is bidirectional.   22. The processing circuit is further configured to receive a second sequence of symbols over the at least one bidirectional line based on the clock signal transmitted over the dedicated clock line. Transmitting device as described in.   23. A transmitting device according to claim 22, wherein the dedicated clock line is bidirectional and can be driven from any device transmitting over the multi-wire link. A method of data communication in a transmitting device, comprising:
Encoding the data bits into a sequence of symbols;
Transmitting the sequence of symbols over a multi-wire link;
Transmitting a clock signal associated with the sequence of symbols via a dedicated clock line, the dedicated clock line being separate and parallel to the multi-wire link.   Further comprising embedding a second clock signal in the sequence of symbols, wherein the second clock signal is embedded in a guaranteed transition between pairs of consecutive symbols in the sequence of symbols; 25. A method according to claim 24. Encoding the data bits;
Using a transcoder to convert the data bits into a set of transition numbers;
25. The method of claim 24, comprising transforming the set of transition numbers to obtain the sequence of symbols.   25. The method of claim 24, wherein each symbol in the sequence of symbols corresponds to a signaling state of N wires of the multi-wire link, where N is an integer greater than one.   25. The method of claim 24, wherein at least one line of the multi-wire link is bidirectional.   30. The method of claim 28, further comprising receiving a second sequence of symbols over the at least one bidirectional line based on the clock signal transmitted over the dedicated clock line.   30. The method of claim 29, wherein the dedicated clock line is bi-directional and can be driven from any device transmitting over the multi-wire link.

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