EP3360278A1 - Multi-lane n-factorial encoded and other multi-wire communication systems - Google Patents

Multi-lane n-factorial encoded and other multi-wire communication systems

Info

Publication number
EP3360278A1
EP3360278A1 EP16770840.3A EP16770840A EP3360278A1 EP 3360278 A1 EP3360278 A1 EP 3360278A1 EP 16770840 A EP16770840 A EP 16770840A EP 3360278 A1 EP3360278 A1 EP 3360278A1
Authority
EP
European Patent Office
Prior art keywords
symbols
sequence
clock signal
clock
lane
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP16770840.3A
Other languages
German (de)
English (en)
French (fr)
Inventor
Shoichiro Sengoku
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US14/875,592 external-priority patent/US9735948B2/en
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of EP3360278A1 publication Critical patent/EP3360278A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/14—Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems

Definitions

  • the present disclosure relates generally to data communications interfaces, and more particularly, multi-lane, multi-wire data communication interfaces.
  • Manufacturers of mobile devices may obtain components of the mobile devices from various sources, including different manufacturers.
  • an application processor in a cellular phone may be obtained from a first manufacturer, while the display for the cellular phone may be obtained from a second manufacturer.
  • the application processor and a display or other device may be interconnected using a standards-based or proprietary physical interface.
  • a display may provide an interface that conforms to the Display System Interface (DSI) standard specified by the Mobile Industry Processor Interface Alliance (MIPI).
  • DSI Display System Interface
  • MIPI Mobile Industry Processor Interface Alliance
  • a multi-signal data transfer system may employ multi-wire differential signaling such as 3-phase or N-factorial (N! ) low-voltage differential signaling (LVDS), transcoding (e.g., the digital -to-digital data conversion of one encoding type to another) may be performed to embed symbol clock information by causing a symbol transition at every symbol cycle.
  • Embedding clock information by transcoding is an effective way to minimize skew between clock and data signals, as well as to eliminate the necessity of a phase-locked loop (PLL) to recover the clock information from the data signals.
  • PLL phase-locked loop
  • Embodiments disclosed herein provide systems, methods and apparatus related to multi-lane, multi-wire interfaces.
  • a method of data communications at a receiving device includes receiving a sequence of symbols over a multi-wire link. Each symbol in the sequence of symbols corresponds to a signaling state of N wires of the multi-wire link, where N is an integer greater than 1.
  • the method further includes receiving a clock signal via a dedicated clock line, wherein the dedicated clock line is separate from, and in parallel with, the multi-wire link, and decoding the sequence of symbols using the clock signal.
  • a second clock signal is embedded in guaranteed transitions between pairs of consecutive symbols in the sequence of symbols. Accordingly, the method decodes the sequence of symbols using the clock signal received via the dedicated clock line while ignoring the second clock signal.
  • the decoding includes converting the sequence of symbols to a set of data bits using the clock signal.
  • the converting the sequence of symbols to the set of data bits includes using a transcoder to convert the sequence of symbols to a set of transition numbers and converting the set of transition numbers to the set of data bits.
  • At least one line of the multi-wire link is bidirectional.
  • the method further includes transmitting a second sequence of symbols over the at least one bi-directional line based on the clock signal received via the dedicated clock line.
  • the dedicated clock line is bi-directional and can be driven from any device transmitting over the multi-wire link.
  • the method further includes transmitting a third clock signal via the dedicated clock line.
  • the third clock signal may be associated with a transmit clock used to encode data bits into a sequence of symbols transmitted over the at least one bi-directional line.
  • a receiving device includes a processing circuit.
  • a memory may be coupled to the processing circuit.
  • the processing circuit is configured to receive a sequence of symbols over a multi-wire link, receive a clock signal via a dedicated clock line, wherein the dedicated clock line is separate from, and in parallel with, the multi-wire link, and decode the sequence of symbols using the clock signal.
  • an apparatus includes means for receiving a sequence of symbols over a multi-wire link, means for receiving a clock signal via a dedicated clock line, wherein the dedicated clock line is separate from, and in parallel with, the multi-wire link, and means for decoding the sequence of symbols using the clock signal.
  • a processor-readable storage medium has one or more instructions stored or maintained thereon.
  • the instructions may cause the at least one processing circuit to receive a sequence of symbols over a multi-wire link, receive a clock signal via a dedicated clock line, wherein the dedicated clock line is separate from, and in parallel with, the multi-wire link, and decode the sequence of symbols using the clock signal.
  • a method of data communications at a transmitting device includes encoding data bits into a sequence of symbols, optionally embedding a second clock signal in the sequence of symbols, wherein the second clock signal is embedded in guaranteed transitions between pairs of consecutive symbols in the sequence of symbols.
  • Each symbol in the sequence of symbols corresponds to a signaling state of N wires of a multi-wire link, where N is an integer greater than 1.
  • the method further includes transmitting the sequence of symbols over a multi-wire link, and transmitting a clock signal associated with the sequence of symbols via a dedicated clock line, wherein the dedicated clock line is separate from, and in parallel with, the multi-wire link.
  • the encoding the data bits includes using a transcoder to convert the data bits to a set of transition numbers and converting the set of transition numbers to obtain the sequence of symbols.
  • At least one line of the multi-wire link is bidirectional.
  • the method further includes receiving a second sequence of symbols over the at least one bi-directional line based on the clock signal transmitted via the dedicated clock line.
  • the dedicated clock line is bi-directional and can be driven from any device transmitting over the multi-wire link.
  • the method further includes receiving a third clock signal via the dedicated clock line.
  • the third clock signal may be associated with a transmit clock used to encode data bits into a sequence of symbols received over the at least one bi-directional line.
  • a transmitting device includes a processing circuit.
  • the processing circuit may be coupled to a memory.
  • the processing circuit is configured to encode data bits into a sequence of symbols, optionally embed a second clock signal in the sequence of symbols, wherein the second clock signal is embedded in guaranteed transitions between pairs of consecutive symbols in the sequence of symbols, transmit the sequence of symbols over a multi-wire link, and transmit a clock signal associated with the sequence of symbols via a dedicated clock line, wherein the dedicated clock line is separate from, and in parallel with, the multi-wire link.
  • an apparatus includes means for encoding data bits into a sequence of symbols using a clock signal, means for optionally embedding a second clock signal in the sequence of symbols, wherein the second clock signal is embedded in guaranteed transitions between pairs of consecutive symbols in the sequence of symbols, means for transmitting the sequence of symbols over a multi-wire link, and means for transmitting a clock signal associated with the sequence of symbols via a dedicated clock line, wherein the dedicated clock line is separate from, and in parallel with, the multi-wire link.
  • a processor-readable storage medium has one or more instructions stored or maintained thereon.
  • the instructions may cause the at least one processing circuit to encode data bits into a sequence of symbols, optionally embed a second clock signal in the sequence of symbols, wherein the second clock signal is embedded in guaranteed transitions between pairs of consecutive symbols in the sequence of symbols, transmit the sequence of symbols over a multi-wire link, and transmit a clock signal associated with the sequence of symbols via a dedicated clock line, wherein the dedicated clock line is separate from, and in parallel with, the multi- wire link.
  • FIG. 1 depicts an apparatus employing a data link between integrated circuit (IC) devices that selectively operates according to one of plurality of available standards.
  • IC integrated circuit
  • FIG. 2 illustrates a system architecture for an apparatus employing a data link between IC devices.
  • FIG. 3 illustrates a CDR circuit that may be used in an N! communication interface.
  • FIG. 4 illustrates timing of certain signals generated by the CDR circuit of FIG.
  • FIG. 5 illustrates an example of a basic N! multi-lane interface.
  • FIG. 6 illustrates a first example of a multi-lane interface provided according to one or more aspects disclosed herein.
  • FIG. 7 illustrates a second example of a multi-lane interface provided according to one or more aspects disclosed herein.
  • FIG. 8 illustrates a third example of a multi-lane interface provided according to one or more aspects disclosed herein.
  • FIG. 9 illustrates a fourth example of a multi-lane interface provided according to one or more aspects disclosed herein.
  • FIG. 10 is a timing diagram illustrating the ordering of data transmitted on a multi-lane interface provided according to one or more aspects disclosed herein.
  • FIG. 11 illustrates a fifth example of a multi-lane interface provided according to one or more aspects disclosed herein.
  • FIG. 12 is a flow chart of a method for operating a receiver in a multi-lane N- wire interface provided according to one or more aspects disclosed herein.
  • FIG. 13 is a diagram illustrating a simplified example of a receiver in a multi- lane N-wire interface provided according to one or more aspects disclosed herein.
  • FIG. 14 is a flow chart of a method for operating a transmitter in a multi-lane N- wire interface provided according to one or more aspects disclosed herein.
  • FIG. 15 is a diagram illustrating a simplified example of a transmitter in a multi- lane N-wire interface provided according to one or more aspects disclosed herein.
  • FIG. 16 is a diagram illustrating a further example of a multi-lane interface provided between two devices according to one or more aspects disclosed herein.
  • FIG. 17 illustrates examples of transmitting symbols on multiple data lanes using a dedicated clock line.
  • FIG. 18 illustrates examples of multi-wire transcoding using a dedicated clock line.
  • FIG. 19 is an illustration of an apparatus (receiving device) configured to support operations related to communicating data bits over a multi-wire link according to one or more aspects disclosed herein.
  • FIG. 20 is a flowchart illustrating a method of a receiving device for communicating data bits over a multi-wire link.
  • FIG. 21 is an illustration of an apparatus (transmitting device) configured to support operations related to communicating data bits over a multi-wire link according to one or more aspects disclosed herein.
  • FIG. 22 is a flowchart illustrating a method of a transmitting device for communicating data bits over a multi-wire link.
  • ком ⁇ онент As used in this application, the terms "component,” “module,” “system” and the like are intended to include a computer-related entity, such as, but not limited to hardware, firmware, a combination of hardware and software, software, or software in execution.
  • a component may be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program and/or a computer.
  • both an application running on a computing device and the computing device can be a component.
  • One or more components can reside within a process and/or thread of execution and a component may be localized on one computer and/or distributed between two or more computers.
  • these components can execute from various computer readable media having various data structures stored thereon.
  • the components may communicate by way of local and/or remote processes such as in accordance with a signal having one or more data packets, such as data from one component interacting with another component in a local system, distributed system, and/or across a network such as the Internet with other systems by way of the signal.
  • the term "or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless specified otherwise, or clear from the context, the phrase “X employs A or B” is intended to mean any of the natural inclusive permutations. That is, the phrase “X employs A or B” is satisfied by any of the following instances: X employs A; X employs B; or X employs both A and B.
  • the articles “a” and “an” as used in this application and the appended claims should generally be construed to mean “one or more” unless specified otherwise or clear from the context to be directed to a singular form.
  • FIG. 1 depicts an apparatus that may employ a communication link between IC devices.
  • the apparatus 100 may include a wireless communication device that communicates through a radio frequency (RF) transceiver with a radio access network (RAN), a core access network, the Internet and/or another network.
  • the apparatus 100 may include a communications transceiver 106 operably coupled to processing circuit 102.
  • the processing circuit 102 may comprise one or more IC devices, such as an application specific integrated circuit (ASIC) 108.
  • ASIC application specific integrated circuit
  • the ASIC 108 may include one or more processing devices, logic circuits, and so on.
  • the processing circuit 102 may include and/or be coupled to processor readable storage such as a memory 112 that may maintain instructions and data that may be executed by processing circuit 102.
  • the processing circuit 102 may be controlled by one or more of an operating system and an application programming interface (API) 110 layer that supports and enables execution of software modules residing in storage media, such as the memory device 112 of the wireless device.
  • the memory device 112 may include read only memory (ROM) or random access memory (RAM), electrically erasable programmable ROM (EEPROM), flash cards, or any memory device that can be used in processing systems and computing platforms.
  • ROM read only memory
  • RAM random access memory
  • EEPROM electrically erasable programmable ROM
  • flash cards or any memory device that can be used in processing systems and computing platforms.
  • the processing circuit 102 may include or access a local database 114 that can maintain operational parameters and other information used to configure and operate the apparatus 100.
  • the local database 114 may be implemented using one or more of a database module, flash memory, magnetic media, EEPROM, optical media, tape, soft or hard disk, or the like.
  • the processing circuit may also be operably coupled to external devices such as an antenna 122, a display 124, operator controls, such as button 128 and keypad 126 among other components.
  • FIG. 2 is a block schematic illustrating certain aspects of an apparatus 200 connected to a communications bus, where the apparatus 200 may be embodied in one or more of a wireless mobile device, a mobile telephone, a mobile computing system, a wireless telephone, a notebook computer, a tablet computing device, a media player, s gaming device, or the like.
  • the apparatus 200 may comprise a plurality of IC devices 202 and 230 that exchange data and control information through a communication link 220.
  • the communication link 220 may be used to connect IC devices 202 and 230 that are located in close proximity to one another, or physically located in different parts of the apparatus 200.
  • the communication link 220 may be provided on a chip carrier, substrate or circuit board that carries the IC devices 202 and 230.
  • a first IC device 202 may be located in a keypad section of a flip-phone while a second IC device 230 may be located in a display section of the flip-phone.
  • a portion of the communication link 220 may comprise a cable or optical connection.
  • the communication link 220 may include multiple channels 222, 224 and 226.
  • One or more channels 226 may be bidirectional, and may operate in half-duplex and/or full-duplex modes.
  • One or more channels 222 and 224 may be unidirectional.
  • the communication link 220 may be asymmetrical, providing higher bandwidth in one direction.
  • a first communications channel 222 may be referred to as a forward link 222 while a second communications channel 224 may be referred to as a reverse link 224.
  • the first IC device 202 may be designated as a host system or transmitter, while the second IC device 230 may be designated as a client system or receiver, even if both IC devices 202 and 230 are configured to transmit and receive on the communications link 222.
  • the forward link 222 may operate at a higher data rate when communicating data from a first IC device 202 to a second IC device 230, while the reverse link 224 may operate at a lower data rate when communicating data from the second IC device 230 to the first IC device 202.
  • the IC devices 202 and 230 may each have a processor or other processing and/or computing circuit or device 206, 236.
  • the first IC device 202 may perform core functions of the apparatus 200, including maintaining wireless communications through a wireless transceiver 204 and an antenna 214, while the second IC device 230 may support a user interface that manages or operates a display controller 232.
  • the first IC device 202 or second IC device 230 may control operations of a camera or video input device using a camera controller 234.
  • Other features supported by one or more of the IC devices 202 and 230 may include a keyboard, a voice-recognition component, and other input or output devices.
  • the display controller 232 may include circuits and software drivers that support displays such as a liquid crystal display (LCD) panel, touch-screen display, indicators and so on.
  • the storage media 208 and 238 may include transitory and/or non-transitory storage devices adapted to maintain instructions and data used by respective processors 206 and 236, and/or other components of the IC devices 202 and 230. Communication between each processor 206, 236 and its corresponding storage media 208 and 238 and other modules and circuits may be facilitated by one or more bus 212 and 242, respectively.
  • the reverse link 224 may be operated in the same manner as the forward link
  • a single bidirectional link 226 may support communications between the first IC device 202 and the second IC device 230.
  • the forward link 222 and/or reverse link 224 may be configurable to operate in a bidirectional mode when, for example, the forward and reverse links 222 and 224 share the same physical connections and operate in a half-duplex manner.
  • the communication link 220 may be operated to communicate control, command and other information between the first IC device 202 and the second IC device 230 in accordance with an industry or other standard.
  • forward and reverse links 222 and 224 may be configured or adapted to support a wide video graphics array (WVGA) 80 frames per second LCD driver IC without a frame buffer, delivering pixel data at 810 Mbps for display refresh.
  • WVGA wide video graphics array
  • forward and reverse links 222 and 224 may be configured or adapted to enable communications between with dynamic random access memory (DRAM), such as double data rate synchronous dynamic random access memory (SDRAM).
  • DRAM dynamic random access memory
  • SDRAM double data rate synchronous dynamic random access memory
  • Encoding devices 210 and/or 240 can encode multiple bits per clock transition, and multiple sets of wires can be used to transmit and receive data from the SDRAM, control signals, address signals, and so on.
  • the forward and reverse links 222 and 224 may comply or be compatible with application-specific industry standards.
  • the MIPI standard defines physical layer interfaces between an application processor IC device 202 and an IC device 230 that supports the camera or display in a mobile device.
  • the MIPI standard includes specifications that govern the operational characteristics of products that comply with MIPI specifications for mobile devices.
  • the MIPI standard may define interfaces that employ complimentary metal-oxide- semiconductor (CMOS) parallel busses.
  • CMOS complimentary metal-oxide- semiconductor
  • the communication link 220 of FIG. 2 may be implemented as a wired bus that includes a plurality of signal wires (denoted as N wires).
  • the N wires may be configured to carry data encoded in symbols, where clock information is embedded in a sequence of the symbols transmitted over the plurality of wires.
  • FIG. 3 illustrates an example of a clock and data recovery (CDR) circuit 300 that may be employed to recover embedded clock information in an N-wire system.
  • FIG. 4 is a timing diagram 400 illustrating certain signals generated through the operation of the CDR circuit 300.
  • the CDR circuit 300 and its timing diagram 400 are provided by way of generalized example, although other variants of the CDR circuit 300 and/or other CDR circuits may be used in some instances.
  • N-wires 308 Signals received from N-wires 308 are initially processed by a number ( VC2) of receivers 302, which produce a corresponding number of raw signals as outputs.
  • SI signal first state transition signal
  • Level latches 310, a comparator 304, set-reset latch 306, a one-shot circuit 326, an analog delay element 312 and (bused) level latches 310 may be configured to generate a level-latched signal (S signal) 322 representative of a delayed instance of the SI signal 320, where the delay before the SI signal 320 is captured by the level latches 310 to provide an updated S signal 322 may be selected by configuring a delay element (Delay S) 312.
  • S signal level-latched signal
  • Delay S delay element
  • the comparator 304 compares the SI signal 320 with the S signal
  • the set-reset latch 306 may receive the ⁇ signal 314 from the comparator 304 and output a signal (NEFLT signal) 316, which is a filtered version of the NE signal 314.
  • the operation of the set-reset latch 306 can be configured to remove any transient instability in the NE signal 314, where the transient instability is exhibited as spikes 410 in the NE signal 314.
  • the NEFLT signal 316 can be used to control the output latches 324 that capture the S signal 322 as output data signal 328.
  • the one-shot circuit 326 receives the NEFLT signal 316 and produces a fixed width pulse 412, which may then be delayed by the delay element 312 to produce a clock signal (SDRCLK) 318.
  • SDRCLK clock signal
  • the SDRCLK signal 318 may be used by external circuitry to sample the data output 328 of the CDR 300.
  • the SDRCLK signal 318 may be provided to decoder or deserializer circuits.
  • the level latches 310 receive the SI signal 320 and output the S signal 322, where the level latches 310 are triggered or otherwise controlled by the SDRCLK signal 318.
  • the comparator 304 compares the SI signal 320 with the S signal
  • the comparator 304 drives the NE signal 314 to a first state (e.g. logic low) when the SI signal 320 and the S signal 322 are equal, and to a second state (e.g. logic high) when the SI signal 320 and the S signal 322 are not equal.
  • the NE signal 314 is in the second state when the SI signal 320 and the S signal 322 are representative of different symbols.
  • the second state indicates that a transition is occurring.
  • the S signal 322 is essentially a delayed and filtered version of SI signal 320, in which transients or glitches 408 have been removed because of the delay 414 between the SI signal 320 and the S signal 322.
  • Multiple transitions 408 in the SI signal 320 may be reflected as spikes 410 in the NE signal 314, but these spikes 410 are masked from the NEFLT signal 316 through the operation of the set-reset circuit.
  • the SDRCLK 318 is resistant to line skew and glitches in the symbol transitions based on the use of the delays 326a, 312 provided in the feedback path to the level-latch 310 and set-reset latch 306, whereby the SDRCLK signal 318 controls the reset function of the set-reset latch 306.
  • the SI signal 320 begins to change state.
  • the state of the SI signal 320 may be different from Si 404 due to the possibility that intermediate or indeterminate states 408 during the transition between So 402 and Si 404.
  • These intermediate or indeterminate states 408 may be caused, for example, by inter-wire skew, over/under shoot, cross-talk, etc.
  • the NE signal 314 becomes high as soon as the comparator 304 detects a difference in values between the SI signal 320 and the S signal 322, and the transition high of the NE signal 314 asynchronously sets the set-reset latch 306 output, driving the NEFLT signal 316 high.
  • the NEFLT signal 316 is maintained in its high state until the set-reset latch 306 is reset by a high state of the SDRCLK signal 318.
  • the SDRCLK signal 318 is a delayed version of the NE1 SHOT signal 324, which is a limited pulse-width version of the NEFLT signal 316.
  • the SDRCLK signal 318 may be delayed with respect to the NE1SHOT signal 324 through the use of the analog delay circuit 312, for example.
  • the intermediate or indeterminate states 408 on SI 320 may represent invalid data. These intermediate or indeterminate states 408 may contain a short period of the previous symbol value So 402, and may cause the NE signal 314 to return low for short periods of time. Transitions of the SI signal 320 may generate spikes 410 on the NE signal 314. The spikes 410 are effectively filtered out and do not appear in the NEFLT signal 316.
  • the high state of the NEFLT signal 316 causes the SDRCLK signal 318 to transition high after a delay period 340 caused by the delay circuit 312.
  • the high state of SDRCLK signal 318 resets the set-reset latch 306 output, causing the NEFLT signal 316 to transition to a low state.
  • the high state of the SDRCLK signal 318 also enables the level latches 310, and the SI signal 320 value may be output on the S signal 322.
  • the comparator 304 detects that the S signal 322 (for symbol Si 402) matches the symbol Si 402 value present on the SI signal 320 and switches its output (the NE signal 314) low.
  • the low state of the NEFLT signal 316 causes the SDRCLK signal 318 to go low after a delay period 342 caused by the analog delay 312. This cycle repeats for each transition in the SI signal 320.
  • a new symbol S2 406 may be received and may cause the SI signal 320 to switch its value in accordance with the next symbol S2 406.
  • FIG. 5 is a diagram illustrating one example of a multi-lane interface 500 provided between two devices 502 and 532.
  • transcoders 506, 516 may be used to encode data 504, 514 and clock information in symbols to be transmitted over a set of N wires on each lane 512, 522, using N-factorial (N!) encoding for example.
  • the clock information is derived from respective transmit clocks 524, 526 and may be encoded in a sequence of symbols transmitted in N 2 differential signals over the N wires by ensuring that a signaling state transition occurs on at least one of the NQI signals between consecutive symbols.
  • N! N-factorial
  • each bit of a symbol is transmitted as a differential signal by one of a set of line drivers 510, 520, where the differential drivers in the set of line drivers 510, 520 are coupled to different pairs of the N wires.
  • the number of available combinations of wire pairs and signals may be calculated to be ⁇ 2, and the number of available combinations determines the number of signals that can be transmitted over the N wires.
  • the number of data bits 504, 514 that can be encoded in a symbol may be calculated based on the number of available signaling states available for each symbol transmission interval.
  • a termination impedance couples each of the N wires to a common center point in a termination network 528, 530. It will be appreciated that the signaling states of the N wires reflects a combination of the currents in the termination network 528, 530 attributed to the differential drivers 510, 520 coupled to each wire. It will be further appreciated that the center point of the termination network 528, 530 is a null point, whereby the currents in the termination network 528, 530 cancel each other at the center point.
  • each transcoder 506, 516 ensures that a transition occurs between each pair of symbols transmitted on the N wires by producing a sequence of symbols in which each symbol is different from its immediate predecessor symbol.
  • the transcoder 506, 516 may employ a mapping scheme to generate raw symbols for transmission on the N wires available on a lane 512, 522.
  • the transcoder 506, 516 and serializer 508, 518 cooperate to produce raw symbols for transmission based on the input data bits 504, 514.
  • a transcoder 540, 550 may employ a mapping to determine a transition number that characterizes a difference between a pair of consecutive raw symbols, symbols in a lookup table, for example.
  • the transcoders 506, 516, 540, 550 operate on the basis that every consecutive pair of raw symbols includes two different symbols.
  • the transcoder 506, 516 at the transmitter 502 may select between the N ⁇ — 1 states that are available at every symbol transition.
  • the bit rate may be calculated as ⁇ og2(available states) per cycle of the transmit clock 524, 526.
  • DDR double data rate
  • symbol transitions occur at both the rising edge and falling edge of the transmit clock 524, 526.
  • a receiving device 532 receives the sequence of symbols using a set of line receivers 534, 544, where each receiver in the set of line receivers 534, 544 determines differences in signaling states on one pair of the N wires. Accordingly, NC2 receivers are used in each lane 512, 522, where N represents the number of wires in the corresponding lane 512, 522. The ⁇ 2 receivers 534, 544 produce a corresponding number of raw symbols as outputs.
  • the CDRs 536 and 546 may operate in generally the same manner as the CDR 300 of FIG. 3 and each CDR 536 and 546 may produce a receive clock signal 554, 556 that can be used by a corresponding deserializer 538, 548.
  • the clock signal 554 may include a DDR clock signal that can be used by external circuitry to receive data provided by the transcoders 540, 550.
  • Each transcoder 540, 550 decodes a block of received symbols from the corresponding deserializer 538, 548 by comparing each next symbol to its immediate predecessor.
  • the transcoders 540, 550 produce output data 542 and 552 that corresponds to the data 504, 514 provided to the transmitter 502.
  • each lane 512, 522 may be operated independently, although in a typical application the data 504 transmitted over one lane 512 may be synchronized with the data 514 transmitted over another lane 522.
  • data bits 504 for transmission over a first lane (in this example, Lane X) 512 are received by a first transcoder 506 which generates a set of raw symbols that, when transmitted in a predetermined sequence, ensure that a transition of signaling state occurs in at least one signal transmitted on the 4 wires of the first lane 512.
  • a serializer 508 produces a sequence of symbol values provided to line drivers 510 that determine the signaling state of the 4 wires of the first lane 512 for each symbol interval.
  • data bits 514 are received by a second transcoder 516 of a second lane (in this example, Lane Y) 522.
  • the second transcoder 516 generates a set of transition numbers that are serialized by a serializer 518 that converts the set of transition numbers to a sequence of symbol values provided to line drivers 520 that determine the signaling state of the 4 wires of the second lane 522 for each symbol interval.
  • the sequence of the raw symbols ensure that a transition of signaling state occurs in at least one signal transmitted on the 4 wires of the second lane 522 between each pair of consecutive symbols.
  • FIG. 6 illustrates a first example of a multi-lane interface 600 provided according to certain aspects disclosed herein.
  • the multi-lane interface 600 offers improved data throughput and reduced circuit complexity when clock information encoded in symbols transmitted on a first lane (here Lane X) 612 is used to receive symbols transmitted without encoded clock information on one or more other lanes, including Lane Y 622.
  • Lane X first lane
  • Lane Y Lane Y
  • each lane 612, 622 includes 4 wires.
  • Data for transmission may be divided into two portions 604 and 614, where each portion is transmitted on a different lane 612, 622.
  • data 604 and information related to the transmit clock 624 may be encoded using the transcoder/serializer 608 to obtain raw symbols that are serialized as described in relation to FIG. 5.
  • the output of receivers 634 associated with the first lane 612 is provided to a CDR 636.
  • the CDR 636 may be configured to detect transitions in signaling state in order to generate a receive clock 654 used by both deserializing and transcoding circuits 638 and 648 for both lanes 612, 622.
  • First deserializing and transcoding circuits 638 extract data 642 from the raw symbols received from the first lane 612
  • second deserializing and transcoding circuits 648 extract data 652 from the raw symbols received from the second lane 622.
  • transmission data 614 may be provided to transcoding and serializing circuits 618 and transmitted on the second lane 622 without encoded clock information.
  • the transcoding circuitry used to produce raw symbols for the second lane 622 may be significantly less complex than the transcoding circuitry used to produce raw symbols with embedded clock information for transmission on the first lane 612.
  • transcoding circuits for the second lane 622 may not need to perform certain arithmetic operations and logic functions to guarantee state transition at every symbol boundary.
  • a DDR clocked 4-wire first lane 612 provides
  • an interface may have two 3-wire lanes where clock information is encoded in the first lane, but not in the second lane.
  • FIG. 7 illustrates another example of a multi-lane interface 700 provided in accordance with one or more aspects disclosed herein.
  • the multi-lane interface 700 offers improved flexibility of design in addition to optimized data throughput and reduced circuit complexity.
  • clock information encoded in the symbols transmitted on one lane (here Lane X) 712 may be used to receive symbols transmitted on one or more other lanes 722 that have different numbers of wires.
  • data for transmission may be divided into a plurality of portions 704 and 714, where each portion is to be transmitted on a different lane 712, 722.
  • data 704 and a transmit clock 724 may be converted by transcoding and serializing circuits 708 to obtain a sequence of raw symbols as described in relation to FIGs. 5 and 6.
  • the received data 714 may be provided to transcoding and serializing circuits 718 and then transmitted without embedded clock information.
  • the output of receivers 734 associated with the first lane 712 is provided to a CDR 736.
  • the CDR 736 may be configured to detect a transition in signaling state of the 3 wires in the first lane 712, and to generate a receive clock 754 used by both deserializing and transcoding circuits 738 and 748 for both lanes 712, 722.
  • First deserializing and transcoding circuits 738 extract data 742 from the raw symbols received from the first lane 712, while second deserializing and transcoding circuits 748 extract data 752 from the raw symbols received from the second lane 722.
  • the first lane 712 includes 3 wires configured for 3 !
  • a single lane 712 encodes clock information and variable numbers of wires may be assigned to other lanes 722.
  • a conventional 3 ! system may configure three 3-wire lanes, with clock information encoded on each lane.
  • Each of the three lanes provides 5 signaling states per symbol for a total of 15 states per symbol.
  • a system provided according to certain aspects described herein may use the 10 interconnects to provide two 3 ! lanes and one 4! lane, where the clock information is encoded in a first 3! lane.
  • FIG. 8 illustrates another example of a multi-lane interface 800 provided in accordance with one or more aspects disclosed herein.
  • the multi-lane interface 800 offers various benefits including improved decoding reliability, which may permit higher transmission rates.
  • the configuration and operation of the multi-lane interface 800 in this example is similar to that of the multi-lane interface 600 of FIG. 6, except that the CDR 836 is configured to generate a receive clock 854 from transitions detected on either the first lane 812 or the second lane 822. Accordingly, the CDR 836 receives the outputs of the receivers 834 and 844. Variations in the delay between the symbol boundary and an edge of the receive clock 854 may be reduced because the CDR 836 generates a clock from the first detected transition on either lane 812, or 822. This approach can reduce the effect of variable transition times on the wires and/or variable switching times of the line drivers 810, 820 or receivers 834, 844.
  • data for transmission may be received in two or more portions 804 and 814, where the portions 804, 814 are for transmission on different lanes 812, 822.
  • a combination of a transcoder and serializer circuits 808 may encode data bits X 804 and embed information related to a transmit clock 824 in a sequence of symbols to be transmitted on the first lane 812, as described in relation to FIG. 5.
  • the outputs of both sets of receivers 834 and 844 are provided to the CDR 836, which is configured to detect a transition in signaling state on either lane 812, 822 and generate a receive clock 854 based on the transition.
  • the receive clock 854 is used by both deserializing/transcoding circuits 838 and 848, which produce respective first and second lane data outputs 842 and 852.
  • FIG. 9 illustrates another example of a multi-lane interface 900 provided according to one or more aspects disclosed herein.
  • the multi-lane interface 900 offers improved data throughput and encoding efficiency by ensuring that a transition in signaling state between consecutive symbol intervals occurs on any one of a plurality of lanes 912, 922. Accordingly, the percentage overhead associated with encoding the clock information can be reduced relative to a system in which the clock information is embedded in sequences of symbols transmitted on a single lane.
  • a first lane (here Lane X) 912 includes three wires that carry 3 ! encoded signals
  • the second lane (here Lane Y) 922 includes four wires and is configured for 4! encoding.
  • a transcoder 906 may be adapted to combine data 904 and clock information in symbols to be transmitted over two or more lanes 912 and/or 922.
  • Encoding efficiencies may be achieved by embedding clock information based on the combination of available signaling states for all lanes 912, 922.
  • the clock information is embedded by ensuring that a transition in signaling state occurs on at least one lane 912, 922 between consecutive symbol intervals.
  • the transcoder 906 may be configured to produce different sets of symbols for each lane 912, 922.
  • the data 904 received by a transmitter 902 according to a clock signal 924 may be transmitted as a first sequence of symbols encoded in three signals transmitted on the 3 ! first lane 912, and a second sequence of symbols encoded in six signals concurrently transmitted on the 4! second lane 922.
  • the transcoder 906 embeds clock information by ensuring that a signaling state transition occurs on at least one of the lanes 912 and 922 between consecutive symbols.
  • the total number of states per symbol interval is the product of the number of states per symbol transmitted on the first lane 912 and the number of states per symbol transmitted on the second lane 922. Accordingly, the number of states available to the transcoder at each symbol interval, when clock information is embedded across both lanes 912, 922 may be calculated as:
  • the number of states available to the transcoder at each symbol interval, when clock information is embedded across two lanes that are encoded in three signals using 3! may be calculated as:
  • Table 1 and Table 2 illustrate increased coding efficiencies when clock information is embedded by a transcoder across two or more N! lanes.
  • Table 1 relates to the multi-lane interface 900 of FIG. 9. As can be seen from the table, a maximum encoding efficiency is obtained when a transcoder 906 embeds the clock information by considering the sequences of symbols transmitted on both lanes 912, 922.
  • Table 2 relates to an example of a multi-lane interface that has two 3! lanes.
  • the receiver 932 includes a CDR 936 that generates a receive clock 954 by detecting transitions on both lanes 912, 922.
  • the deserializers 938, 948 provide symbols received from respective lanes 912, 922 to a transcoder 940 that reverses the transcoding performed by the transcoder 906 in the transmitter.
  • the transcoder 940 in the receiver 932 operates by examining the combined sequences of received symbols to produce output data 942, which corresponds to the data 904 received at the transmitter 902.
  • Sets of line drivers 910, 920 and receivers 934, 944 may be provided according to the number of wires in the N! lanes 912, 922.
  • the multi-lane interface 900 can be configured to provide additional advantages over conventional interfaces.
  • FIG. 10 illustrates an example in which a transcoder 1024 can be used to control the order of delivery of data to a receiver.
  • One multi- lane interface 1000 such as the multi-lane interface 500 in FIG. 5 may independently encode two or more sets of data bits 1002, 1004 in sequences of symbols 1006, 1008 for transmission over a corresponding number of lanes. Data may be provided to the multi-lane interface 1000 pre-divided into the sets of data bits 1002, 1004, and/or the sets of data bits 1002, 1004 may be split by the multi-lane interface 1000. Data bits may be allocated among the two or more sets of data bits 1002, 1004 arbitrarily, according to function, design preference or for convenience and/or other reasons.
  • each word, byte or other data element received in a first clock cycle may be encoded into two or more symbols transmitted sequentially in a pair of symbol intervals 1012a-1012g on one of the two lanes.
  • the receiver can decode the data element when the two or more symbols are received from the pair of symbol intervals 1012a-1012g.
  • a multi-lane interface 1020 may include a transcoder 1024 that encodes data 1022 and clock information into a plurality of sequences of symbols 1026, 1028 concurrently transmitted over two or more lanes.
  • the transcoder 1024 may control the order of delivery of data to a receiver by concurrently transmitting symbols for transmission on two lanes.
  • data bits 1022 received in a first clock cycle (Bits(0)) may be transcoded into two symbols and transmitted in parallel on two lanes during a first symbol interval 1030.
  • Data bits 1022 received in a second clock cycle (Bits(l)) may be transmitted as two symbols in parallel on the two lanes during a second symbol interval 1032.
  • FIG. 11 illustrates another example of a multi-lane interface 1100 provided in accordance with one or more aspects disclosed herein.
  • the multi- lane interface 1100 includes at least one N! encoded lane 1112 and a serial data link 1122.
  • the serial data link 1122 may be a single ended serial link (as illustrated) or a differentially encoded serial data link.
  • the serial data link 1122 may include a serial bus, such as an Inter-Integrated Circuit (I2C) bus, a camera control interface (CCI) serial bus or derivatives of these serial bus technologies.
  • I2C Inter-Integrated Circuit
  • CCI camera control interface
  • a clock signal 1124 is used by the serializer 1108 of the N! link and the serializer 1118 of the serial link 1122, and the clock signal 1124 need not be transmitted to the receiver 1132 over a separate clock signal lane. Instead, a transcoder 1106 embeds clock information in a sequence of symbols that is provided through the serializer to the differential line drivers of the N! lane 1112.
  • a CDR 1136 At the receiver 1132, a CDR 1136 generates a receiver clock signal 1154 from transitions detected at the outputs of receivers 1134.
  • the receiver clock signal 1154 is used by the N! lane deserializer 1138 and the serial link deserializer 1148.
  • the CDR 1136 may monitor the output of the line receivers 1144 associated with the serial link 1122 in order to improve detection of a transition between symbol intervals.
  • the N! lane deserializer 1138 provides deserialized symbol information to the transcoder 1140, which produces output data 1142 representative of the input data 1104 that is transmitted over the N! encoded lane 1112.
  • a transmitter 1102 transmits symbols in three signals on a 3! encoded first lane 1112.
  • the symbols include embedded clock information and 5 signaling states per symbol are available on the first lane 1112.
  • the transmitter may also send data on a second lane using 4 serial signals transmitted on the wires of a serial link 1122.
  • a conventional or traditional four-wire serial link 1 122 may dedicate one of the four wires for carrying a clock signal, and data transmission may be limited to three signals on the other three of the 4 wires.
  • FIG. 12 is a flowchart 1200 illustrating a method for data communications on an N-wire communications link.
  • the communications link may include a plurality of connectors that carry symbols encoded using a suitable encoding scheme, such as N! encoding, multiphase encoding, multi-wire differential encoding, etc.
  • the connectors may include electrically conductive wires, optical signal conductors, semi-conductive interconnects and so on.
  • the method may be performed by one or more processors of a receiving device.
  • a first sequence of symbols is received from a first lane of a multi- lane interface.
  • Each symbol in the sequence of symbols may correspond to a signaling state of N wires of the first lane.
  • a clock signal is recovered or extracted from the multi-lane interface.
  • the clock signal may include edges corresponding to a plurality of transitions in the signaling state of the N wires between pairs of consecutive symbols in the first sequence of symbols.
  • the first sequence of symbols is converted to a first set of data bits using the clock signal.
  • the first sequence of symbols may be converted to the first set of data bits by using a transcoder to convert the first sequence of symbols to a set of transition numbers, and converting the set of transition numbers to obtain the first set of data bits.
  • a second set of data bits is derived from one or more signals received from a second lane of the multi-lane interface using the clock signal.
  • the second set of data bits may be derived without using a transcoder.
  • the first sequence of symbols may be encoded in AiC 2 differential signals received from NC 2 different pairs of the N wires.
  • the second lane may include M wires, wherein a second sequence of symbols is encoded in MC 2 differential signals received from MC 2 different pairs of the M wires.
  • M and N may have equal or have different values.
  • deriving the second set of data bits includes receiving serial signals from each of M wires of a serial interface, and extracting the second set of data bits by sampling the serial signals in accordance with the clock signal.
  • Deriving the second set of data bits may includes receiving Mil differential signals from M wires of a serial interface, and extracting the second set of data bits by sampling the Mil differential signals in accordance with the clock signal.
  • the clock signal may be recovered or extracted by providing a transition in the clock signal corresponding to a transition detected in the signaling state of the N wires or in the signaling state of one or more wires of the second lane.
  • the clock signal may include edges corresponding to one or more transitions in the signaling state of at least one wire of the second lane of the multi-lane interface.
  • the first sequence of symbols is encoded in NC 2 differential signals.
  • Each of the NC 2 differential signals may be received from a different pair of the N wires.
  • a second sequence of symbols may be encoded in M 2 differential signals received from M wires of the second lane.
  • Each of the MC 2 differential signals may be received from a different pair of the M wires.
  • the first sequence of symbols may be converted to the first set of data bits using a transcoder circuit.
  • the second sequence of symbols may be converted to the second set of data bits using the same transcoder circuit.
  • a transition in the signaling state of one or more of the N wires and the M wires occurs between each sequential pair of symbols in the first sequence of symbols.
  • Each of the first sequence of symbols may be transmitted in a different symbol interval.
  • the first set of data bits and the second set of data bits received in each symbol interval may be combined to obtain a completed data element from the each symbol interval.
  • FIG. 13 is a diagram illustrating a simplified example of a hardware implementation for an apparatus 1300 employing a processing circuit 1302.
  • the processing circuit typically has a processor 1316 that may include one or more of a microprocessor, microcontroller, digital signal processor, a sequencer and a state machine.
  • the processing circuit 1302 may be implemented with a bus architecture, represented generally by the bus 1320.
  • the bus 1320 may include any number of interconnecting buses and bridges depending on the specific application of the processing circuit 1302 and the overall design constraints.
  • the bus 1320 links together various circuits including one or more processors and/or hardware modules, represented by the processor 1316, the modules and/or circuits 1304, 1306 and 1308, line interface circuits 1312 configurable to communicate over connectors or wires (multi-lane interface) 1314 and the processor-readable/computer-readable storage medium 1318.
  • the bus 1320 may also link various other circuits such as timing sources, peripherals, voltage regulators, and power management circuits, which are well known in the art, and therefore, will not be described any further.
  • the processor 1316 is responsible for general processing, including the execution of software stored on the computer-readable storage medium 1318.
  • the software when executed by the processor 1316, causes the processing circuit 1302 to perform the various functions described supra for any particular apparatus.
  • the computer-readable storage medium 1318 may also be used for storing data that is manipulated by the processor 1316 when executing software, including data decoded from symbols transmitted over the connectors 1314.
  • the processing circuit 1302 further includes at least one of the modules and/or circuits 1304, 1306 and 1308.
  • the modules and/or circuits 1304, 1306 and 1308 may be software modules running in the processor 1316, resident/stored in the computer-readable storage medium 1318, one or more hardware modules coupled to the processor 1316, or some combination thereof.
  • the modules and/or circuits 1304, 1306 and/or 1308 may include microcontroller instructions, state machine configuration parameters, or some combination thereof.
  • the apparatus 1300 for wireless communication includes modules and/or circuits 1306, 1312 configured to receive a first sequence of symbols from a first lane of a multi-lane interface 1314, a module and/or circuit 1306 configured to recover a clock signal from the multi-lane interface 1314, where the clock signal includes edges corresponding to a plurality of transitions in the signaling state of the N wires occurs between pairs of consecutive symbols in the first sequence of symbols, modules and/or circuits 1304 and/or 1308 configured to convert the first sequence of symbols to a first set of data bits using the clock signal, and modules and/or circuits 1304 and/or 1308 configured to derive a second set of data bits from one or more signals received from a second lane of the multi-lane interface 1314 using the clock signal.
  • the circuits illustrated in FIGs. 6-9 and 1 1 provides logic which implement the various functions performed by the processing circuit 1302.
  • the computer-readable storage medium 1318 has one or more instructions stored or maintained thereon.
  • the instructions may cause the processing circuit 1302 to receive a first sequence of symbols from a first lane of a multi-lane interface 1314, recover a clock signal from the multi-lane interface 1314, wherein the clock signal includes edges corresponding to a plurality of transitions in the signaling state of the N wires between pairs of consecutive symbols in the first sequence of symbols, convert the first sequence of symbols to a first set of data bits using the clock signal, and derive a second set of data bits from one or more signals received from a second lane of the multi-lane interface 1314 using the clock signal.
  • Each symbol in the sequence of symbols may correspond to a signaling state of the N wires.
  • the aforementioned means may be implemented, for example, using some combination of a processor 206 or 236, physical layer drivers 210 or 240 and storage media 208 and 238.
  • FIG. 14 is a flowchart 1400 illustrating a method for data communications on an
  • the communications link may include a plurality of connectors that carry symbols encoded using a suitable encoding scheme, such as N! encoding, multiphase encoding, multi-wire differential encoding, etc.
  • the connectors may include electrically conductive wires, optical signal conductors, semi-conductive interconnects and so on. The method may be performed by one or more processors of a receiving device.
  • clock information is embedded in a first sequence of symbols that encodes first data bits.
  • Each of the first sequence of symbols may correspond to a signaling state of N wires of a first lane of a multi-lane interface.
  • the clock information may be encoded by using a transcoder to convert the first data bits to a set of transition numbers, and convert the set of transition numbers to obtain the first sequence of symbols.
  • the second data bits may be encoded in the second sequence of symbols without using a transcoder.
  • the first sequence of symbols is transmitted on the first lane.
  • a second sequence of symbols is transmitted on a second lane of the multi-lane interface.
  • the second sequence of symbols may be encoded with second data bits and without embedded clock information.
  • the first sequence of symbols may be transmitted by transmitting the first sequence of symbols in N 2 differential signals on N 2 different pairs of the N wires.
  • the second lane may include M wires.
  • the second sequence of symbols may be transmitted in M 2 differential signals on MC 2 different pairs of the M wires.
  • the values of M and N may be equal or different.
  • the second sequence of symbols may be transmitted on M wires of a serial bus. Transmitting the second sequence of symbols may include transmitting the second set of data in Mil differential signals.
  • each of the first sequence of symbols is transmitted in a different symbol interval.
  • Embedding the clock information may include causing a transition in the signaling state of the N wires or in the signaling state of one or more wires of the second lane between each pair of consecutive symbols in the first sequence of symbols.
  • a single transcoder circuit may be used to encode the first data bits in the first sequence of symbols and to encode the second data bits in the second sequence of symbols.
  • embedding the clock information includes causing a transition in the signaling state of the N wires between each pair of consecutive symbols in the first sequence of symbols or in the signaling state of M wires of the second lane between each pair of consecutive symbols in the second sequence of symbols.
  • the clock information may relate to a transmit clock used to encode both the first sequence of symbols and the second sequence of symbols.
  • FIG. 15 is a diagram illustrating a simplified example of a hardware implementation for an apparatus 1500 employing a processing circuit 1502.
  • the processing circuit typically has a processor 1516 that may include one or more of a microprocessor, microcontroller, digital signal processor, a sequencer and a state machine.
  • the processing circuit 1502 may be implemented with a bus architecture, represented generally by the bus 1520.
  • the bus 1520 may include any number of interconnecting buses and bridges depending on the specific application of the processing circuit 1502 and the overall design constraints.
  • the bus 1520 links together various circuits including one or more processors and/or hardware modules, represented by the processor 1516, the modules and/or circuits 1504, 1506 and 1508, line interface circuits 1512 configurable to communicate over connectors or wires 1514 and the processor-readable/computer-readable storage medium 1518.
  • the bus 1520 may also link various other circuits such as timing sources, peripherals, voltage regulators, and power management circuits, which are well known in the art, and therefore, will not be described any further.
  • the processor 1516 is responsible for general processing, including the execution of software stored on the computer-readable storage medium 1518.
  • the software when executed by the processor 1516, causes the processing circuit 1502 to perform the various functions described supra for any particular apparatus.
  • the computer-readable storage medium 1518 may also be used for storing data that is manipulated by the processor 1516 when executing software, including data decoded from symbols transmitted over the connectors 1514.
  • the processing circuit 1502 further includes at least one of the modules and/or circuits 1504, 1506 and 1508.
  • the modules and/or circuits 1504, 1506 and 1508 may be software modules running in the processor 1516, resident/stored in the computer-readable storage medium 1518, one or more hardware modules coupled to the processor 1516, or some combination thereof.
  • the modules and/or circuits 1504, 1506 and/or 1508 may include microcontroller instructions, state machine configuration parameters, or some combination thereof.
  • the apparatus 1500 for wireless communication includes a module and/or circuit 1504 configured to embed information with first data bits encoded in a first sequence of symbols, modules and/or circuits 1506, 1512 configured to transmit the first sequence of symbols on a first lane of a multi-lane interface the first lane, modules and/or circuits 1504, 1506 and/or 1508 configured to transmit a second sequence of symbols on a second lane of the multi-lane interface.
  • the circuits illustrated in FIGs. 6-9 and 1 1 provides logic which implement the various functions performed by the processing circuit 1502.
  • a processor-readable/computer-readable storage medium 1518 has one or more instructions stored or maintained thereon.
  • the instructions may cause the processor 1516 to embed clock information with first data bits encoded in a first sequence of symbols, transmit the first sequence of symbols on a first lane of the multi-lane interface 1514, and transmit a second sequence of symbols on a second lane of the multi-lane interface 1514.
  • Each of the first sequence of symbols may correspond to a signaling state of N wires of a first lane of a multi-lane interface 1514.
  • the second sequence of symbols may be encoded with second data bits and without embedded clock information.
  • the aforementioned means may be implemented, for example, using some combination of a processor 206 or 236, physical layer drivers 210 or 240 and storage media 208 and 238.
  • multi-wire symbol transition clocking may be implemented by embedding a clock into symbol transitions.
  • an embedded clock requires clock and data recovery (CDR) logic/circuitry at a receiving device to recover the embedded clock from the symbol transitions.
  • CDR logic/circuitry may be complex or expensive to implement by some receiving devices.
  • Embedded clocks may also suffer from symbol slip errors due to excess jitters, inter lane skews, signal spikes, and other causes.
  • an N! multi-wire bus/link may be used to facilitate the transmission of symbols in which an embedded clock is encoded/embedded in guaranteed symbol transitions while a dedicated clock line is used to transmit a dedicated clock.
  • the bus/link may be a single- ended multi-wire bus/link.
  • the dedicated clock transmitted via the dedicated clock line facilitates a receiver to decode the symbols transmitted over the multi-wire bus/link without using CDR logic/circuitry and without having to rely on the embedded clock.
  • use of the dedicated clock line for receiving the dedicated clock allows the receiver to forgo implementing the CDR logic/circuitry, and consequently, minimize the complexity and cost associated with such implementation, as well as reduce symbol slip errors related to an embedded clock.
  • a separate clock does not need to be encoded/embedded in symbol transitions of a sequence of symbols to be transmitted. Accordingly, it is not mandatory upon the system to guarantee a transition between each symbol in the sequence of symbols, and therefore, the system is able to interleave symbols of different types on a data lane and across multiple data lanes.
  • circuitry/modules for converting raw symbols into symbols with guaranteed transitions may be omitted at a transmitter and circuitry/modules for converting symbols with guaranteed transitions into raw symbols may be omitted at a receiver, thus minimizing the complexity and cost associated with implementing such circuitry/ modules .
  • the clock signal in a system using the dedicated clock line to transmit/receive a clock signal, is separately transmitted from a data signal, and therefore, the direction of the data signal transmission is not constrained by the direction of the clock signal transmission.
  • a clock signal to be transmitted over the dedicated clock line from a first device to a second device while data/symbols associated with the clock signal are transmitted from the second device to the first device.
  • the dedicated clock line for bi-directional transmissions.
  • both the first device and the second device may utilize the multi-wire bus/link for transmissions by interleaving the lines of the multi-wire bus/link and/or alternately transmitting a dedicated clock over the dedicated clock line.
  • FIG. 16 is a diagram illustrating a further example of a multi-lane interface 1600 provided between two devices 1602 and 1632.
  • a transcoder 1606 may be used to encode data 1604 and clock information in symbols to be transmitted over a set of N wires on a lane (or "multi-wire link") 1612 using N- factorial (N! ) encoding for example, where N is an integer greater than 2.
  • the clock information may be derived from a first transmit clock (e.g., DDRCLK X) 1624 or a second transmit clock (e.g., DDRCLK Y) 1626, and may be encoded in a sequence of symbols transmitted in N 2 differential signals over the N wires by ensuring that a signaling state transition occurs on at least one of the N 2 signals between consecutive symbols.
  • a first transmit clock e.g., DDRCLK X
  • DDRCLK Y second transmit clock
  • the number of available combinations of wire pairs and signals may be calculated to be N 2 , and the number of available combinations determines the number of signals that can be transmitted over the N wires.
  • the number of data bits 1604 that can be encoded in a symbol may be calculated based on the number of available signaling states available for each symbol transmission interval.
  • a termination impedance couples each of the N wires to a common center point in a termination network 1628. It will be appreciated that the signaling states of the N wires reflects a combination of the currents in the termination network 1628 attributed to the differential drivers 1610 coupled to each wire. It will be further appreciated that the center point of the termination network 1628 is a null point, whereby the currents in the termination network 1628 cancel each other at the center point.
  • At least one of the NC 2 signals in the link transitions between consecutive symbols.
  • the transcoder 1606 ensures that a transition occurs between each pair of symbols transmitted on the N wires by producing a sequence of symbols in which each symbol is different from its immediate predecessor symbol.
  • the transcoder 1606 may employ a mapping scheme to generate raw symbols for transmission on the N wires available on the lane 1612.
  • the transcoder 1606 and serializer 1608 cooperate to produce raw symbols for transmission based on the input data bits 1604.
  • a transcoder 1640 may employ a mapping to determine a transition number that characterizes a difference between a pair of consecutive raw symbols, symbols in a lookup table, for example.
  • the transcoders 1606, 1640 operate on the basis that every consecutive pair of raw symbols includes two different symbols.
  • the transcoder 1606 at the transmitter 1602 may select between the N ⁇ — 1 states that are available at every symbol transition.
  • the bit rate may be calculated as ⁇ og2(available states) per cycle of the first transmit clock 1624 or the second transmit clock 1626.
  • DDR double data rate
  • the second transmit clock 1626 used to encode the data 1604 may be transmitted to a receiver 1632 using a line driver 1620.
  • the line driver 1620 may generate a clock signal based on the second transmit clock 1626 and transmit the clock signal over a dedicated clock line 1622.
  • the dedicated clock line 1622 is separate from and in parallel with the lane/multi-wire link 1612, and may be limited to communicating clock signals between the transmitter 1602 and the receiver 1632.
  • the receiver 1632 receives the sequence of symbols using a set of line receivers 1634, where each receiver in the set of line receivers 1634 determines differences in signaling states on one pair of the N wires. Accordingly, NC 2 receivers are used in the lane 1612, where N represents the number of wires in the lane 1612. The N 2 receivers 1634 produce a corresponding number of raw symbols as outputs.
  • the receiver 1632 receives the clock signal transmitted over the dedicated clock line 1622 using a line receiver 1644.
  • the line receiver 1644 Upon receipt of the clock signal over the dedicated clock line 1622, the line receiver 1644 generates a receive clock (e.g., DDRCLK Y) 1656 that corresponds to the second transmit clock 1626.
  • a receive clock e.g., DDRCLK Y
  • the deserializer 1638 deserializes symbols based on the state transition signal from the set of line receivers 1634 and the receive clock 1656 (corresponding to the second transmit clock 1626).
  • the receive clock 1656 may be used by external circuitry to receive data provided by a transcoder 1640.
  • the transcoder 1640 decodes a block of received symbols from the deserializer 1638 by comparing each next symbol to its immediate predecessor.
  • the transcoder 1640 produces output data 1642 that corresponds to the data 1604 provided to the transmitter 1602. Accordingly, because the receiver 1632 may utilize the second transmit clock 1626 provided via the dedicated clock line 1622 to decode received symbols corresponding to the data 1604, the receiver 1632 does not require CDR logic/circuitry to recover the first transmit clock 1624 that may be embedded in transitions between the received symbols. Hence, the receiver 1632 may ignore the first transmit clock 1624.
  • the lane (or "multi-wire link") 1612 may be operated according to the following examples.
  • data bits 1604 for transmission over the lane (in this example, Lane X) 1612 are received by the transcoder 1606 which generates a set of raw symbols that, when transmitted in a predetermined sequence, ensure that a transition of signaling state occurs in at least one signal transmitted on the 4 wires of the lane 1612.
  • the serializer 1608 produces a sequence of symbol values provided to the line drivers 1610 that determine the signaling state of the 4 wires of the lane 1612 for each symbol interval.
  • data bits 1604 are received by the transcoder 1606 of the lane (in this example, Lane X) 1612.
  • the transcoder 1606 generates a set of transition numbers that are serialized by the serializer 1608 that converts the set of transition numbers to a sequence of symbol values provided to the line drivers 1610 that determine the signaling state of the 4 wires of the lane 1612 for each symbol interval.
  • the sequence of the raw symbols ensure that a transition of signaling state occurs in at least one signal transmitted on the 4 wires of the lane 1612 between each pair of consecutive symbols.
  • At least one line/wire of the lane (or "multi-wire link") 1612 is bidirectional. Accordingly, the transmitter 1602 may be configured to receive a sequence of symbols transmitted from the receiver 1632 over the at least one bidirectional line/wire of the lane 1612.
  • the dedicated clock line 1622 is bi-directional and can be driven by either of the transmitter 1602 or the receiver 1632 transmitting over the lane 1612.
  • the transmitter 1602 may be configured to receive a dedicated clock signal from the receiver 1632 over the dedicated clock line 1622.
  • the dedicated clock signal may be associated with a transmit clock used to encode the sequence of symbols transmitted by the receiver over the at least one bi-directional line/wire of the lane 1612.
  • FIG. 17 illustrates examples of transmitting symbols on multiple data lanes using a dedicated clock line.
  • symbols of a first type 1710 are transmitted on a first data lane (Data Lane 1) 1704
  • symbols of a second type 1712 are transmitted on a second data lane (Data Lane 2) 1706
  • symbols of a third type 1714 are transmitted on a third data lane (Data Lane 3) 1708.
  • the symbols of the first type 1710, the second type 1712, and the third type 1714 may all be transmitted on their respective data lanes according to a clock signal separately transmitted on a dedicated clock line 1702.
  • a separate clock does not need to be encoded/embedded in symbol transitions of a sequence of symbols to be transmitted.
  • a transmitter does not have to guarantee a transition of signaling state between each symbol in the sequence of symbols.
  • the transmitter is able to interleave symbols of different types on a data lane and across multiple data lanes. For example, a symbol of a first type 1760, a symbol of a second type 1762, and a symbol of third type 1764 may be interleaved and transmitted on a first data lane (Data Lane 1) 1754.
  • a symbol of the second type 1762, a symbol of the third type 1764, and a symbol of the first type 1760 may be interleaved and transmitted on a second data lane (Data Lane 2) 1756.
  • a symbol of the third type 1764, a symbol of the first type 1760, and a symbol of the second type 1762 may be interleaved and transmitted on a third data lane (Data Lane 3) 1758.
  • the symbol of the second type 1762 and the symbol of the third type 1764 can be transmitted on a data lane (e.g., the first data lane 1754) without a transition of signaling state between the symbols (see 1766).
  • the symbol of the first type 1760 and the symbol of the second type 1762 can be transmitted on a data lane (e.g., the second data lane 1756) without a transition of signaling state between the symbols (see 1768).
  • the symbol of the second type 1762, the symbol of the third type 1764, and the symbol of the first type 1760 can be transmitted on a data lane (e.g., the third data lane 1758) without a transition of signaling state between any pair of symbols (see 1770 and 1772).
  • the symbols of the first type 1760, the second type 1762, and the third type 1764 may all be transmitted on each of the data lanes according to a clock signal separately transmitted on a dedicated clock line 1752.
  • FIG. 18 illustrates examples of multi-wire transcoding using a dedicated clock line.
  • a bits-to-transition symbol converter Bits to T 1802.
  • the Bits to T 1802 Based on the data bits, the Bits to T 1802 generates a set of raw transition symbols 1804 for transmission over a multi-wire link 1820.
  • the set of raw transition symbols 1804 are fed into a transition symbol-to-symbol converter (T to S) 1806.
  • T to S 1806 selects raw transition symbols for transmission such that a transition of signaling state is guaranteed between each symbol, thus allowing for clock information to be encoded/embedded in the symbol transitions.
  • the symbols output by the T to S 1806 may be serialized by serializer (SER) 1808 based on a clock signal that is transmitted on a dedicated clock line 1812.
  • the SER 1808 produces a sequence of symbols that determine the signaling state of wires of the multi-wire link 1820.
  • the sequence of symbols 1814 are provided to line drivers 1810 for transmission on the multi-wire link 1820.
  • a deserializer (DES) 1824 receives the sequence of symbols 1814 via line receivers 1822.
  • the DES 1824 deserializes the received symbols based on the clock signal received on the dedicated clock line 1812.
  • the output of the DES 1824 is fed into a symbol-to- transition symbol converter (S to T) 1826.
  • S to T 1826 recovers the raw transition symbols 1804 based on the transitions present between each deserialized symbol.
  • a transition symbol -to-bits converter (T to Bits) 1828 then converts the recovered raw transition symbols into data bits (Bits).
  • a separate clock does not need to be encoded/embedded in symbol transitions of a sequence of symbols to be transmitted. Accordingly, referring to a second example 1850 of multi-wire transcoding using a dedicated clock line, if no clock information is to be encoded/embedded in symbol transitions, then a transmitter does not have to guarantee a transition between each symbol in the sequence of symbols.
  • circuitry/modules for converting raw symbols into symbols with guaranteed transitions may be omitted at the transmitter and circuitry/modules for converting symbols with guaranteed transitions into raw symbols may be omitted at the receiver, thus minimizing the complexity and cost associated with implementing such circuitry/modules.
  • a bits-to-transition symbol converter (Bits to T) 1852. Based on the data bits, the Bits to T 1852 generates a set of raw transition symbols 1854 for transmission over a multi-wire link 1870. Because no clock information is to be encoded/embedded in symbol transitions, the transmitter does not have to guarantee a transition of signaling state between each symbol of the set of symbols to be transmitted. Hence, a transition symbol-to-symbol converter (e.g., T to S 1806 of first example 1800) may be omitted at the transmitter of second example 1850 and the raw transition symbols 1854 may be fed directly to a serializer (SER) 1858.
  • SER serializer
  • the raw transition symbols 1854 may be serialized by the SER 1858 based on a clock signal that is transmitted on a dedicated clock line 1862.
  • the SER 1858 produces a sequence of symbols that determine the signaling state of wires of the multi-wire link 1870.
  • the sequence of symbols 1854 are provided to line drivers 1860 for transmission on the multi-wire link 1870.
  • a deserializer (DES) 1874 receives the sequence of symbols 1854 via line receivers 1872.
  • the DES 1874 deserializes the received symbols based on the clock signal received on the dedicated clock line 1862 to recover the set of raw transition symbols 1854.
  • a symbol-to- transition symbol converter e.g., S to T 1826 of first example 1800
  • a transition symbol-to-bits converter (T to Bits) 1878 converts the recovered raw transition symbols into data bits (Bits).
  • the second example 1850 improves throughput as it allows for one extra state per symbol to be transmitted.
  • FIG. 19 is an illustration of an apparatus (receiving device) 1900 configured to support operations related to communicating data bits over a multi-wire link according to one or more aspects of the disclosure (e.g., aspects related to the method of FIG. 20 described below).
  • the apparatus 1900 includes a communication interface (e.g., at least one transceiver) 1902, a storage medium 1904, a user interface 1906, a memory device 1908, and a processing circuit 1910.
  • the signaling bus may include any number of interconnecting buses and bridges depending on the specific application of the processing circuit 1910 and the overall design constraints.
  • the signaling bus links together various circuits such that each of the communication interface 1902, the storage medium 1904, the user interface 1906, and the memory device 1908 are coupled to and/or in electrical communication with the processing circuit 1910.
  • the signaling bus may also link various other circuits (not shown) such as timing sources, peripherals, voltage regulators, and power management circuits, which are well known in the art, and therefore, will not be described any further.
  • the communication interface 1902 may be adapted to facilitate wireless communication of the apparatus 1900.
  • the communication interface 1902 may include circuitry and/or code (e.g., instructions) adapted to facilitate the communication of information bi-directionally with respect to one or more communication devices in a network.
  • the communication interface 1902 may be coupled to one or more antennas 1912 for wireless communication within a wireless communication system.
  • the communication interface 1902 can be configured with one or more standalone receivers and/or transmitters, as well as one or more transceivers.
  • the communication interface 1902 includes a transmitter 1914 and a receiver 1916.
  • the memory device 1908 may represent one or more memory devices. As indicated, the memory device 1908 may maintain network-related information 1918 along with other information used by the apparatus 1900. In some implementations, the memory device 1908 and the storage medium 1904 are implemented as a common memory component.
  • the memory device 1908 may also be used for storing data that is manipulated by the processing circuit 1910 or some other component of the apparatus 1900.
  • the storage medium 1904 may represent one or more computer-readable, machine-readable, and/or processor-readable devices for storing code, such as processor executable code or instructions (e.g., software, firmware), electronic data, databases, or other digital information.
  • code such as processor executable code or instructions (e.g., software, firmware), electronic data, databases, or other digital information.
  • the storage medium 1904 may also be used for storing data that is manipulated by the processing circuit 1910 when executing code.
  • the storage medium 1904 may be any available media that can be accessed by a general purpose or special purpose processor, including portable or fixed storage devices, optical storage devices, and various other mediums capable of storing, containing or carrying code.
  • the storage medium 1904 may include a magnetic storage device (e.g., hard disk, floppy disk, magnetic strip), an optical disk (e.g., a compact disc (CD) or a digital versatile disc (DVD)), a smart card, a flash memory device (e.g., a card, a stick, or a key drive), a random access memory (RAM), a read only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), a register, a removable disk, and any other suitable medium for storing code that may be accessed and read by a computer.
  • a magnetic storage device e.g., hard disk, floppy disk, magnetic strip
  • an optical disk e.g., a compact disc (CD) or a digital versatile disc (DVD)
  • a smart card e.g., a flash memory device (e.g., a card, a stick, or a key drive
  • the storage medium 1904 may be embodied in an article of manufacture (e.g., a computer program product).
  • a computer program product may include a computer-readable medium in packaging materials.
  • the storage medium 1904 may be a non-transitory (e.g., tangible) storage medium.
  • the storage medium 1904 may be coupled to the processing circuit 1910 such that the processing circuit 1910 can read information from, and write information to, the storage medium 1904. That is, the storage medium 1904 can be coupled to the processing circuit 1910 so that the storage medium 1904 is at least accessible by the processing circuit 1910, including examples where at least one storage medium is integral to the processing circuit 1910 and/or examples where at least one storage medium is separate from the processing circuit 1910 (e.g., resident in the apparatus 1900, external to the apparatus 1900, distributed across multiple entities, etc.).
  • Code and/or instructions stored by the storage medium 1904 when executed by the processing circuit 1910, causes the processing circuit 1910 to perform one or more of the various functions and/or process operations described herein.
  • the storage medium 1904 may include operations configured for regulating operations at one or more hardware blocks of the processing circuit 1910, as well as to utilize the communication interface 1902 for wireless communication utilizing their respective communication protocols.
  • the processing circuit 1910 is generally adapted for processing, including the execution of such code/instructions stored on the storage medium 1904.
  • code or "instructions” shall be construed broadly to include without limitation programming, instructions, instruction sets, data, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise.
  • the processing circuit 1910 is arranged to obtain, process and/or send data, control data access and storage, issue commands, and control other desired operations.
  • the processing circuit 1910 may include circuitry configured to implement desired code provided by appropriate media in at least one example.
  • the processing circuit 1910 may be implemented as one or more processors, one or more controllers, and/or other structure configured to execute executable code.
  • Examples of the processing circuit 1910 may include a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic component, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein.
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • a general purpose processor may include a microprocessor, as well as any conventional processor, controller, microcontroller, or state machine.
  • the processing circuit 1910 may also be implemented as a combination of computing components, such as a combination of a DSP and a microprocessor, a number of microprocessors, one or more microprocessors in conjunction with a DSP core, an ASIC and a microprocessor, or any other number of varying configurations. These examples of the processing circuit 1910 are for illustration and other suitable configurations within the scope of the disclosure are also contemplated.
  • the processing circuit 1910 may be adapted to perform any or all of the features, processes, functions, operations and/or routines for any or all of the apparatuses described herein.
  • the term "adapted" in relation to the processing circuit 1910 may refer to the processing circuit 1910 being one or more of configured, employed, implemented, and/or programmed to perform a particular process, function, operation and/or routine according to various features described herein.
  • the processing circuit 1910 may include one or more of a symbol receiving circuit/module 1920, a clock receiving circuit/module 1922, a symbol decoding circuit/module 1924, a symbol transmitting circuit/module 1926, and a clock transmitting circuit/module 1928 that are adapted to perform any or all of the features, processes, functions, operations and/or routines described herein (e.g., features, processes, functions, operations and/or routines described with respect to FIG. 20).
  • the symbol receiving circuit/module 1920 may include circuitry and/or instructions (e.g., symbol receiving instructions 1930 stored on the storage medium 1904) adapted to perform several functions relating to, for example, receiving a sequence of symbols over a multi-wire link.
  • the clock receiving circuit/module 1922 may include circuitry and/or instructions (e.g., clock receiving instructions 1932 stored on the storage medium 1904) adapted to perform several functions relating to, for example, receiving a clock signal via a dedicated clock line, wherein the dedicated clock line is separate from, and in parallel with, the multi-wire link.
  • circuitry and/or instructions e.g., clock receiving instructions 1932 stored on the storage medium 1904
  • the dedicated clock line is separate from, and in parallel with, the multi-wire link.
  • the symbol decoding circuit/module 1924 may include circuitry and/or instructions (e.g., symbol decoding instructions 1934 stored on the storage medium 1904) adapted to perform several functions relating to, for example, decoding the sequence of symbols using the clock signal.
  • a second clock signal may be embedded in guaranteed transitions between pairs of consecutive symbols in the sequence of symbols.
  • the symbol decoding circuit/module 1924 may be configured to perform the decoding by decoding the sequence of symbols using the clock signal received via the dedicated clock line while ignoring the second clock signal.
  • the symbol decoding circuit/module 1924 may be configured to perform the decoding by converting the sequence of symbols to a set of data bits using the clock signal.
  • the symbol decoding circuit/module 1924 may be configured to perform the converting by using a transcoder to convert the sequence of symbols to a set of transition numbers and converting the set of transition numbers to the set of data bits.
  • the symbol transmitting circuit/module 1926 may include circuitry and/or instructions (e.g., symbol transmitting instructions 1936 stored on the storage medium 1904) adapted to perform several functions relating to, for example, transmitting a second sequence of symbols over at least one bi-directional line of the multi-wire link based on the clock signal received via the dedicated clock line.
  • symbol transmitting instructions 1936 stored on the storage medium 1904
  • the clock transmitting circuit/module 1928 may include circuitry and/or instructions (e.g., clock transmitting instructions 1938 stored on the storage medium 1904) adapted to perform several functions relating to, for example, transmitting a third clock signal via the dedicated clock line.
  • the third clock signal may be associated with a transmit clock used to encode data bits into a sequence of symbols transmitted by the symbol transmitting circuit/module 1926 over the at least one bidirectional line of the multi-wire link.
  • instructions stored by the storage medium 1904 when executed by the processing circuit 1910, causes the processing circuit 1910 to perform one or more of the various functions and/or process operations described herein.
  • the storage medium 1904 may include one or more of the symbol receiving instructions 1930, the clock receiving instructions 1932, the symbol decoding instructions 1934, the symbol transmitting instructions 1936, and the clock transmitting instructions 1938.
  • FIG. 20 is a flowchart 2000 illustrating a method of communicating data bits over a multi-wire link. The method may be performed by a receiving device (e.g., apparatus 100 of FIG. 1, receiver 1632 of FIG. 16, or apparatus 1900 of FIG. 19).
  • a receiving device e.g., apparatus 100 of FIG. 1, receiver 1632 of FIG. 16, or apparatus 1900 of FIG. 19.
  • the receiving device receives a sequence of symbols over a multi-wire link (e.g., multi-wire link 1612) from a transmitting device (e.g., transmitter 1602) 2002. Each symbol in the sequence of symbols may correspond to a signaling state of N wires of the multi-wire link, where N is an integer greater than 1.
  • the receiving device further receives a clock signal (e.g., DDRCLK Y 1626) via a dedicated clock line (e.g., dedicated clock line 1622), wherein the dedicated clock line is separate from, and in parallel with, the multi-wire link 2004.
  • the receiving device also decodes the sequence of symbols using the clock signal 2006.
  • a second clock signal (e.g., DDRCLK X 1624) is embedded in guaranteed transitions between pairs of consecutive symbols in the sequence of symbols. Accordingly, the receiving device decodes the sequence of symbols using the clock signal received via the dedicated clock line while ignoring the second clock signal.
  • the receiving device decodes the sequence of symbols by converting the sequence of symbols to a set of data bits using the clock signal.
  • the receiving device performs the converting by using a transcoder (e.g., transcoder 1640) to convert the sequence of symbols to a set of transition numbers and convert the set of transition numbers to the set of data bits.
  • a transcoder e.g., transcoder 1640
  • At least one line of the multi-wire link is bi-directional.
  • the receiving device may transmit a second sequence of symbols over the at least one bi-directional line based on the clock signal received via the dedicated clock line 2008.
  • both the receiving device and the transmitting device may utilize the multi-wire link for bi-directional transmissions by interleaving the lines of the multi-wire link.
  • the dedicated clock line is bi-directional and can be driven from any device transmitting over the multi-wire link.
  • the receiving device may transmit a third clock signal via the dedicated clock line 2010.
  • the third clock signal may be associated with a transmit clock used to encode data bits into a sequence of symbols transmitted by the receiving device over the at least one bidirectional line.
  • both the receiving device and the transmitting device may utilize the dedicated clock line by alternately transmitting a dedicated clock signal over the dedicated clock line.
  • FIG. 21 is an illustration of an apparatus (transmitting device) 2100 configured to support operations related to communicating data bits over a multi-wire link according to one or more aspects of the disclosure (e.g., aspects related to the method of FIG. 22 described below).
  • the apparatus 2100 includes a communication interface (e.g., at least one transceiver) 2102, a storage medium 2104, a user interface 2106, a memory device 2108, and a processing circuit 2110.
  • the signaling bus may include any number of interconnecting buses and bridges depending on the specific application of the processing circuit 2110 and the overall design constraints.
  • the signaling bus links together various circuits such that each of the communication interface 2102, the storage medium 2104, the user interface 2106, and the memory device 2108 are coupled to and/or in electrical communication with the processing circuit 2110.
  • the signaling bus may also link various other circuits (not shown) such as timing sources, peripherals, voltage regulators, and power management circuits, which are well known in the art, and therefore, will not be described any further.
  • the communication interface 2102 may be adapted to facilitate wireless communication of the apparatus 2100.
  • the communication interface 2102 may include circuitry and/or code (e.g., instructions) adapted to facilitate the communication of information bi-directionally with respect to one or more communication devices in a network.
  • the communication interface 2102 may be coupled to one or more antennas 2112 for wireless communication within a wireless communication system.
  • the communication interface 2102 can be configured with one or more standalone receivers and/or transmitters, as well as one or more transceivers.
  • the communication interface 2102 includes a transmitter 2114 and a receiver 2116.
  • the memory device 2108 may represent one or more memory devices. As indicated, the memory device 2108 may maintain network-related information 2118 along with other information used by the apparatus 2100. In some implementations, the memory device 2108 and the storage medium 2104 are implemented as a common memory component. The memory device 2108 may also be used for storing data that is manipulated by the processing circuit 2110 or some other component of the apparatus 2100. [00176]
  • the storage medium 2104 may represent one or more computer-readable, machine-readable, and/or processor-readable devices for storing code, such as processor executable code or instructions (e.g., software, firmware), electronic data, databases, or other digital information. The storage medium 2104 may also be used for storing data that is manipulated by the processing circuit 2110 when executing code.
  • the storage medium 2104 may be any available media that can be accessed by a general purpose or special purpose processor, including portable or fixed storage devices, optical storage devices, and various other mediums capable of storing, containing or carrying code.
  • the storage medium 2104 may include a magnetic storage device (e.g., hard disk, floppy disk, magnetic strip), an optical disk (e.g., a compact disc (CD) or a digital versatile disc (DVD)), a smart card, a flash memory device (e.g., a card, a stick, or a key drive), a random access memory (RAM), a read only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), a register, a removable disk, and any other suitable medium for storing code that may be accessed and read by a computer.
  • a magnetic storage device e.g., hard disk, floppy disk, magnetic strip
  • an optical disk e.g., a compact disc (CD) or a digital versatile disc (DVD)
  • a smart card e.g., a flash memory device (e.g., a card, a stick, or a key drive
  • the storage medium 2104 may be embodied in an article of manufacture (e.g., a computer program product).
  • a computer program product may include a computer-readable medium in packaging materials.
  • the storage medium 2104 may be a non-transitory (e.g., tangible) storage medium.
  • the storage medium 2104 may be coupled to the processing circuit 2110 such that the processing circuit 2110 can read information from, and write information to, the storage medium 2104. That is, the storage medium 2104 can be coupled to the processing circuit 2110 so that the storage medium 2104 is at least accessible by the processing circuit 2110, including examples where at least one storage medium is integral to the processing circuit 2110 and/or examples where at least one storage medium is separate from the processing circuit 2110 (e.g., resident in the apparatus 2100, external to the apparatus 2100, distributed across multiple entities, etc.).
  • Code and/or instructions stored by the storage medium 2104 when executed by the processing circuit 2110, causes the processing circuit 2110 to perform one or more of the various functions and/or process operations described herein.
  • the storage medium 2104 may include operations configured for regulating operations at one or more hardware blocks of the processing circuit 2110, as well as to utilize the communication interface 2102 for wireless communication utilizing their respective communication protocols.
  • the processing circuit 2110 is generally adapted for processing, including the execution of such code/instructions stored on the storage medium 2104.
  • code or "instructions” shall be construed broadly to include without limitation programming, instructions, instruction sets, data, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise.
  • the processing circuit 2110 is arranged to obtain, process and/or send data, control data access and storage, issue commands, and control other desired operations.
  • the processing circuit 2110 may include circuitry configured to implement desired code provided by appropriate media in at least one example.
  • the processing circuit 2110 may be implemented as one or more processors, one or more controllers, and/or other structure configured to execute executable code.
  • Examples of the processing circuit 2110 may include a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic component, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein.
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • a general purpose processor may include a microprocessor, as well as any conventional processor, controller, microcontroller, or state machine.
  • the processing circuit 2110 may also be implemented as a combination of computing components, such as a combination of a DSP and a microprocessor, a number of microprocessors, one or more microprocessors in conjunction with a DSP core, an ASIC and a microprocessor, or any other number of varying configurations. These examples of the processing circuit 2110 are for illustration and other suitable configurations within the scope of the disclosure are also contemplated.
  • the processing circuit 2110 may be adapted to perform any or all of the features, processes, functions, operations and/or routines for any or all of the apparatuses described herein.
  • the term "adapted" in relation to the processing circuit 2110 may refer to the processing circuit 2110 being one or more of configured, employed, implemented, and/or programmed to perform a particular process, function, operation and/or routine according to various features described herein.
  • the processing circuit 21 10 may include one or more of a clock embedding circuit/module 2120, a symbol transmitting circuit/module 2122, a clock transmitting circuit/module 2124, a symbol receiving circuit/module 2126, a clock receiving circuit/module 2128, and an encoding circuit/module 2140 that are adapted to perform any or all of the features, processes, functions, operations and/or routines described herein (e.g., features, processes, functions, operations and/or routines described with respect to FIG. 22).
  • the encoding circuit/module 2140 may include circuitry and/or instructions (e.g., encoding instructions 2142 stored on the storage medium 2104) adapted to perform several functions relating to, for example, encoding data bits into a sequence of symbols.
  • the encoding circuit/module 2140 may be configured to perform the encoding by converting the data bits to a set of transition numbers and converting the set of transition numbers to obtain the sequence of symbols.
  • the clock embedding circuit/module 2120 may include circuitry and/or instructions (e.g., clock embedding instructions 2130 stored on the storage medium 2104) adapted to perform several functions relating to, for example, embedding a second clock signal in the sequence of symbols, wherein the second clock signal is embedded in guaranteed transitions between pairs of consecutive symbols in the sequence of symbols.
  • the symbol transmitting circuit/module 2122 may include circuitry and/or instructions (e.g., symbol transmitting instructions 2132 stored on the storage medium 2104) adapted to perform several functions relating to, for example, transmitting the sequence of symbols over a multi-wire link.
  • the clock transmitting circuit/module 2124 may include circuitry and/or instructions (e.g., clock transmitting instructions 2134 stored on the storage medium 2104) adapted to perform several functions relating to, for example, transmitting a clock signal associated with the sequence of symbols via a dedicated clock line, wherein the dedicated clock line is separate from, and in parallel with, the multi- wire link.
  • circuitry and/or instructions e.g., clock transmitting instructions 2134 stored on the storage medium 2104
  • the clock transmitting circuit/module 2124 may include circuitry and/or instructions (e.g., clock transmitting instructions 2134 stored on the storage medium 2104) adapted to perform several functions relating to, for example, transmitting a clock signal associated with the sequence of symbols via a dedicated clock line, wherein the dedicated clock line is separate from, and in parallel with, the multi- wire link.
  • the symbol receiving circuit/module 2126 may include circuitry and/or instructions (e.g., symbol receiving instructions 2136 stored on the storage medium 2104) adapted to perform several functions relating to, for example, receiving a second sequence of symbols over at least one bi-directional line of the multi-wire link based on the clock signal transmitted via the dedicated clock signal.
  • the clock receiving circuit/module 2128 may include circuitry and/or instructions (e.g., clock receiving instructions 2138 stored on the storage medium 2104) adapted to perform several functions relating to, for example, receiving a third clock signal via the dedicated clock line.
  • the third clock signal may be associated with a transmit clock used to encode data bits into a sequence of symbols received by the symbol receiving circuit/module 2126 over the at least one bi-directional line of the multi-wire link.
  • the storage medium 2104 when executed by the processing circuit 2110, causes the processing circuit 2110 to perform one or more of the various functions and/or process operations described herein.
  • the storage medium 2104 may include one or more of the clock embedding instructions 2130, the symbol transmitting instructions 2132, the clock transmitting instructions 2134, the symbol receiving instructions 2136, the clock receiving instructions 2138, and the encoding instructions 2142.
  • FIG. 22 is a flowchart 2200 illustrating a method of communicating data bits over a multi-wire link. The method may be performed by a transmitting device (e.g., apparatus 100 of FIG. 1, transmitter 1602 of FIG. 16, or apparatus 2100 of FIG. 21).
  • a transmitting device e.g., apparatus 100 of FIG. 1, transmitter 1602 of FIG. 16, or apparatus 2100 of FIG. 21.
  • the transmitting device encodes data bits (e.g., Bits X 1604) into a sequence of symbols 2202. Additionally or optionally, the transmitting device embeds a second clock signal (e.g., DDRCLK X 1624) in the sequence of symbols, wherein the second clock signal is embedded in guaranteed transitions between pairs of consecutive symbols in the sequence of symbols 2204.
  • a second clock signal e.g., DDRCLK X 1624
  • Each symbol in the sequence of symbols may correspond to a signaling state of N wires of a multi-wire link (e.g., multi-wire link 1612), where N is an integer greater than 1.
  • the transmitting device further transmits the sequence of symbols over the multi-wire link 2206.
  • the transmitting device also transmits a clock signal (e.g., DDRCLK Y 1626) associated with the sequence of symbols via a dedicated clock line (e.g., dedicated clock line 1622), wherein the dedicated clock line is separate from, and in parallel with, the multi-wire link 2208.
  • a clock signal e.g., DDRCLK Y 1626
  • dedicated clock line e.g., dedicated clock line 1622
  • the transmitting device encodes the data bits into the sequence of symbols by using a transcoder (e.g., transcoder 1606) to convert the data bits to a set of transition numbers and converting the set of transition numbers to the sequence of symbols.
  • a transcoder e.g., transcoder 1606
  • At least one line of the multi-wire link is bi-directional.
  • the transmitting device may receive, from a receiving device, a second sequence of symbols over the at least one bi-directional line 2210.
  • both the receiving device and the transmitting device may utilize the multi-wire link for bidirectional transmissions by interleaving the lines of the multi-wire link.
  • the dedicated clock line is bi-directional and can be driven from any device transmitting over the multi-wire link.
  • the transmitting device may receive a third clock signal via the dedicated clock line.
  • the third clock signal may be associated with a transmit clock used to encode data bits into a sequence of symbols received by the transmitting device over the at least one bi-directional line 2212.
  • both the receiving device and the transmitting device may utilize the dedicated clock line by alternately transmitting a dedicated clock signal over the dedicated clock line.

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EP16770840.3A 2015-10-05 2016-09-09 Multi-lane n-factorial encoded and other multi-wire communication systems Withdrawn EP3360278A1 (en)

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US14/875,592 US9735948B2 (en) 2013-10-03 2015-10-05 Multi-lane N-factorial (N!) and other multi-wire communication systems
PCT/US2016/051131 WO2017062132A1 (en) 2015-10-05 2016-09-09 Multi-lane n-factorial encoded and other multi-wire communication systems

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JP (1) JP2018534847A (ru)
KR (1) KR102520096B1 (ru)
CN (1) CN108141346A (ru)
AU (1) AU2016335548A1 (ru)
BR (1) BR112018006874A2 (ru)
TW (1) TW201714443A (ru)
WO (1) WO2017062132A1 (ru)

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US11437998B2 (en) 2020-04-30 2022-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit including back side conductive lines for clock signals
CN113192950A (zh) * 2020-04-30 2021-07-30 台湾积体电路制造股份有限公司 集成电路及其制造方法

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US9711041B2 (en) * 2012-03-16 2017-07-18 Qualcomm Incorporated N-phase polarity data transfer
JP2013110554A (ja) * 2011-11-21 2013-06-06 Panasonic Corp 送信装置、受信装置及びシリアル伝送システム
US8996740B2 (en) * 2012-06-29 2015-03-31 Qualcomm Incorporated N-phase polarity output pin mode multiplexer
IN2015DN02408A (ru) * 2012-10-26 2015-09-04 Hitachi Int Electric Inc
US9363071B2 (en) * 2013-03-07 2016-06-07 Qualcomm Incorporated Circuit to recover a clock signal from multiple wire data signals that changes state every state cycle and is immune to data inter-lane skew as well as data state transition glitches
US9582457B2 (en) 2013-06-12 2017-02-28 Qualcomm Incorporated Camera control interface extension bus
US9755818B2 (en) * 2013-10-03 2017-09-05 Qualcomm Incorporated Method to enhance MIPI D-PHY link rate with minimal PHY changes and no protocol changes
US20150220472A1 (en) * 2014-02-05 2015-08-06 Qualcomm Incorporated Increasing throughput on multi-wire and multi-lane interfaces
CN106063181B (zh) 2014-03-06 2018-03-13 高通股份有限公司 接收机电路和在接收机电路上操作的方法

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KR102520096B1 (ko) 2023-04-07
CN108141346A (zh) 2018-06-08
JP2018534847A (ja) 2018-11-22
WO2017062132A1 (en) 2017-04-13
TW201714443A (zh) 2017-04-16
AU2016335548A1 (en) 2018-04-12
BR112018006874A2 (pt) 2018-10-16

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