JP2018517212A5 - - Google Patents

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Publication number
JP2018517212A5
JP2018517212A5 JP2017563196A JP2017563196A JP2018517212A5 JP 2018517212 A5 JP2018517212 A5 JP 2018517212A5 JP 2017563196 A JP2017563196 A JP 2017563196A JP 2017563196 A JP2017563196 A JP 2017563196A JP 2018517212 A5 JP2018517212 A5 JP 2018517212A5
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JP
Japan
Prior art keywords
instruction
load
storing
data
transient
Prior art date
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Application number
JP2017563196A
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English (en)
Japanese (ja)
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JP2018517212A (ja
JP6759249B2 (ja
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Priority claimed from US14/732,784 external-priority patent/US11561792B2/en
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Publication of JP2018517212A publication Critical patent/JP2018517212A/ja
Publication of JP2018517212A5 publication Critical patent/JP2018517212A5/ja
Application granted granted Critical
Publication of JP6759249B2 publication Critical patent/JP6759249B2/ja
Active legal-status Critical Current
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JP2017563196A 2015-06-08 2016-05-17 一時的なロード命令のためのシステム、装置および方法 Active JP6759249B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/732,784 US11561792B2 (en) 2015-06-08 2015-06-08 System, apparatus, and method for a transient load instruction within a VLIW operation
US14/732,784 2015-06-08
PCT/US2016/032863 WO2016200569A1 (en) 2015-06-08 2016-05-17 System, apparatus, and method for temporary load instruction

Publications (3)

Publication Number Publication Date
JP2018517212A JP2018517212A (ja) 2018-06-28
JP2018517212A5 true JP2018517212A5 (enExample) 2019-05-30
JP6759249B2 JP6759249B2 (ja) 2020-09-23

Family

ID=56081616

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017563196A Active JP6759249B2 (ja) 2015-06-08 2016-05-17 一時的なロード命令のためのシステム、装置および方法

Country Status (7)

Country Link
US (1) US11561792B2 (enExample)
EP (1) EP3304283B1 (enExample)
JP (1) JP6759249B2 (enExample)
KR (1) KR102534646B1 (enExample)
CN (1) CN107636611B (enExample)
BR (1) BR112017026374B1 (enExample)
WO (1) WO2016200569A1 (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110908716B (zh) * 2019-11-14 2022-02-08 中国人民解放军国防科技大学 一种向量聚合装载指令的实现方法

Family Cites Families (24)

* Cited by examiner, † Cited by third party
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WO1994008287A1 (en) 1992-09-29 1994-04-14 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
US5555432A (en) * 1994-08-19 1996-09-10 Intel Corporation Circuit and method for scheduling instructions by predicting future availability of resources required for execution
US5813037A (en) * 1995-03-30 1998-09-22 Intel Corporation Multi-port register file for a reservation station including a pair of interleaved storage cells with shared write data lines and a capacitance isolation mechanism
JP3449186B2 (ja) 1997-08-19 2003-09-22 富士通株式会社 パイプラインバイパス機能を有するデータ処理装置
US6026479A (en) * 1998-04-22 2000-02-15 Hewlett-Packard Company Apparatus and method for efficient switching of CPU mode between regions of high instruction level parallism and low instruction level parallism in computer programs
EP1050800A1 (en) 1999-05-03 2000-11-08 STMicroelectronics SA A pipelined execution unit
US6862677B1 (en) * 2000-02-16 2005-03-01 Koninklijke Philips Electronics N.V. System and method for eliminating write back to register using dead field indicator
EP1199629A1 (en) 2000-10-17 2002-04-24 STMicroelectronics S.r.l. Processor architecture with variable-stage pipeline
US6925639B2 (en) 2001-02-23 2005-08-02 Microsoft Corporation Method and system for register allocation
JP2002333978A (ja) * 2001-05-08 2002-11-22 Nec Corp Ｖｌｉｗ型プロセッサ
US20040044881A1 (en) * 2002-08-28 2004-03-04 Sun Microsystems, Inc. Method and system for early speculative store-load bypass
US7484075B2 (en) 2002-12-16 2009-01-27 International Business Machines Corporation Method and apparatus for providing fast remote register access in a clustered VLIW processor using partitioned register files
US7493609B2 (en) 2004-08-30 2009-02-17 International Business Machines Corporation Method and apparatus for automatic second-order predictive commoning
US20060224864A1 (en) 2005-03-31 2006-10-05 Dement Jonathan J System and method for handling multi-cycle non-pipelined instruction sequencing
JP4771079B2 (ja) 2006-07-03 2011-09-14 日本電気株式会社 Ｖｌｉｗ型プロセッサ
US8141062B2 (en) 2007-01-31 2012-03-20 Hewlett-Packard Development Company, L.P. Replacing a variable in a use of the variable with a variant of the variable
US8266411B2 (en) 2009-02-05 2012-09-11 International Business Machines Corporation Instruction set architecture with instruction characteristic bit indicating a result is not of architectural importance
US8880854B2 (en) 2009-02-11 2014-11-04 Via Technologies, Inc. Out-of-order execution microprocessor that speculatively executes dependent memory access instructions by predicting no value change by older instructions that load a segment register
US9501286B2 (en) * 2009-08-07 2016-11-22 Via Technologies, Inc. Microprocessor with ALU integrated into load unit
US8516465B2 (en) 2009-12-04 2013-08-20 Oracle America, Inc. Register prespill phase in a compiler
CN102141905B (zh) 2010-01-29 2015-02-25 上海芯豪微电子有限公司 一种处理器体系结构
US9182992B2 (en) 2012-06-08 2015-11-10 Esencia Technologies Inc Method for improving performance of a pipelined microprocessor by utilizing pipeline virtual registers
US9612840B2 (en) * 2014-03-28 2017-04-04 Intel Corporation Method and apparatus for implementing a dynamic out-of-order processor pipeline
US9841974B2 (en) * 2014-04-25 2017-12-12 Avago Technologies General Ip (Singapore) Pte. Ltd. Renaming with generation numbers

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