JP2017527886A5 - - Google Patents

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JP2017527886A5
JP2017527886A5 JP2017502132A JP2017502132A JP2017527886A5 JP 2017527886 A5 JP2017527886 A5 JP 2017527886A5 JP 2017502132 A JP2017502132 A JP 2017502132A JP 2017502132 A JP2017502132 A JP 2017502132A JP 2017527886 A5 JP2017527886 A5 JP 2017527886A5
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Japan
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vector
register
index
input data
write ports
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JP2017502132A
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Japanese (ja)
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JP6571752B2 (ja
JP2017527886A (ja
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Priority claimed from US14/486,326 external-priority patent/US20160026607A1/en
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JP2017502132A 2014-07-25 2015-06-26 ベクトルレジスタファイルにおいてデータインデックス方式アキュムレータを使用するベクトルプロセッサによるスカラ演算の並列化、関連する回路、方法およびコンピュータ可読媒体 Active JP6571752B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201462029039P 2014-07-25 2014-07-25
US62/029,039 2014-07-25
US14/486,326 US20160026607A1 (en) 2014-07-25 2014-09-15 Parallelization of scalar operations by vector processors using data-indexed accumulators in vector register files, and related circuits, methods, and computer-readable media
US14/486,326 2014-09-15
PCT/US2015/038013 WO2016014213A1 (en) 2014-07-25 2015-06-26 Parallelization of scalar operations by vector processors using data-indexed accumulators in vector register files, and related circuits, methods, and computer-readable media

Publications (3)

Publication Number Publication Date
JP2017527886A JP2017527886A (ja) 2017-09-21
JP2017527886A5 true JP2017527886A5 (enExample) 2018-07-19
JP6571752B2 JP6571752B2 (ja) 2019-09-04

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JP2017502132A Active JP6571752B2 (ja) 2014-07-25 2015-06-26 ベクトルレジスタファイルにおいてデータインデックス方式アキュムレータを使用するベクトルプロセッサによるスカラ演算の並列化、関連する回路、方法およびコンピュータ可読媒体

Country Status (5)

Country Link
US (1) US20160026607A1 (enExample)
EP (1) EP3172659B1 (enExample)
JP (1) JP6571752B2 (enExample)
CN (1) CN106537330B (enExample)
WO (1) WO2016014213A1 (enExample)

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US11544214B2 (en) * 2015-02-02 2023-01-03 Optimum Semiconductor Technologies, Inc. Monolithic vector processor configured to operate on variable length vectors using a vector length register
US9875213B2 (en) * 2015-06-26 2018-01-23 Intel Corporation Methods, apparatus, instructions and logic to provide vector packed histogram functionality
US10417730B2 (en) * 2016-12-21 2019-09-17 Intel Corporation Single input multiple data processing mechanism
US10877925B2 (en) * 2019-03-18 2020-12-29 Micron Technology, Inc. Vector processor with vector first and multiple lane configuration
US11327862B2 (en) 2019-05-20 2022-05-10 Micron Technology, Inc. Multi-lane solutions for addressing vector elements using vector index registers
US11507374B2 (en) 2019-05-20 2022-11-22 Micron Technology, Inc. True/false vector index registers and methods of populating thereof
US11340904B2 (en) 2019-05-20 2022-05-24 Micron Technology, Inc. Vector index registers
US11403256B2 (en) 2019-05-20 2022-08-02 Micron Technology, Inc. Conditional operations in a vector processor having true and false vector index registers
US11157278B2 (en) * 2019-05-27 2021-10-26 Texas Instruments Incorporated Histogram operation
CN110245756B (zh) 2019-06-14 2021-10-26 第四范式（北京）技术有限公司 用于处理数据组的可编程器件及处理数据组的方法
CN112463215B (zh) * 2019-09-09 2024-06-07 腾讯科技（深圳）有限公司 数据处理方法、装置、计算机可读存储介质和计算机设备
US11119772B2 (en) 2019-12-06 2021-09-14 International Business Machines Corporation Check pointing of accumulator register results in a microprocessor
US11900116B1 (en) 2021-09-29 2024-02-13 International Business Machines Corporation Loosely-coupled slice target file data
US12438556B2 (en) * 2022-09-30 2025-10-07 Qualcomm Incorporated Single instruction multiple data (SIMD) sparse decompression with variable density

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JPH06105459B2 (ja) * 1988-08-11 1994-12-21 日本電気株式会社 ベクトル処理装置
WO2001009717A1 (en) * 1999-08-02 2001-02-08 Morton Steven G Video digital signal processor chip
US6625685B1 (en) * 2000-09-20 2003-09-23 Broadcom Corporation Memory controller with programmable configuration
US6931511B1 (en) * 2001-12-31 2005-08-16 Apple Computer, Inc. Parallel vector table look-up with replicated index element vector
US20130212353A1 (en) * 2002-02-04 2013-08-15 Tibet MIMAR System for implementing vector look-up table operations in a SIMD processor
US7506135B1 (en) * 2002-06-03 2009-03-17 Mimar Tibet Histogram generation with vector operations in SIMD and VLIW processor by consolidating LUTs storing parallel update incremented count values for vector data elements
EP1623307B1 (en) * 2003-05-09 2015-07-01 QUALCOMM Incorporated Processor reduction unit for accumulation of multiple operands with or without saturation
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