JP2015534169A5 - - Google Patents

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JP2015534169A5
JP2015534169A5 JP2015531281A JP2015531281A JP2015534169A5 JP 2015534169 A5 JP2015534169 A5 JP 2015534169A5 JP 2015531281 A JP2015531281 A JP 2015531281A JP 2015531281 A JP2015531281 A JP 2015531281A JP 2015534169 A5 JP2015534169 A5 JP 2015534169A5
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JP2015534169A (ja
JP6263538B2 (ja
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Priority claimed from US13/606,237 external-priority patent/US20140071146A1/en
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JP2015531281A 2012-09-07 2013-09-09 マルチメディアデータ処理のための方法及びシステム Active JP6263538B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/606,237 2012-09-07
US13/606,237 US20140071146A1 (en) 2012-09-07 2012-09-07 Methods and systems for multimedia data processing
PCT/US2013/058765 WO2014039969A1 (en) 2012-09-07 2013-09-09 Methods and systems for multimedia data processing

Publications (3)

Publication Number Publication Date
JP2015534169A JP2015534169A (ja) 2015-11-26
JP2015534169A5 true JP2015534169A5 (enExample) 2016-10-27
JP6263538B2 JP6263538B2 (ja) 2018-01-17

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JP2015531281A Active JP6263538B2 (ja) 2012-09-07 2013-09-09 マルチメディアデータ処理のための方法及びシステム

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US (2) US20140071146A1 (enExample)
JP (1) JP6263538B2 (enExample)
CN (1) CN104603834A (enExample)
WO (1) WO2014039969A1 (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10085016B1 (en) * 2013-01-18 2018-09-25 Ovics Video prediction cache indexing systems and methods
US20150193907A1 (en) * 2014-01-08 2015-07-09 Nvidia Corporation Efficient cache management in a tiled architecture
US9762919B2 (en) * 2014-08-28 2017-09-12 Apple Inc. Chroma cache architecture in block processing pipelines
WO2016143336A1 (ja) * 2015-03-10 2016-09-15 日本電気株式会社 動画像符号化装置、動画像符号化方法及び動画像符号化プログラムを記憶する記録媒体
CN105323586B (zh) * 2015-04-07 2016-11-09 佛山世寰智能科技有限公司 一种用于多核并行视频编码和解码的共享内存接口
US10809928B2 (en) 2017-06-02 2020-10-20 Western Digital Technologies, Inc. Efficient data deduplication leveraging sequential chunks or auxiliary databases
CN107273310A (zh) * 2017-06-30 2017-10-20 浙江大华技术股份有限公司 一种多媒体数据的读取方法、装置、介质及设备
US10503608B2 (en) 2017-07-24 2019-12-10 Western Digital Technologies, Inc. Efficient management of reference blocks used in data deduplication
WO2019041222A1 (zh) * 2017-08-31 2019-03-07 深圳市大疆创新科技有限公司 编码方法、解码方法以及编码装置和解码装置
US10863190B2 (en) * 2018-06-14 2020-12-08 Tencent America LLC Techniques for memory bandwidth optimization in bi-predicted motion vector refinement
CN121418565A (zh) * 2019-06-07 2026-01-27 弗劳恩霍夫应用研究促进协会 基于区域的帧内块复制
TW202129591A (zh) * 2019-09-20 2021-08-01 日商索尼股份有限公司 圖像處理裝置及圖像處理方法以及程式
CN112862725B (zh) * 2021-03-12 2023-10-27 上海壁仞智能科技有限公司 用于计算的方法、计算设备和计算机可读存储介质

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5353418A (en) * 1989-05-26 1994-10-04 Massachusetts Institute Of Technology System storing thread descriptor identifying one of plural threads of computation in storage only when all data for operating on thread is ready and independently of resultant imperative processing of thread
US6219688B1 (en) * 1993-11-30 2001-04-17 Texas Instruments Incorporated Method, apparatus and system for sum of plural absolute differences
US20030163643A1 (en) * 2002-02-22 2003-08-28 Riedlinger Reid James Bank conflict determination
US9137541B2 (en) * 2003-05-23 2015-09-15 Broadcom Corporation Video data cache
US7336284B2 (en) * 2004-04-08 2008-02-26 Ati Technologies Inc. Two level cache memory architecture
US20050286777A1 (en) * 2004-06-27 2005-12-29 Roger Kumar Encoding and decoding images
US20060050976A1 (en) * 2004-09-09 2006-03-09 Stephen Molloy Caching method and apparatus for video motion compensation
US20070008323A1 (en) * 2005-07-08 2007-01-11 Yaxiong Zhou Reference picture loading cache for motion prediction
US7427990B2 (en) * 2006-01-30 2008-09-23 Ati Technologies, Inc. Data replacement method and circuit for motion prediction cache
JP2007279829A (ja) * 2006-04-03 2007-10-25 Fuji Xerox Co Ltd 画像処理装置およびプログラム
US7649538B1 (en) * 2006-11-03 2010-01-19 Nvidia Corporation Reconfigurable high performance texture pipeline with advanced filtering
JP2010102623A (ja) * 2008-10-27 2010-05-06 Nec Electronics Corp キャッシュメモリ及びその制御方法
US8510496B1 (en) * 2009-04-27 2013-08-13 Netapp, Inc. Scheduling access requests for a multi-bank low-latency random read memory device
US8458405B2 (en) * 2010-06-23 2013-06-04 International Business Machines Corporation Cache bank modeling with variable access and busy times

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