JP2016526220A5 - - Google Patents

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JP2016526220A5
JP2016526220A5 JP2016515113A JP2016515113A JP2016526220A5 JP 2016526220 A5 JP2016526220 A5 JP 2016526220A5 JP 2016515113 A JP2016515113 A JP 2016515113A JP 2016515113 A JP2016515113 A JP 2016515113A JP 2016526220 A5 JP2016526220 A5 JP 2016526220A5
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address
instruction
fields
addresses
arithmetic operation
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JP2016526220A (ja
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Priority claimed from PCT/US2014/039345 external-priority patent/WO2014190263A2/en
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JP2016515113A 2013-05-24 2014-05-23 プログラム可能な最適化を有するメモリネットワークプロセッサ Pending JP2016526220A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201361827117P 2013-05-24 2013-05-24
US61/827,117 2013-05-24
PCT/US2014/039345 WO2014190263A2 (en) 2013-05-24 2014-05-23 Memory-network processor with programmable optimizations

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JP2019100154A Division JP7210078B2 (ja) 2013-05-24 2019-05-29 プログラム可能な最適化を有するメモリネットワークプロセッサ

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JP2016526220A JP2016526220A (ja) 2016-09-01
JP2016526220A5 true JP2016526220A5 (enExample) 2017-03-09

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JP2016515113A Pending JP2016526220A (ja) 2013-05-24 2014-05-23 プログラム可能な最適化を有するメモリネットワークプロセッサ
JP2019100154A Active JP7210078B2 (ja) 2013-05-24 2019-05-29 プログラム可能な最適化を有するメモリネットワークプロセッサ
JP2021139076A Active JP7264955B2 (ja) 2013-05-24 2021-08-27 プログラム可能な最適化を有するメモリネットワークプロセッサ

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JP2019100154A Active JP7210078B2 (ja) 2013-05-24 2019-05-29 プログラム可能な最適化を有するメモリネットワークプロセッサ
JP2021139076A Active JP7264955B2 (ja) 2013-05-24 2021-08-27 プログラム可能な最適化を有するメモリネットワークプロセッサ

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US (5) US9430369B2 (enExample)
EP (2) EP3005078A2 (enExample)
JP (3) JP2016526220A (enExample)
CN (2) CN105378651B (enExample)
WO (1) WO2014190263A2 (enExample)

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