JP2006012163A5 - - Google Patents

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Publication number
JP2006012163A5
JP2006012163A5 JP2005179948A JP2005179948A JP2006012163A5 JP 2006012163 A5 JP2006012163 A5 JP 2006012163A5 JP 2005179948 A JP2005179948 A JP 2005179948A JP 2005179948 A JP2005179948 A JP 2005179948A JP 2006012163 A5 JP2006012163 A5 JP 2006012163A5
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Japan
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register
level
registers
execution
logic
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JP2005179948A
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Japanese (ja)
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JP2006012163A (ja
JP4829541B2 (ja
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Priority claimed from US10/875,373 external-priority patent/US7284092B2/en
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Publication of JP2006012163A5 publication Critical patent/JP2006012163A5/ja
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Publication of JP4829541B2 publication Critical patent/JP4829541B2/ja
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JP2005179948A 2004-06-24 2005-06-20 マルチレベル・レジスタ・ファイルを有するディジタル・データ処理装置 Expired - Fee Related JP4829541B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/875,373 US7284092B2 (en) 2004-06-24 2004-06-24 Digital data processing apparatus having multi-level register file
US10/875,373 2004-06-24

Publications (3)

Publication Number Publication Date
JP2006012163A JP2006012163A (ja) 2006-01-12
JP2006012163A5 true JP2006012163A5 (enExample) 2008-06-19
JP4829541B2 JP4829541B2 (ja) 2011-12-07

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JP2005179948A Expired - Fee Related JP4829541B2 (ja) 2004-06-24 2005-06-20 マルチレベル・レジスタ・ファイルを有するディジタル・データ処理装置

Country Status (4)

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US (2) US7284092B2 (enExample)
JP (1) JP4829541B2 (enExample)
CN (1) CN100447738C (enExample)
TW (1) TW200609744A (enExample)

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