CN100447738C - 含有多级寄存器文件的数字数据处理设备 - Google Patents

含有多级寄存器文件的数字数据处理设备 Download PDF

Info

Publication number
CN100447738C
CN100447738C CNB2005100794172A CN200510079417A CN100447738C CN 100447738 C CN100447738 C CN 100447738C CN B2005100794172 A CNB2005100794172 A CN B2005100794172A CN 200510079417 A CN200510079417 A CN 200510079417A CN 100447738 C CN100447738 C CN 100447738C
Authority
CN
China
Prior art keywords
register
order
instruction
subclass
several
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2005100794172A
Other languages
English (en)
Chinese (zh)
Other versions
CN1713137A (zh
Inventor
内森·S·纽纳马克
杰克·C·伦道夫
土屋宪一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CN1713137A publication Critical patent/CN1713137A/zh
Application granted granted Critical
Publication of CN100447738C publication Critical patent/CN100447738C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098Register arrangements
    • G06F9/3012Organisation of register space, e.g. banked or distributed register file
    • G06F9/30138Extension of register space, e.g. register cache
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30007Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098Register arrangements
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098Register arrangements
    • G06F9/3012Organisation of register space, e.g. banked or distributed register file
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098Register arrangements
    • G06F9/3012Organisation of register space, e.g. banked or distributed register file
    • G06F9/30123Organisation of register space, e.g. banked or distributed register file according to context, e.g. thread buffers
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098Register arrangements
    • G06F9/3012Organisation of register space, e.g. banked or distributed register file
    • G06F9/3013Organisation of register space, e.g. banked or distributed register file according to data content, e.g. floating-point registers, address registers
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861Recovery, e.g. branch miss-prediction, exception handling
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3888Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple threads [SIMT] in parallel

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Mathematical Physics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
CNB2005100794172A 2004-06-24 2005-06-21 含有多级寄存器文件的数字数据处理设备 Expired - Fee Related CN100447738C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/875,373 US7284092B2 (en) 2004-06-24 2004-06-24 Digital data processing apparatus having multi-level register file
US10/875,373 2004-06-24

Publications (2)

Publication Number Publication Date
CN1713137A CN1713137A (zh) 2005-12-28
CN100447738C true CN100447738C (zh) 2008-12-31

Family

ID=35507434

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2005100794172A Expired - Fee Related CN100447738C (zh) 2004-06-24 2005-06-21 含有多级寄存器文件的数字数据处理设备

Country Status (4)

Country Link
US (2) US7284092B2 (enExample)
JP (1) JP4829541B2 (enExample)
CN (1) CN100447738C (enExample)
TW (1) TW200609744A (enExample)

Families Citing this family (73)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7263593B2 (en) 2002-11-25 2007-08-28 Hitachi, Ltd. Virtualization controller and data transfer control method
US7933405B2 (en) * 2005-04-08 2011-04-26 Icera Inc. Data access and permute unit
US7788468B1 (en) 2005-12-15 2010-08-31 Nvidia Corporation Synchronization of threads in a cooperative thread array
US7861060B1 (en) * 2005-12-15 2010-12-28 Nvidia Corporation Parallel data processing systems and methods using cooperative thread arrays and thread identifier values to determine processing behavior
EP2011018B1 (en) 2006-04-12 2016-07-13 Soft Machines, Inc. Apparatus and method for processing an instruction matrix specifying parallel and dependent operations
US9069547B2 (en) 2006-09-22 2015-06-30 Intel Corporation Instruction and logic for processing text strings
US8677105B2 (en) 2006-11-14 2014-03-18 Soft Machines, Inc. Parallel processing of a sequential program using hardware generated threads and their instruction groups executing on plural execution units and accessing register file segments using dependency inheritance vectors across multiple engines
US7797514B2 (en) * 2006-11-16 2010-09-14 Texas Instruments Incorporated Scalable multi-threaded sequencing/synchronizing processor architecture
US20080229062A1 (en) * 2007-03-12 2008-09-18 Lorenzo Di Gregorio Method of sharing registers in a processor and processor
US20090006753A1 (en) * 2007-06-28 2009-01-01 David Arnold Luick Design structure for accessing a cache with an effective address
US7937530B2 (en) * 2007-06-28 2011-05-03 International Business Machines Corporation Method and apparatus for accessing a cache with an effective address
US7877582B2 (en) * 2008-01-31 2011-01-25 International Business Machines Corporation Multi-addressable register file
US7849294B2 (en) * 2008-01-31 2010-12-07 International Business Machines Corporation Sharing data in internal and memory representations with dynamic data-driven conversion
US8176406B2 (en) * 2008-03-19 2012-05-08 International Business Machines Corporation Hard error detection
US8631223B2 (en) 2010-05-12 2014-01-14 International Business Machines Corporation Register file supporting transactional processing
US8914619B2 (en) 2010-06-22 2014-12-16 International Business Machines Corporation High-word facility for extending the number of general purpose registers available to instructions
US8661227B2 (en) * 2010-09-17 2014-02-25 International Business Machines Corporation Multi-level register file supporting multiple threads
CN103250131B (zh) 2010-09-17 2015-12-16 索夫特机械公司 包括用于早期远分支预测的影子缓存的单周期多分支预测
US8725993B2 (en) 2011-02-23 2014-05-13 International Business Machines Corporation Thread transition management
KR101636602B1 (ko) 2011-03-25 2016-07-05 소프트 머신즈, 인크. 분할가능한 엔진에 의해 인스턴스화된 가상 코어를 이용한 코드 블록의 실행을 지원하는 메모리 프래그먼트
KR101620676B1 (ko) 2011-03-25 2016-05-23 소프트 머신즈, 인크. 분할가능한 엔진에 의해 인스턴스화된 가상 코어를 이용한 코드 블록의 실행을 지원하는 레지스터 파일 세그먼트
TWI533129B (zh) 2011-03-25 2016-05-11 軟體機器公司 使用可分割引擎實體化的虛擬核心執行指令序列程式碼區塊
CN103649932B (zh) 2011-05-20 2017-09-26 英特尔公司 资源的分散分配以及用于支持由多个引擎执行指令序列的互连结构
KR101639854B1 (ko) 2011-05-20 2016-07-14 소프트 머신즈, 인크. 복수의 엔진에 의해 명령어 시퀀스들의 실행을 지원하기 위한 상호접속 구조
US8595460B2 (en) * 2011-08-26 2013-11-26 Vmware, Inc. Configuring object storage system for input/output operations
US9727336B2 (en) 2011-09-16 2017-08-08 International Business Machines Corporation Fine-grained instruction enablement at sub-function granularity based on an indicated subrange of registers
US9411585B2 (en) 2011-09-16 2016-08-09 International Business Machines Corporation Multi-addressable register files and format conversions associated therewith
US20130086364A1 (en) * 2011-10-03 2013-04-04 International Business Machines Corporation Managing a Register Cache Based on an Architected Computer Instruction Set Having Operand Last-User Information
US9329869B2 (en) 2011-10-03 2016-05-03 International Business Machines Corporation Prefix computer instruction for compatibily extending instruction functionality
US9354874B2 (en) 2011-10-03 2016-05-31 International Business Machines Corporation Scalable decode-time instruction sequence optimization of dependent instructions
US8615745B2 (en) 2011-10-03 2013-12-24 International Business Machines Corporation Compiling code for an enhanced application binary interface (ABI) with decode time instruction optimization
US9690583B2 (en) 2011-10-03 2017-06-27 International Business Machines Corporation Exploiting an architected list-use operand indication in a computer system operand resource pool
US9697002B2 (en) 2011-10-03 2017-07-04 International Business Machines Corporation Computer instructions for activating and deactivating operands
US9286072B2 (en) 2011-10-03 2016-03-15 International Business Machines Corporation Using register last use infomation to perform decode-time computer instruction optimization
US10078515B2 (en) 2011-10-03 2018-09-18 International Business Machines Corporation Tracking operand liveness information in a computer system and performing function based on the liveness information
US8756591B2 (en) 2011-10-03 2014-06-17 International Business Machines Corporation Generating compiled code that indicates register liveness
US8612959B2 (en) 2011-10-03 2013-12-17 International Business Machines Corporation Linking code for an enhanced application binary interface (ABI) with decode time instruction optimization
WO2013077876A1 (en) 2011-11-22 2013-05-30 Soft Machines, Inc. A microprocessor accelerated code optimizer
US10191746B2 (en) 2011-11-22 2019-01-29 Intel Corporation Accelerated code optimizer for a multiengine microprocessor
CN104025019B (zh) * 2011-12-23 2018-01-05 英特尔公司 用于执行双块绝对差求和的系统、装置和方法
US10275251B2 (en) 2012-10-31 2019-04-30 International Business Machines Corporation Processor for avoiding reduced performance using instruction metadata to determine not to maintain a mapping of a logical register to a physical register in a first level register file
US9286068B2 (en) 2012-10-31 2016-03-15 International Business Machines Corporation Efficient usage of a multi-level register file utilizing a register file bypass
US9811342B2 (en) 2013-03-15 2017-11-07 Intel Corporation Method for performing dual dispatch of blocks and half blocks
WO2014150991A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for implementing a reduced size register view data structure in a microprocessor
US9886279B2 (en) 2013-03-15 2018-02-06 Intel Corporation Method for populating and instruction view data structure by using register template snapshots
US9891924B2 (en) 2013-03-15 2018-02-13 Intel Corporation Method for implementing a reduced size register view data structure in a microprocessor
WO2014150806A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for populating register view data structure by using register template snapshots
US9569216B2 (en) 2013-03-15 2017-02-14 Soft Machines, Inc. Method for populating a source view data structure by using register template snapshots
KR102063656B1 (ko) 2013-03-15 2020-01-09 소프트 머신즈, 인크. 블록들로 그룹화된 멀티스레드 명령어들을 실행하기 위한 방법
CN105247484B (zh) 2013-03-15 2021-02-23 英特尔公司 利用本地分布式标志体系架构来仿真访客集中式标志体系架构的方法
US10275255B2 (en) 2013-03-15 2019-04-30 Intel Corporation Method for dependency broadcasting through a source organized source view data structure
US9904625B2 (en) 2013-03-15 2018-02-27 Intel Corporation Methods, systems and apparatus for predicting the way of a set associative cache
WO2014150971A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for dependency broadcasting through a block organized source view data structure
US10140138B2 (en) 2013-03-15 2018-11-27 Intel Corporation Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation
US9508112B2 (en) * 2013-07-31 2016-11-29 Apple Inc. Multi-threaded GPU pipeline
US9459869B2 (en) 2013-08-20 2016-10-04 Apple Inc. Intelligent caching for an operand cache
US9378146B2 (en) 2013-08-20 2016-06-28 Apple Inc. Operand cache design
US9652233B2 (en) 2013-08-20 2017-05-16 Apple Inc. Hint values for use with an operand cache
US9870340B2 (en) * 2015-03-30 2018-01-16 International Business Machines Corporation Multithreading in vector processors
US9952865B2 (en) * 2015-04-04 2018-04-24 Texas Instruments Incorporated Low energy accelerator processor architecture with short parallel instruction word and non-orthogonal register data file
US9619394B2 (en) 2015-07-21 2017-04-11 Apple Inc. Operand cache flush, eviction, and clean techniques using hint information and dirty information
US9785567B2 (en) 2015-09-11 2017-10-10 Apple Inc. Operand cache control techniques
US10241790B2 (en) 2015-12-15 2019-03-26 International Business Machines Corporation Operation of a multi-slice processor with reduced flush and restore latency
US20170371654A1 (en) * 2016-06-23 2017-12-28 Advanced Micro Devices, Inc. System and method for using virtual vector register files
GB2552154B (en) * 2016-07-08 2019-03-06 Advanced Risc Mach Ltd Vector register access
US10613987B2 (en) 2016-09-23 2020-04-07 Apple Inc. Operand cache coherence for SIMD processor supporting predication
US10423415B2 (en) * 2017-04-01 2019-09-24 Intel Corporation Hierarchical general register file (GRF) for execution block
CN111951845B (zh) * 2019-05-15 2022-06-03 上海磁宇信息科技有限公司 一种分级管理冗余存储的mram芯片
US11848980B2 (en) * 2020-07-09 2023-12-19 Boray Data Technology Co. Ltd. Distributed pipeline configuration in a distributed computing system
TWI783310B (zh) * 2020-11-26 2022-11-11 華邦電子股份有限公司 計數方法以及計數裝置
CN112817639B (zh) * 2021-01-13 2022-04-08 中国民航大学 Gpu读写单元通过操作数收集器访问寄存器文件的方法
CN116560729B (zh) * 2023-05-11 2024-06-04 北京市合芯数字科技有限公司 一种多线程处理器的寄存器多级管理方法及系统
US20250130799A1 (en) * 2023-10-19 2025-04-24 Ampere Computing Llc Techniques for performing non-vector micro-operations on vector hardware

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5226142A (en) * 1990-11-21 1993-07-06 Ross Technology, Inc. High performance register file with overlapping windows
US5701507A (en) * 1991-12-26 1997-12-23 Texas Instruments Incorporated Architecture of a chip having multiple processors and multiple memories
US5721868A (en) * 1994-01-21 1998-02-24 Sun Microsystems, Inc. Rapid register file access by limiting access to a selectable register subset
US5974438A (en) * 1996-12-31 1999-10-26 Compaq Computer Corporation Scoreboard for cached multi-thread processes
US20040064680A1 (en) * 2002-09-26 2004-04-01 Sudarshan Kadambi Method and apparatus for reducing register file access times in pipelined processors

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4128880A (en) * 1976-06-30 1978-12-05 Cray Research, Inc. Computer vector register processing
US5179681A (en) * 1989-11-16 1993-01-12 Sun Microsystems, Inc. Method and apparatus for current window cache with switchable address and out cache registers
JPH06222990A (ja) * 1992-10-16 1994-08-12 Fujitsu Ltd データ処理装置
US5592679A (en) * 1994-11-14 1997-01-07 Sun Microsystems, Inc. Apparatus and method for distributed control in a processor architecture
EP0717359A3 (en) * 1994-12-15 1997-02-05 Sun Microsystems Inc Register cache memory for a computer processor
US6131155A (en) * 1997-11-07 2000-10-10 Pmc Sierra Ltd. Programmer-visible uncached load/store unit having burst capability
US6108770A (en) * 1998-06-24 2000-08-22 Digital Equipment Corporation Method and apparatus for predicting memory dependence using store sets
US6381678B2 (en) * 1998-10-30 2002-04-30 Intel Corporation Processing ordered data requests to a memory
US6282614B1 (en) * 1999-04-15 2001-08-28 National Semiconductor Corporation Apparatus and method for reducing the power consumption of a microprocessor with multiple levels of caches
US6557078B1 (en) * 2000-02-21 2003-04-29 Hewlett Packard Development Company, L.P. Cache chain structure to implement high bandwidth low latency cache memory subsystem
DE60143194D1 (de) * 2000-04-12 2010-11-18 Dsp Group Switzerland Ag Datenverarbeitungsschaltung mit cachespeicher und vorrichtung mit solcher schaltung
JP3659941B2 (ja) * 2002-07-26 2005-06-15 インターナショナル・ビジネス・マシーンズ・コーポレーション マイクロプロセッサおよびその処理方法
US20040222379A1 (en) * 2003-05-09 2004-11-11 Cook Michael Joseph Event counter for an imaging device
US7206923B2 (en) * 2003-12-12 2007-04-17 International Business Machines Corporation Method and apparatus for eliminating the need for register assignment, allocation, spilling and re-filling
US20050138297A1 (en) * 2003-12-23 2005-06-23 Intel Corporation Register file cache
US7694075B1 (en) * 2005-03-09 2010-04-06 Globalfoundries Inc. System for enabling and disabling cache and a method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5226142A (en) * 1990-11-21 1993-07-06 Ross Technology, Inc. High performance register file with overlapping windows
US5701507A (en) * 1991-12-26 1997-12-23 Texas Instruments Incorporated Architecture of a chip having multiple processors and multiple memories
US5721868A (en) * 1994-01-21 1998-02-24 Sun Microsystems, Inc. Rapid register file access by limiting access to a selectable register subset
US5974438A (en) * 1996-12-31 1999-10-26 Compaq Computer Corporation Scoreboard for cached multi-thread processes
US20040064680A1 (en) * 2002-09-26 2004-04-01 Sudarshan Kadambi Method and apparatus for reducing register file access times in pipelined processors

Also Published As

Publication number Publication date
JP2006012163A (ja) 2006-01-12
JP4829541B2 (ja) 2011-12-07
US20080022044A1 (en) 2008-01-24
TW200609744A (en) 2006-03-16
US7284092B2 (en) 2007-10-16
US20050289299A1 (en) 2005-12-29
US8793433B2 (en) 2014-07-29
CN1713137A (zh) 2005-12-28

Similar Documents

Publication Publication Date Title
CN100447738C (zh) 含有多级寄存器文件的数字数据处理设备
NL2028867B1 (en) Vector Processor Architectures
US8516280B2 (en) Parallel processing computer systems with reduced power consumption and methods for providing the same
US7124318B2 (en) Multiple parallel pipeline processor having self-repairing capability
KR100279784B1 (ko) 연산처리장치
JP3916680B2 (ja) プロセッサ
US5513366A (en) Method and system for dynamically reconfiguring a register file in a vector processor
US6301653B1 (en) Processor containing data path units with forwarding paths between two data path units and a unique configuration or register blocks
KR100346515B1 (ko) 수퍼파이프라인된수퍼스칼라프로세서를위한임시파이프라인레지스터파일
JP3593346B2 (ja) マルチポートメモリ及びそれをアクセスするデータ処理装置
US20130054939A1 (en) Integrated circuit having a hard core and a soft core
JP2006509306A (ja) 関係アプリケーションへのデータ処理システム相互参照用セルエンジン
WO1999036852A1 (en) Digital signal processor having data alignment buffer for performing unaligned data accesses
US6963962B2 (en) Memory system for supporting multiple parallel accesses at very high frequencies
US20060265555A1 (en) Methods and apparatus for sharing processor resources
KR100681199B1 (ko) 코어스 그레인 어레이에서의 인터럽트 처리 방법 및 장치
CN101727435B (zh) 一种超长指令字处理器
US6301651B1 (en) Method and apparatus for folding a plurality of instructions
KR100431975B1 (ko) 분기에의한중단이없는파이프라인방식의마이크로프로세서를위한다중명령디스패치시스템
EP1220089B1 (en) Method for executing conditional branch instructions in a data processor and corresponding data processor
US20070136560A1 (en) Method and apparatus for a shift register based interconnection for a massively parallel processor array
US20020138535A1 (en) SIMD sum of product arithmetic method and circuit, and semiconductor integrated circuit device equipped with the SIMD sum of product arithmetic circuit
US5832533A (en) Method and system for addressing registers in a data processing unit in an indexed addressing mode
US8140833B2 (en) Implementing polymorphic branch history table reconfiguration
JPH077388B2 (ja) ベクトル演算処理装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20081231

Termination date: 20110621