DE60143194D1 - Datenverarbeitungsschaltung mit cachespeicher und vorrichtung mit solcher schaltung - Google Patents

Datenverarbeitungsschaltung mit cachespeicher und vorrichtung mit solcher schaltung

Info

Publication number
DE60143194D1
DE60143194D1 DE60143194T DE60143194T DE60143194D1 DE 60143194 D1 DE60143194 D1 DE 60143194D1 DE 60143194 T DE60143194 T DE 60143194T DE 60143194 T DE60143194 T DE 60143194T DE 60143194 D1 DE60143194 D1 DE 60143194D1
Authority
DE
Germany
Prior art keywords
cache
memory
processor
access requests
main memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60143194T
Other languages
English (en)
Inventor
Martijn J Emons
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
DSP Group Switzerland AG
Original Assignee
DSP Group Switzerland AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by DSP Group Switzerland AG filed Critical DSP Group Switzerland AG
Application granted granted Critical
Publication of DE60143194D1 publication Critical patent/DE60143194D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3215—Monitoring of peripheral devices
    • G06F1/3225—Monitoring of peripheral devices of memory devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3275—Power saving in memory, e.g. RAM, cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE60143194T 2000-04-12 2001-04-03 Datenverarbeitungsschaltung mit cachespeicher und vorrichtung mit solcher schaltung Expired - Lifetime DE60143194D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP00201310 2000-04-12
PCT/EP2001/003751 WO2001077836A1 (en) 2000-04-12 2001-04-03 Data processing circuit with a cache memory and apparatus containing such a circuit

Publications (1)

Publication Number Publication Date
DE60143194D1 true DE60143194D1 (de) 2010-11-18

Family

ID=8171332

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60143194T Expired - Lifetime DE60143194D1 (de) 2000-04-12 2001-04-03 Datenverarbeitungsschaltung mit cachespeicher und vorrichtung mit solcher schaltung

Country Status (7)

Country Link
US (1) US7076612B2 (de)
EP (1) EP1275046B1 (de)
JP (1) JP2003530640A (de)
KR (1) KR100798020B1 (de)
AT (1) ATE484026T1 (de)
DE (1) DE60143194D1 (de)
WO (1) WO2001077836A1 (de)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030145170A1 (en) * 2002-01-31 2003-07-31 Kever Wayne D. Dynamically adjusted cache power supply to optimize for cache access or power consumption
GB2390700B (en) * 2002-04-15 2006-03-15 Alphamosaic Ltd Narrow/wide cache
DE10338038B4 (de) * 2002-12-13 2005-11-17 Hewlett-Packard Development Co., L.P., Houston Vorrichtung zum Sparen einer Leistung, die durch ein System verbraucht wird, das eine integrierte Prozessorschaltung aufweist
US7284092B2 (en) * 2004-06-24 2007-10-16 International Business Machines Corporation Digital data processing apparatus having multi-level register file
US7472224B1 (en) * 2004-10-01 2008-12-30 Advanced Micro Devices, Inc. Reconfigurable processing node including first and second processor cores
US7257678B2 (en) * 2004-10-01 2007-08-14 Advanced Micro Devices, Inc. Dynamic reconfiguration of cache memory
US7237065B2 (en) * 2005-05-24 2007-06-26 Texas Instruments Incorporated Configurable cache system depending on instruction type
US8683139B2 (en) 2006-10-31 2014-03-25 Hewlett-Packard Development Company, L.P. Cache and method for cache bypass functionality
US7783830B2 (en) * 2006-11-29 2010-08-24 Seagate Technology Llc Solid state device pattern for non-solid state storage media
JP2009093559A (ja) * 2007-10-11 2009-04-30 Nec Corp プロセッサ、情報処理装置、プロセッサのキャッシュ制御方法
US8166326B2 (en) * 2007-11-08 2012-04-24 International Business Machines Corporation Managing power consumption in a computer
US20090132842A1 (en) * 2007-11-15 2009-05-21 International Business Machines Corporation Managing Computer Power Consumption In A Computer Equipment Rack
US8041521B2 (en) * 2007-11-28 2011-10-18 International Business Machines Corporation Estimating power consumption of computing components configured in a computing system
US8103884B2 (en) 2008-06-25 2012-01-24 International Business Machines Corporation Managing power consumption of a computer
TWI361372B (en) * 2008-07-11 2012-04-01 Htc Corp Touch-sensitive control systems and methods
TW201017421A (en) * 2008-09-24 2010-05-01 Panasonic Corp Cache memory, memory system and control method therefor
US8041976B2 (en) * 2008-10-01 2011-10-18 International Business Machines Corporation Power management for clusters of computers
US8514215B2 (en) * 2008-11-12 2013-08-20 International Business Machines Corporation Dynamically managing power consumption of a computer with graphics adapter configurations
US8924645B2 (en) 2010-03-08 2014-12-30 Hewlett-Packard Development Company, L. P. Data storage apparatus and methods
JP5484281B2 (ja) * 2010-09-21 2014-05-07 三菱電機株式会社 情報処理システム
WO2012049760A1 (ja) 2010-10-14 2012-04-19 富士通株式会社 ストレージ制御装置における基準時間設定方法
JP5668858B2 (ja) * 2011-08-23 2015-02-12 富士通株式会社 情報処理装置及びスケジューリング方法
KR102049265B1 (ko) * 2012-11-30 2019-11-28 삼성전자주식회사 최대절전 모드를 가지는 시스템 및 그 동작방법
US9568986B2 (en) * 2013-09-25 2017-02-14 International Business Machines Corporation System-wide power conservation using memory cache
KR102589298B1 (ko) 2016-05-11 2023-10-13 삼성전자주식회사 그래픽스 프로세싱 장치 및, 그래픽스 프로세싱 장치에서 캐시 바이패스를 제어하는 방법
US10592142B2 (en) * 2016-09-30 2020-03-17 International Business Machines Corporation Toggling modal transient memory access state

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4075686A (en) * 1976-12-30 1978-02-21 Honeywell Information Systems Inc. Input/output cache system including bypass capability
US4429363A (en) * 1981-10-15 1984-01-31 International Business Machines Corporation Method and apparatus for managing data movements from a backing store to a caching buffer store
US4506323A (en) * 1982-03-03 1985-03-19 Sperry Corporation Cache/disk file status indicator with data protection feature
US5247639A (en) * 1989-06-20 1993-09-21 Nec Corporation Microprocessor having cache bypass signal terminal
US5875464A (en) * 1991-12-10 1999-02-23 International Business Machines Corporation Computer system with private and shared partitions in cache
US5913223A (en) * 1993-01-25 1999-06-15 Sheppard; Douglas Parks Low power set associative cache memory
US5682515A (en) * 1993-01-25 1997-10-28 Benchmarq Microelectronics, Inc. Low power set associative cache memory with status inhibit of cache data output
JPH06348595A (ja) * 1993-06-07 1994-12-22 Hitachi Ltd キャッシュ装置
US5809532A (en) * 1993-12-06 1998-09-15 Motorola Inc. Data processor with cache and method of operation
US5632038A (en) * 1994-02-22 1997-05-20 Dell Usa, L.P. Secondary cache system for portable computer
US5430683A (en) * 1994-03-15 1995-07-04 Intel Corporation Method and apparatus for reducing power in on-chip tag SRAM
US5551001A (en) * 1994-06-29 1996-08-27 Exponential Technology, Inc. Master-slave cache system for instruction and data cache memories
US5729713A (en) * 1995-03-27 1998-03-17 Texas Instruments Incorporated Data processing with first level cache bypassing after a data transfer becomes excessively long
JPH0950401A (ja) * 1995-08-09 1997-02-18 Toshiba Corp キャッシュメモリ及びそれを備えた情報処理装置
US5692202A (en) * 1995-12-29 1997-11-25 Intel Corporation System, apparatus, and method for managing power in a computer system
US6643745B1 (en) * 1998-03-31 2003-11-04 Intel Corporation Method and apparatus for prefetching data into cache
JP2000100054A (ja) * 1998-09-22 2000-04-07 Matsushita Electric Ind Co Ltd 二次記憶装置
US6282614B1 (en) * 1999-04-15 2001-08-28 National Semiconductor Corporation Apparatus and method for reducing the power consumption of a microprocessor with multiple levels of caches
US6496888B1 (en) * 1999-09-15 2002-12-17 Intel Corporation Incorporation of bus ratio strap options in chipset logic
KR100351504B1 (ko) * 2000-06-05 2002-09-05 삼성전자 주식회사 캐쉬 메모리, 그의 전력 소비 절감 방법 그리고 캐쉬메모리를 구비하는 데이터 처리 시스템
US6480938B2 (en) * 2000-12-15 2002-11-12 Hewlett-Packard Company Efficient I-cache structure to support instructions crossing line boundaries
US6772355B2 (en) * 2000-12-29 2004-08-03 Stmicroelectronics, Inc. System and method for reducing power consumption in a data processor having a clustered architecture
US6434076B1 (en) * 2001-01-22 2002-08-13 International Business Machines Corporation Refresh control circuit for low-power SRAM applications

Also Published As

Publication number Publication date
US7076612B2 (en) 2006-07-11
KR20020023231A (ko) 2002-03-28
EP1275046A1 (de) 2003-01-15
ATE484026T1 (de) 2010-10-15
EP1275046B1 (de) 2010-10-06
KR100798020B1 (ko) 2008-01-24
US20010032298A1 (en) 2001-10-18
WO2001077836A1 (en) 2001-10-18
JP2003530640A (ja) 2003-10-14

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