JP2018528510A5 - - Google Patents

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Publication number
JP2018528510A5
JP2018528510A5 JP2018500902A JP2018500902A JP2018528510A5 JP 2018528510 A5 JP2018528510 A5 JP 2018528510A5 JP 2018500902 A JP2018500902 A JP 2018500902A JP 2018500902 A JP2018500902 A JP 2018500902A JP 2018528510 A5 JP2018528510 A5 JP 2018528510A5
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JP
Japan
Prior art keywords
frequency
reset
memory
processor
command
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2018500902A
Other languages
English (en)
Japanese (ja)
Other versions
JP2018528510A (ja
Filing date
Publication date
Priority claimed from US15/170,742 external-priority patent/US10331526B2/en
Application filed filed Critical
Publication of JP2018528510A publication Critical patent/JP2018528510A/ja
Publication of JP2018528510A5 publication Critical patent/JP2018528510A5/ja
Pending legal-status Critical Current

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JP2018500902A 2015-07-31 2016-06-02 メモリの周波数リセットのためのシステム、方法、および装置 Pending JP2018528510A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201562199639P 2015-07-31 2015-07-31
US62/199,639 2015-07-31
US15/170,742 US10331526B2 (en) 2015-07-31 2016-06-01 Systems, methods, and apparatus for frequency reset of a memory
US15/170,742 2016-06-01
PCT/US2016/035520 WO2017023408A1 (en) 2015-07-31 2016-06-02 Systems, methods, and apparatus for frequency reset of a memory

Publications (2)

Publication Number Publication Date
JP2018528510A JP2018528510A (ja) 2018-09-27
JP2018528510A5 true JP2018528510A5 (enExample) 2019-06-13

Family

ID=57883569

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018500902A Pending JP2018528510A (ja) 2015-07-31 2016-06-02 メモリの周波数リセットのためのシステム、方法、および装置

Country Status (9)

Country Link
US (1) US10331526B2 (enExample)
EP (1) EP3304325B1 (enExample)
JP (1) JP2018528510A (enExample)
KR (1) KR20180035815A (enExample)
CN (1) CN107851075A (enExample)
BR (1) BR112018002030A2 (enExample)
CA (1) CA2989298A1 (enExample)
TW (1) TW201712681A (enExample)
WO (1) WO2017023408A1 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9978437B2 (en) * 2015-12-11 2018-05-22 Micron Technology, Inc. Apparatuses and methods for dynamic voltage and frequency switching for dynamic random access memory
US10599206B2 (en) * 2017-06-02 2020-03-24 Intel Corporation Techniques to change a mode of operation for a memory device
US11056166B2 (en) * 2019-07-17 2021-07-06 Micron Technology, Inc. Performing a refresh operation based on a characteristic of a memory sub-system

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5229970A (en) * 1991-04-15 1993-07-20 Micron Technology, Inc. Circuit for synchronizing refresh cycles in self-refreshing drams having timing circuit shutdown
US5446695A (en) * 1994-03-22 1995-08-29 International Business Machines Corporation Memory device with programmable self-refreshing and testing methods therefore
KR100276386B1 (ko) * 1997-12-06 2001-01-15 윤종용 반도체메모리장치의리프레시방법및회로
US7088633B2 (en) * 2004-05-27 2006-08-08 Qualcomm Incorporated Method and system for providing seamless self-refresh for directed bank refresh in volatile memories
US8593470B2 (en) * 2005-02-24 2013-11-26 Ati Technologies Ulc Dynamic memory clock switching circuit and method for adjusting power consumption
US7639764B2 (en) * 2005-08-17 2009-12-29 Atmel Corporation Method and apparatus for synchronizing data between different clock domains in a memory controller
US7369451B2 (en) * 2005-10-31 2008-05-06 Mosaid Technologies Incorporated Dynamic random access memory device and method for self-refreshing memory cells
JP4967561B2 (ja) * 2006-09-20 2012-07-04 富士通株式会社 移動通信端末、移動通信システム、基地局及び通信方法
US8069327B2 (en) * 2006-12-28 2011-11-29 Intel Corporation Commands scheduled for frequency mismatch bubbles
US7624310B2 (en) * 2007-07-11 2009-11-24 Micron Technology, Inc. System and method for initializing a memory system, and memory device and processor-based system using same
US20090024916A1 (en) * 2007-07-20 2009-01-22 Burckart Erik J Seamless Asynchronous Updates of Dynamic Content
US8275945B2 (en) * 2008-02-05 2012-09-25 Spansion Llc Mitigation of flash memory latency and bandwidth limitations via a write activity log and buffer
US7969807B2 (en) * 2008-03-05 2011-06-28 Qimonda Ag Memory that retains data when switching partial array self refresh settings
US8161356B2 (en) * 2008-03-28 2012-04-17 Intel Corporation Systems, methods, and apparatuses to save memory self-refresh power
JP4517312B2 (ja) * 2008-07-08 2010-08-04 ソニー株式会社 メモリアクセス制御装置および撮像装置
CN102402454B (zh) * 2010-09-10 2013-10-02 联想(北京)有限公司 一种调节内存运行频率的方法及电子设备
KR101837239B1 (ko) * 2011-12-29 2018-03-09 르네사스 일렉트로닉스 가부시키가이샤 반도체 장치
JP2014019354A (ja) * 2012-07-20 2014-02-03 Toyota Motor Corp ハイブリッド自動車
US9704557B2 (en) * 2013-09-25 2017-07-11 Qualcomm Incorporated Method and apparatus for storing retention time profile information based on retention time and temperature
KR102216559B1 (ko) * 2013-12-09 2021-02-17 삼성전자주식회사 멀티 칩 패키지에 적합한 반도체 메모리 장치

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