BR112018002030A2 - sistemas, métodos e aparelho para redefinição de frequência de uma memória - Google Patents

sistemas, métodos e aparelho para redefinição de frequência de uma memória

Info

Publication number
BR112018002030A2
BR112018002030A2 BR112018002030A BR112018002030A BR112018002030A2 BR 112018002030 A2 BR112018002030 A2 BR 112018002030A2 BR 112018002030 A BR112018002030 A BR 112018002030A BR 112018002030 A BR112018002030 A BR 112018002030A BR 112018002030 A2 BR112018002030 A2 BR 112018002030A2
Authority
BR
Brazil
Prior art keywords
auto
memory
update
reset
frequency
Prior art date
Application number
BR112018002030A
Other languages
English (en)
Inventor
Jose Edwin
Wang Tao
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112018002030A2 publication Critical patent/BR112018002030A2/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G06F3/0632—Configuration or reconfiguration of storage systems by initialisation or re-initialisation of storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1471—Saving, restoring, recovering or retrying involving logging of persistent data for recovery
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/805—Real-time
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/84—Using snapshots, i.e. a logical point-in-time copy of the data
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/85—Active fault masking without idle spares

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Quality & Reliability (AREA)
  • Computer Security & Cryptography (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)
  • Memory System (AREA)

Abstract

alguns aspectos da revelação incluem uma sequência de entrada de auto-atualização para uma memória, tal como uma dram, que pode ser usada para evitar uma divergência de frequência entre um processador do sistema e uma memória do sistema. a sequência de entrada de auto-atualização pode sinalizar que a memória redefina o estado de ponto de definição de frequência e se padronize para o estado de ativação mediante uma saída do processo de auto-atualização. em outro aspecto, um novo registro de modo pode ser usado para indicar que o ponto de definição de frequência precisa ser reinicializado após o próximo comando de entrada de auto-atualização. nesse aspecto, o processador executará um comando de registro de gravação de modo seguido por uma entrada de auto-atualização em resposta à ocorrência de um evento de falha. então, a memória se redefinirá para o ponto de definição de frequência padrão no fim da execução da entrada de auto-atualização.
BR112018002030A 2015-07-31 2016-06-02 sistemas, métodos e aparelho para redefinição de frequência de uma memória BR112018002030A2 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201562199639P 2015-07-31 2015-07-31
US15/170,742 US10331526B2 (en) 2015-07-31 2016-06-01 Systems, methods, and apparatus for frequency reset of a memory
PCT/US2016/035520 WO2017023408A1 (en) 2015-07-31 2016-06-02 Systems, methods, and apparatus for frequency reset of a memory

Publications (1)

Publication Number Publication Date
BR112018002030A2 true BR112018002030A2 (pt) 2018-09-11

Family

ID=57883569

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112018002030A BR112018002030A2 (pt) 2015-07-31 2016-06-02 sistemas, métodos e aparelho para redefinição de frequência de uma memória

Country Status (9)

Country Link
US (1) US10331526B2 (pt)
EP (1) EP3304325B1 (pt)
JP (1) JP2018528510A (pt)
KR (1) KR20180035815A (pt)
CN (1) CN107851075A (pt)
BR (1) BR112018002030A2 (pt)
CA (1) CA2989298A1 (pt)
TW (1) TW201712681A (pt)
WO (1) WO2017023408A1 (pt)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9978437B2 (en) 2015-12-11 2018-05-22 Micron Technology, Inc. Apparatuses and methods for dynamic voltage and frequency switching for dynamic random access memory
US10599206B2 (en) * 2017-06-02 2020-03-24 Intel Corporation Techniques to change a mode of operation for a memory device

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5229970A (en) * 1991-04-15 1993-07-20 Micron Technology, Inc. Circuit for synchronizing refresh cycles in self-refreshing drams having timing circuit shutdown
US5446695A (en) * 1994-03-22 1995-08-29 International Business Machines Corporation Memory device with programmable self-refreshing and testing methods therefore
KR100276386B1 (ko) * 1997-12-06 2001-01-15 윤종용 반도체메모리장치의리프레시방법및회로
US7088633B2 (en) * 2004-05-27 2006-08-08 Qualcomm Incorporated Method and system for providing seamless self-refresh for directed bank refresh in volatile memories
US8593470B2 (en) * 2005-02-24 2013-11-26 Ati Technologies Ulc Dynamic memory clock switching circuit and method for adjusting power consumption
US7639764B2 (en) * 2005-08-17 2009-12-29 Atmel Corporation Method and apparatus for synchronizing data between different clock domains in a memory controller
US7369451B2 (en) * 2005-10-31 2008-05-06 Mosaid Technologies Incorporated Dynamic random access memory device and method for self-refreshing memory cells
JP4967561B2 (ja) * 2006-09-20 2012-07-04 富士通株式会社 移動通信端末、移動通信システム、基地局及び通信方法
US8069327B2 (en) * 2006-12-28 2011-11-29 Intel Corporation Commands scheduled for frequency mismatch bubbles
US7624310B2 (en) * 2007-07-11 2009-11-24 Micron Technology, Inc. System and method for initializing a memory system, and memory device and processor-based system using same
US20090024916A1 (en) * 2007-07-20 2009-01-22 Burckart Erik J Seamless Asynchronous Updates of Dynamic Content
US8275945B2 (en) * 2008-02-05 2012-09-25 Spansion Llc Mitigation of flash memory latency and bandwidth limitations via a write activity log and buffer
US7969807B2 (en) * 2008-03-05 2011-06-28 Qimonda Ag Memory that retains data when switching partial array self refresh settings
US8161356B2 (en) * 2008-03-28 2012-04-17 Intel Corporation Systems, methods, and apparatuses to save memory self-refresh power
JP4517312B2 (ja) * 2008-07-08 2010-08-04 ソニー株式会社 メモリアクセス制御装置および撮像装置
CN102402454B (zh) * 2010-09-10 2013-10-02 联想(北京)有限公司 一种调节内存运行频率的方法及电子设备
CN104012002B (zh) * 2011-12-29 2017-04-12 瑞萨电子株式会社 半导体装置
JP2014019354A (ja) * 2012-07-20 2014-02-03 Toyota Motor Corp ハイブリッド自動車
US9704557B2 (en) * 2013-09-25 2017-07-11 Qualcomm Incorporated Method and apparatus for storing retention time profile information based on retention time and temperature
KR102216559B1 (ko) * 2013-12-09 2021-02-17 삼성전자주식회사 멀티 칩 패키지에 적합한 반도체 메모리 장치

Also Published As

Publication number Publication date
WO2017023408A1 (en) 2017-02-09
CN107851075A (zh) 2018-03-27
JP2018528510A (ja) 2018-09-27
KR20180035815A (ko) 2018-04-06
CA2989298A1 (en) 2017-02-09
US20170031785A1 (en) 2017-02-02
EP3304325B1 (en) 2019-03-20
US10331526B2 (en) 2019-06-25
EP3304325A1 (en) 2018-04-11
TW201712681A (zh) 2017-04-01

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Legal Events

Date Code Title Description
B06U Preliminary requirement: requests with searches performed by other patent offices: suspension of the patent application procedure
B11B Dismissal acc. art. 36, par 1 of ipl - no reply within 90 days to fullfil the necessary requirements