JP2018515912A - 半導体構造体及びプロセス - Google Patents
半導体構造体及びプロセス Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 61
- 125000006850 spacer group Chemical group 0.000 claims abstract description 154
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
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- 229910052759 nickel Inorganic materials 0.000 description 1
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 1
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- 229910052763 palladium Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 150000004760 silicates Chemical class 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
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- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
12:絶縁層
14P:半導体フィン
14L、14R:半導体フィン部分
15W:端壁
16L、16R:ゲート構造体
18L、18R:ゲート誘電体部分
20L、20R:ゲート導電体部分
24:誘電体材料ライナ
24P、50P:第1の組のゲートスペーサ
26P:光学的平坦化層部分
28P:反射防止コーティング部分
(26P、28P):パターン付き材料スタック
30:開口部
32P:第2の組のゲートスペーサ
52:犠牲誘電体ライナ
52P:犠牲誘電体ライナ部分
Claims (23)
- 端壁を有し且つ基板から上方に延びた半導体フィン部分と、
前記半導体フィン部分にまたがるゲート構造体と、
前記ゲート構造体の対向する側壁上に位置する第1の組のゲートスペーサと、
前記第1のゲートスペーサの側壁上に位置する第2の組のゲートスペーサであって、前記第2の組のゲートスペーサの片方のゲートスペーサは、前記半導体フィン部分の前記端壁に直接接触する下部分を有する、第2の組のゲートスペーサと、
を含む、半導体構造体。 - 前記ゲート構造体は、機能ゲート構造体である、請求項1に記載の半導体構造体。
- 前記第1の組のゲートスペーサの各ゲートスペーサは、前記半導体フィン部分の最上面上にのみ位置し、前記第1の組のゲートスペーサの片方のゲートスペーサは、前記半導体フィン部分の前記端壁に垂直方向に位置合わせされた外縁を有する、請求項2に記載の半導体構造体。
- 前記第2の組のゲートスペーサのもう片方のゲートスペーサは、前記半導体フィン部分の前記最上面の上にまたがる、請求項3に記載の半導体構造体。
- 前記第1の組のゲートスペーサの各ゲートスペーサは、前記半導体フィン部分の上にまたがる、請求項2に記載の半導体構造体。
- 前記第2の組のゲートスペーサのもう片方のゲートスペーサは、前記半導体フィン部分の別の部分の上にまたがる、請求項5に記載の半導体構造体。
- 前記基板は、絶縁体層である、請求項1に記載の半導体構造体。
- 前記第1の組のゲートスペーサは、前記第2の組のゲートスペーサと同じ誘電体材料を含む、請求項1に記載の半導体構造体。
- 前記第1の組のゲートスペーサは、前記第2の組のゲートスペーサとは異なる誘電体材料を含む、請求項1に記載の半導体構造体。
- 前記第1の組のゲートスペーサ又は前記第2の組のゲートスペーサのうちの少なくとも1つのゲートスペーサがSiBCN又はSiOCN材料で構成された、請求項1に記載の半導体構造体。
- 半導体構造体を形成する方法であって、
半導体フィンにまたがるゲート構造体を形成することと、
前記半導体フィン、及び前記ゲート構造体の少なくとも片方の側壁表面の上に誘電体材料を形成することと、
前記誘電体材料の上に、開口部を有するパターン付き材料スタックを形成することと、
前記半導体フィンを、前記パターン付き材料スタック及び前記開口部内の前記誘電体材料の一部をエッチマスクとして利用して切削して、前記ゲート構造体を含み且つ露出した端壁を有する半導体フィン部分を設けることと、
外側ゲートスペーサを、前記外側ゲートスペーサの片方が前記半導体フィン部分の前記露出した端壁に直接接触する下部分を含むように、形成することと、
を含む、方法。 - 前記開口部の一部分が、前記半導体フィンの上の前記誘電体材料の一部分を露出させる、請求項11に記載の方法。
- 前記半導体フィンを切削する前に、エッチングを行って、前記半導体フィンの上の前記誘電体材料の前記露出した部分を除去する、請求項12に記載の方法。
- 前記誘電体材料は、内側ゲートスペーサを設け、前記内側ゲートスペーサの各々は、前記半導体フィン部分の表面の上にまたがり、前記内側ゲートスペーサの片方は、前記半導体フィン部分の前記端壁に垂直方向に位置合わせされた外縁を有する、請求項11に記載の方法。
- 前記外側ゲートスペーサのもう片方は、前記半導体フィン部分の表面の上にまたがる、請求項14に記載の方法。
- 前記ゲート構造体は、機能ゲート構造体である、請求項11に記載の方法。
- 前記ゲート構造体は、犠牲ゲート構造体であり、前記犠牲ゲート構造体は、前記外側ゲートスペーサを形成した後、機能ゲート構造体で置き換えられる、請求項11に記載の方法。
- 半導体構造体を形成する方法であって、
半導体フィンの一部分にまたがるゲート構造体を形成することと、
前記ゲート構造体の対向する側壁上に、前記半導体フィンの別の部分にまたがる第1の組のゲートスペーサを設けることと、
前記第1の組のゲートスペーサ及び前記ゲート構造体の上に、前記半導体フィンの残りの部分にまたがる犠牲誘電体ライナを形成することと、
開口部を有するパターン付き材料スタックを形成することと、
前記半導体フィンを、前記パターン付き材料スタック、前記開口部内の犠牲誘電体ライナの一部分及び前記第1の組のゲートスペーサの片方のゲートスペーサをエッチマスクとして利用して切削して、前記ゲート構造体を含み且つ露出した端壁を有する半導体フィン部分を設けることと、
横方向エッチングを行って、前記半導体フィン部分の前記露出した端壁を、前記開口部内の前記第1の組のゲートスペーサの前記片方のゲートスペーサの側壁の下に又はこれに位置合わせして後退させることと、
第2の組のゲートスペーサを、前記第2の組のゲートスペーサの片方のゲートスペーサが前記半導体フィン部分の前記露出した端壁に直接接触する下部分を含むように、形成することと、
を含む、方法。 - 前記開口部の一部分が、前記半導体フィンの上の前記犠牲誘電体ライナの一部分を露出させる、請求項18に記載の方法。
- 前記半導体フィンを切削する前に、エッチングを行って、前記半導体フィンの上の前記犠牲誘電体ライナの前記露出した部分を除去する、請求項19に記載の方法。
- 前記第1の組のゲートスペーサの各ゲートスペーサは、前記半導体フィン部分の上にまたがり、前記第2の組のゲートスペーサのもう片方のゲートスペーサは、前記半導体フィン部分の別の部分にまたがる、請求項18に記載の方法。
- 前記ゲート構造体は、機能ゲート構造体である、請求項18に記載の方法。
- 前記ゲート構造体は、犠牲ゲート構造体であり、前記犠牲ゲート構造体は、前記第1及び第2の組のゲートスペーサを形成した後、機能ゲート構造体で置き換えられる、請求項18に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/719,829 | 2015-05-22 | ||
US14/719,829 US9876074B2 (en) | 2015-05-22 | 2015-05-22 | Structure and process to tuck fin tips self-aligned to gates |
PCT/IB2016/052590 WO2016189405A1 (en) | 2015-05-22 | 2016-05-06 | Semiconductor structure and process |
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JP2018515912A true JP2018515912A (ja) | 2018-06-14 |
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JP2017553105A Pending JP2018515912A (ja) | 2015-05-22 | 2016-05-06 | 半導体構造体及びプロセス |
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Country | Link |
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US (3) | US9876074B2 (ja) |
JP (1) | JP2018515912A (ja) |
CN (2) | CN107615461B (ja) |
DE (1) | DE112016001414B4 (ja) |
GB (1) | GB2556224B (ja) |
WO (1) | WO2016189405A1 (ja) |
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JP2021518050A (ja) * | 2018-02-08 | 2021-07-29 | インテル・コーポレーション | 集積トランジスタデバイスのシリサイド構造、および当該シリサイド構造を提供する方法 |
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US10121853B2 (en) | 2018-11-06 |
CN107615461B (zh) | 2021-02-05 |
CN112786705A (zh) | 2021-05-11 |
US20160343861A1 (en) | 2016-11-24 |
GB2556224A (en) | 2018-05-23 |
GB201720310D0 (en) | 2018-01-17 |
GB2556224B (en) | 2019-10-30 |
DE112016001414T5 (de) | 2017-12-14 |
US20180061941A1 (en) | 2018-03-01 |
US10121852B2 (en) | 2018-11-06 |
US20180061942A1 (en) | 2018-03-01 |
DE112016001414B4 (de) | 2023-12-14 |
CN107615461A (zh) | 2018-01-19 |
WO2016189405A1 (en) | 2016-12-01 |
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