JP2018117001A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device in which an upper end part of a cavity in a trench is not opened.SOLUTION: When filling an insulation film into a trench, a cavity 10 remains in the trench and a first insulation film 11 is filled, and after that, the cavity is opened, and sequentially, a second insulation film 12 is filled. According to such a structure, a position of the upper end part of the cavity formed by filling the second insulation film can be moved to a position deeper than a position of an upper end part of the cavity formed by filling the first insulation film.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a trench for isolation.

  Conventionally, an insulating isolation trench is used to electrically isolate a plurality of semiconductor elements formed on a semiconductor substrate. Insulating isolation trenches are formed in a semiconductor substrate, and an insulating film is embedded in the trench. In a semiconductor device provided with such an isolation trench, crystal defects are generated due to the stress caused by the difference in thermal expansion coefficient between the insulating film and the semiconductor substrate, and the characteristics of the semiconductor device are degraded. For this reason, a method has been proposed in which a cavity is left in the trench to relieve stress stress (for example, cited document 1).

  A semiconductor device including an insulating isolation trench having a cavity can be generally formed by a manufacturing process shown in FIG. First, a silicon oxide film 2 having a thickness of about 0.01 μm is formed on the main surface of the semiconductor substrate 1 by a thermal oxidation method, and a silicon nitride film having a thickness of about 0.1 μm is formed on the silicon oxide film 2 by a CVD method. 3 is formed. Further, a silicon oxide film 4 having a thickness of about 0.8 μm is formed on the silicon nitride film 3 by the CVD method. Next, the silicon oxide film 2, the silicon nitride film 3, and the silicon oxide film 4 are patterned to open a region where a trench is to be formed (FIG. 3a).

  Thereafter, the exposed semiconductor substrate 1 is removed by etching, thereby forming a trench 5 having a width of about 1 μm and a depth of about 12 μm (FIG. 3b).

  A silicon oxide film 6 having a thickness of about 0.05 μm is formed on the inner wall surface of the trench 5 by thermal oxidation, and a punch-through stop region 7 is formed at the bottom of the trench 5 by ion implantation (FIG. 3c).

  The silicon oxide film 4 on the silicon nitride film 3 and the silicon oxide film 6 in the trench 5 are temporarily removed, and a silicon oxide film 8 having a thickness of about 0.05 μm is formed again on the inner wall surface of the trench 5 by thermal oxidation ( FIG. 3d).

  Thereafter, an insulating film 9 made of a TEOS film is formed on the entire surface of the semiconductor substrate 1 by a CVD method and filled in the trench 5. At this time, the insulating film 9 is sequentially deposited on the silicon nitride film 3 and in the trench 5 to fill the trench 5, but the insulating film 9 deposited in the opening of the trench 5 gradually moves toward the center of the trench 5. It begins to protrude and the opening narrows. As a result, as shown in FIG. 3 (e), a cavity 10 surrounded by an insulating film 9 is formed in the trench 5. At this time, the upper end portion of the cavity 10 is positioned in the vicinity of the surface of the semiconductor substrate 1 as shown in FIG.

  Thereafter, when etching back is performed for planarization, the insulating film 9 remaining on the cavity 10 is also etched, resulting in a structure in which the insulating film 9 remains slightly as shown in FIG. Here, since the etch-back process is performed under over-etching conditions, the cavity 10 may open as shown in FIG. Further, in the planarization process, even if the insulating film 9 remains on the cavity 10 as shown in FIG. 3F, the cavity 10 may be opened by an etching process or the like performed thereafter.

JP-A-3-229443

  As described above, in the conventional method for manufacturing a semiconductor device, the upper end portion of the cavity 10 is located in the vicinity of the surface of the semiconductor substrate, so that the insulating film 9 remaining on the upper end portion of the cavity 10 is eliminated in the planarization and the subsequent etching process. There was a problem that 10 opened. If the opening is formed, a problem occurs in the subsequent manufacturing process.

  For example, in the step of applying a resist to the surface of the semiconductor substrate 1, the resist penetrates deep into the cavity 10 and cannot be removed in a normal resist removal step. The resist left in the cavity 10 is carbonized by a subsequent heat treatment, which causes a decrease in product yield and deterioration in characteristics of the semiconductor device. An object of the present invention is to provide a method for manufacturing a semiconductor device that eliminates such problems and does not open the upper end of a cavity in a trench.

  In order to achieve the above object, a manufacturing method of a semiconductor device according to claim 1 of the present application is a method of manufacturing a semiconductor device including a step of forming a trench in a semiconductor substrate and filling the trench with an insulating film. Forming the first insulating film in the trench, leaving a first cavity surrounded by a first insulating film and having an upper end at a first depth from the surface of the semiconductor substrate. A step of removing a part of the first insulating film in the trench to open the first cavity, and a second insulating film is filled in the trench, and the second insulating film And forming a second cavity surrounded by the first insulating film and having an upper end at a second depth deeper than the first depth.

  The invention according to claim 2 of the present application includes the step of removing the second insulating film in the trench to a third depth shallower than the second depth in the method of manufacturing a semiconductor device according to claim 1. It is characterized by.

  According to the present invention, since the upper end of the cavity can be surely formed at a deeper position than the surface of the semiconductor substrate, the cavity 10 can be formed even if the insulating film in the trench 5 is etched by a process such as planarization or etching. Does not open, and deterioration of product yield and deterioration of the characteristics of the semiconductor device can be suppressed.

  Further, since the cavity 10 is left in the trench 5, stress caused by a difference in thermal expansion coefficient between the insulating film filling the trench 5 and the semiconductor substrate 1 can be reduced.

  Furthermore, by reducing the thickness of the insulating film remaining on the cavity 10, it is possible to relieve stress caused by the difference in thermal expansion coefficient between the insulating film filling the trench 5 and the semiconductor substrate 1.

  When the surface of the insulating film embedded in the trench 5 has a shape lower than the semiconductor substrate 1, there is an advantage that stress concentration on the edge portion generated from both sides of the surface of the semiconductor substrate 1 and the side surface of the trench 5 is reduced.

  Since the manufacturing method of the present invention is constituted only by a normal manufacturing process of a semiconductor device, there is an advantage that a semiconductor device can be formed with a high yield.

It is a figure explaining the Example of this invention. It is a figure explaining the Example of this invention. It is a figure explaining the conventional Example. It is a figure explaining the conventional Example.

  In the present invention, when an insulating film is filled in a trench, the first insulating film is filled leaving a cavity in the trench, the cavity is opened, and then the second insulating film is filled again. With this configuration, the position of the upper end of the cavity formed by filling the second insulating film is moved deeper than the position of the upper end of the cavity formed by filling the first insulating film. It becomes possible. Hereinafter, examples will be described in detail.

  A first embodiment of the present invention will be described. First, as in the conventional example described above, a silicon oxide film 2 having a thickness of about 0.01 μm is formed on the main surface of the semiconductor substrate 1 by a thermal oxidation method, and the thickness is formed on the silicon oxide film 2 by a CVD method. A silicon nitride film 3 of about 0.1 μm is formed. Further, a silicon oxide film 4 having a thickness of about 0.8 μm is formed on the silicon nitride film 3 by the CVD method. Next, the silicon oxide film 2, the silicon nitride film 3, and the silicon oxide film 4 are patterned to open a region where a trench is to be formed (FIG. 3a).

  Thereafter, the exposed semiconductor substrate 1 is removed by etching, thereby forming a trench 5 having a width of about 1 μm and a depth of about 12 μm (FIG. 3b).

  A silicon oxide film 6 having a thickness of about 0.05 μm is formed on the inner wall surface of the trench 5 by thermal oxidation, and a punch-through stop region 7 is formed at the bottom of the trench 5 by ion implantation (FIG. 3c).

  The silicon oxide film 4 on the silicon nitride film 3 and the silicon oxide film 6 in the trench 5 are temporarily removed, and a silicon oxide film 8 having a thickness of about 0.05 μm is formed again on the inner wall surface of the trench 5 by thermal oxidation ( FIG. 3d).

  Thereafter, as shown in FIG. 1A, a first insulating film 11 made of a TEOS film is formed on the entire surface of the semiconductor substrate 1 by a CVD method and filled in the trench 5. At this time, the first insulating film 11 is sequentially deposited on the silicon nitride film 3 and in the trench 5 and is filled in the trench 5, but the first insulating film 11 deposited in the opening of the trench 5 is the trench. 5 gradually protrudes toward the center of the opening 5, and the opening narrows. As a result, the cavity 10 is formed in the trench 5. Here, the first insulating film 11 is slightly left at the upper end of the cavity 10. That is, the position A of the upper end portion of the cavity 10 is arranged in the vicinity of the surface of the semiconductor substrate 1. The above steps are the same as those of the conventional example described above, and the insulating film 9 corresponds to the first insulating film 11.

  Next, in the present invention, when etching back for planarization, the first insulating film 11 on the cavity 10 is etched until the cavity 10 is opened. As shown in FIG. 1 (a), the cavity 10 has a wide central portion and a narrower width at the upper end portion. Therefore, the etching of the first insulating film 10 is preferably performed not only at the opening of the narrow upper end portion of the cavity 10 but also until the wide region of the central portion of the cavity 10 is exposed (FIG. 1b). .

  Thereafter, a second insulating film 12 made of a TEOS film is formed by a CVD method and filled in the trench 5. At this time, the second insulating film 12 enters and accumulates in the opening, narrows the narrow opening of the cavity 10, and fills the trench 5 (FIG. 1c).

  As a result, the position B of the upper end portion of the cavity 10 is arranged at a position deeper than the position A of the upper end portion of the cavity 10 formed by the deposition of the first insulating film 11 previously.

  After that, even if etch back is performed for planarization, the second insulating film 12 is thickly deposited on the cavity 10, and the cavity 10 does not open (FIG. 1d). In the subsequent etching process, the cavity 10 does not open.

  Note that the position of the upper end portion of the opening 10 is moved to a deeper position by increasing the etching amount of the first insulating film 11 when the opening is formed by etching the first insulating film 11 (FIG. 1b). It becomes possible. In that case, when the second insulating film 12 is filled in the trench, the depth may be set so that a new opening surrounded by the second insulating film 12 is not formed.

  Next, a second embodiment of the present invention will be described. In the first embodiment, when the first insulating film 11 and the second insulating film 12 are filled in the trench 5 and flattened, overetching is performed in consideration of etching variation and the like. At that time, the first insulating film 11 or the second insulating film 12 in the trench 5 is slightly etched. In this case, as shown in FIG. 1D, the first insulating film 11 and the second insulating film 12 remaining on the upper end portion of the cavity 10 remain thick.

  Leaving the thick first insulating film 11 and the second insulating film 12 may cause stress due to a difference in thermal expansion coefficient between them and the semiconductor substrate 1. In particular, in the present invention, since the volume of the opening 10 for relaxing stress is made smaller than that of the conventional example, the effect of stress relaxation by the cavity 10 is reduced. Therefore, as shown in FIG. 2, stress relaxation can be achieved by thinning the first insulating film 11 and the second insulating film 12 on the cavity 10.

  Since the process of thinning the first insulating film 11 and the second insulating film 12 is allowed even if the remaining film thickness varies to some extent, the second film having a sufficient thickness on the upper end portion of the cavity 10 is allowed. If the conditions are set so that the insulating film 12 remains, there is no inconvenience that the cavity 10 opens.

1: semiconductor substrate, 2: silicon oxide film, 3: silicon nitride film, 4: silicon oxide film, 5: trench, 6: silicon oxide film, 7: punch-through stop region, 8: silicon oxide film, 9: insulating film 10: cavity, 11: first insulating film, 12: second insulating film

Claims (2)

In a manufacturing method of a semiconductor device including a step of forming a trench in a semiconductor substrate and filling the trench with an insulating film,
Forming the trench;
Filling the first insulating film in the trench, leaving a first cavity surrounded by a first insulating film and having an upper end at a first depth from the semiconductor substrate surface;
Removing a portion of the first insulating film in the trench and opening the first cavity;
A second insulating film is filled in the trench, and is surrounded by the second insulating film and the first insulating film, and has an upper end at a second depth deeper than the first depth. Forming a cavity, and a method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, comprising: removing the second insulating film in the trench to a third depth shallower than the second depth.

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