KR20080089998A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
KR20080089998A
KR20080089998A KR1020070032912A KR20070032912A KR20080089998A KR 20080089998 A KR20080089998 A KR 20080089998A KR 1020070032912 A KR1020070032912 A KR 1020070032912A KR 20070032912 A KR20070032912 A KR 20070032912A KR 20080089998 A KR20080089998 A KR 20080089998A
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KR
South Korea
Prior art keywords
spacer
forming
recess
semiconductor device
film
Prior art date
Application number
KR1020070032912A
Other languages
Korean (ko)
Inventor
강대인
Original Assignee
주식회사 하이닉스반도체
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Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020070032912A priority Critical patent/KR20080089998A/en
Publication of KR20080089998A publication Critical patent/KR20080089998A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers

Abstract

A method for manufacturing a semiconductor device is provided to prevent a SAC fail from being generated between a silicon epitaxial growth(SEG) membrane and gate patterns by growing the SEG membrane between the gate patterns after forming a first spacer and a second spacer on sidewalls of the gate patterns, to increase a cell area and to improve an interfacial property of the SEG membrane. Also, this method is provided to improve a cell resistance property and an element property by securing the area of a landing plug contact. A method for manufacturing a semiconductor device, comprises the following steps of: forming a gate pattern on a semiconductor substrate(200); forming a first spacer on a sidewall of the gate pattern; forming a first recess(230) by etching the semiconductor substrate on which the first spacer is exposed through a mask; forming a second spacer(240a) on a sidewall of the gate pattern where the first spacer is formed; forming a second recess to define a landing plug contact area by further etching the first recess exposed from the second spacer through a mask; and forming a SEG membrane(250) on the landing plug contact area by growing a silicone membrane of the second recess.

Description

Method for manufacturing a semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

1A and 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

2A to 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

<Description of Symbols for Main Parts of Drawings>

100, 200: semiconductor substrate 105, 205: device isolation film

110, 210: gate polysilicon layer 115, 215: gate metal layer

120, 220: gate hard mask layer 125, 225: gate pattern

130, 230: spacer 150, 250: SEG film

237: first recess 240: second spacer layer

240a: second spacer 245: second recess

255: spacer for cell

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, comprising: forming a gate pattern on an upper surface of a semiconductor substrate, forming a first spacer on a sidewall of the gate pattern, and exposing the first spacer with a mask. Etching to form a first recess, forming a second spacer on the sidewall of the gate pattern provided with the first spacer, and etching the first recess further using the second spacer as a mask. Forming a second recess defining a landing plug contact region, and growing a silicon layer of the second recess to form a SEG film in the landing plug contact region, wherein the SEG film and the gate It prevents SAC failing between patterns, increases cell area, and improves interfacial properties of the SEG film.

In addition, a technique of improving the characteristics of the device by improving the area of the landing plug contact to improve the cell resistance characteristics is disclosed.

The landing plug contact of a semiconductor device is formed by filling a landing plug contact hole with a single layer of a polysilicon layer or an SPE film. However, as the device becomes highly integrated, a silicon epitaxial growth (SEG) film is formed by single crystal growth so that a natural oxide film does not exist. The cell resistance characteristics were improved by obtaining.

However, in the SEG film forming process, the throw-put is reduced and a single layer of the SEG film causes a problem in forming a landing plug contact. Thus, a polysilicon layer or a solid phase epitaxy having good throw foot characteristics is obtained. A film is formed on the SEG film to form a landing plug contact.

1A and 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

Referring to FIG. 1A, a gate recess (not shown) is formed by etching a semiconductor substrate 100 including an isolation layer 105 to a predetermined depth, and a gate oxide layer having a predetermined thickness inside the gate recess (not shown). (Not shown) is formed.

Next, a stacked structure of the gate polysilicon layer 110, the gate metal layer 115, and the gate hard mask layer 120 is formed on the entire surface including the recess (not shown), and then the patterned laminate structure is patterned. The gate pattern 125 is formed.

Next, nitride film spacers 130 are formed on both sides of the gate pattern 125.

Referring to FIG. 1B, the semiconductor substrate 100 between the gate patterns 125 is etched to a predetermined depth by using the gate pattern 125 including the spacers 130 as an etching mask.

Next, the silicon layer of the etched semiconductor substrate 100 is grown to grow the SEG film 150.

Next, a cleaning process is performed to improve the interfacial properties with the polysilicon layer or the SPE film formed in a subsequent process.

In this case, when the cleaning process is performed, the spacer 130 on the sidewall of the gate pattern 125 may be damaged, and the gate polysilicon layer 110 and the SEG film 150 may come into contact with each other, causing a SAC fail.

In the above-described method of manufacturing a semiconductor device according to the related art, while the spacers of the gate pattern sidewalls are damaged, the SEG film used as the landing plug contact and the gate polysilicon layer of the gate pattern are contacted to generate a SAC fail. The problem occurs that the characteristics of.

In order to solve the above problem, by forming a first spacer and a second spacer on the sidewall of the gate pattern, by growing a SEG film between the gate pattern, to prevent the SAC failure occurring between the SEG film and the gate pattern, the cell area Increase the interface properties of the SEG film.

In addition, an object of the present invention is to provide a method for manufacturing a semiconductor device in which the area of a landing plug contact can be secured, thereby improving cell resistance characteristics and improving device characteristics.

Method for manufacturing a semiconductor device according to the present invention

Forming a gate pattern on the semiconductor substrate;

Forming a first spacer on sidewalls of the gate pattern;

Etching the semiconductor substrate exposed using the first spacer as a mask to form a first recess;

Forming a second spacer on sidewalls of the gate pattern provided with the first spacer;

Further etching the first recess using the second spacer as a mask to form a second recess defining a landing plug contact region;

Growing a silicon layer of the second recess to form an SEG film in the landing plug contact region;

The first spacer and the second spacer is a nitride film,

The thickness of the first spacer is 50 to 200Å,

The depth of the first recess is 50 to 150 microns;

Forming a capping oxide layer after performing the step of forming the second spacer;

The capping oxide film is a USG oxide film,

The thickness of the second spacer is 30 to 200Å,

The depth of the second recess is 50 to 400 microns;

Performing a cleaning process before forming the SEG film;

The cleaning process is performed using a 300: 1 BOE solution,

The cleaning process is carried out using a 50: 1 HF solution,

The thickness of the SEG film is 300 to 400Å,

After the forming of the SEG film is characterized in that it further comprises the step of forming a polysilicon layer or SPE film.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

2A to 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

Referring to FIG. 2A, a gate recess (not shown) is formed by etching the active region of the semiconductor substrate 200 provided with the device isolation layer 205 to a predetermined depth.

Next, a gate oxide layer (not shown) is formed inside the gate recess (not shown), and then the polysilicon layer 210, the gate metal layer 215, and the entire upper portion of the gate recess (not shown) are formed. A stack structure of the gate hard mask layer 220 is formed.

Thereafter, the stacked structure is etched to form a gate pattern 225 and then a selective oxidation process is performed to form oxide films (not shown) on both sides of the polysilicon layer 210 of the gate pattern 225.

In addition, a nitride film having a predetermined thickness is formed on the entire surface including the gate pattern 225, and a first spacer 230 is formed on both sides of the gate pattern 225 to expose the semiconductor substrate 200 by performing an entire surface etching process. do.

Here, the first spacer 230 is a nitride film, preferably formed with a thickness of 50 to 200 GPa.

Referring to FIG. 2B, the first recess 237 is formed by etching the semiconductor substrate 200 exposed by using the first spacer 230 as a mask to a predetermined depth.

Here, the depth of the first recess 237 is preferably 50 to 150 kPa.

Referring to FIG. 2C, a second spacer layer 240 having a predetermined thickness and a capping oxide layer (not shown) are formed on the entire surface including the gate pattern 225 having the first spacer 230.

Next, a cleaning process is performed, and the capping oxide layer (not shown) on the sidewall of the gate pattern 225 is removed by the cleaning process.

Next, an entire surface etching process is performed to form second spacers 240a through which the first recesses 237 are exposed.

Here, the second spacer 240a is preferably formed of a nitride film of 30 to 200 GPa, and the capping oxide film (not shown) is preferably an undoped silicate glass (USG) oxide of 300 to 1000 GPa.

Referring to FIG. 2D, the first recess 237 is further etched using the second spacer 240a as an etch mask to form a second recess 245 in the landing plug contact region.

Here, the second recess 245 may be formed to have a depth of 50 to 400 mm from the first recess 237.

Referring to FIG. 2E, a LET (Light Etch Treatment) process and a primary cleaning process are sequentially performed on the resultant.

Here, the primary cleaning process is preferably carried out using a BOE solution or HF solution.

In this case, the BOE (Buffer Oxide Etch) solution is preferably a ratio of DI water and HF is 250 ~ 350: 1, the HF solution is preferably a ratio of DI water and F is 45 ~ 55: 1.

Next, a silicon layer of the exposed semiconductor substrate 200 is grown to form a silicon epitaxial growth (SEG) film 250 in the landing plug contact region.

Here, the SEG film 250 is preferably formed to a thickness of 300 to 400 kPa.

At this time, by forming the first spacer 230 and the second spacer 240 over the secondary, the SEG film 250 and the gate pattern 225 can be in contact with each other to prevent the electrical short. .

Referring to FIG. 2F, a nitride film having a predetermined thickness is formed on the resultant, and a front surface etching process is performed to form a cell spacer 255.

Next, a second cleaning process is performed, and a landing plug contact (not shown) is formed by forming a polysilicon layer or a solid phase epitaxy (SPE) film over the entire resultant.

In this case, the secondary cleaning process is preferably performed to improve the interface characteristics between the SEG film 250 and the polysilicon layer or SPE film formed subsequently.

The method of manufacturing a semiconductor device according to the present invention forms a first spacer and a second spacer on a sidewall of a gate pattern, and then grows an SEG film between the gate patterns, thereby preventing SAC failing between the SEG film and the gate pattern. The cell area is increased, and the interfacial properties of the SEG film are improved.

In addition, it is possible to secure the area of the landing plug contact to improve the cell resistance characteristics, thereby improving the characteristics of the device.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as being in scope.

Claims (13)

Forming a gate pattern on the semiconductor substrate; Forming a first spacer on sidewalls of the gate pattern; Etching the semiconductor substrate exposed with the first spacer as a mask to form a first recess; Forming a second spacer on sidewalls of the gate pattern provided with the first spacer; Further etching the first recess with the second spacer as a mask to form a second recess defining a landing plug contact region; And Growing a silicon layer of the second recess to form an SEG film in the landing plug contact region Method of manufacturing a semiconductor device comprising a. The method of claim 1, The first spacer and the second spacer is a manufacturing method of a semiconductor device, characterized in that the nitride film. The method of claim 1, The thickness of the first spacer is a method of manufacturing a semiconductor device, characterized in that 50 to 200Å. The method of claim 1, The first recess has a depth of 50 to 150 microns. The method of claim 1, And forming a capping oxide layer after performing the step of forming the second spacer. The method of claim 5, wherein The capping oxide film is a manufacturing method of a semiconductor device, characterized in that the USG oxide film. The method of claim 1, The thickness of the second spacer is a manufacturing method of a semiconductor device, characterized in that 30 to 200Å. The method of claim 1, And the depth of the second recess is 50 to 400 microns. The method of claim 1, And performing a cleaning process before forming the SEG film. The method of claim 9, The cleaning process is a method of manufacturing a semiconductor device, characterized in that performed using a 300: 1 BOE solution. The method of claim 9, The cleaning process is a method of manufacturing a semiconductor device, characterized in that carried out using a 50: 1 HF solution. The method of claim 1, The SEG film has a thickness of 300 to 400 GPa. The method of claim 1, And forming a polysilicon layer or an SPE film after the forming of the SEG film.
KR1020070032912A 2007-04-03 2007-04-03 Method for manufacturing semiconductor device KR20080089998A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8835252B2 (en) 2012-06-21 2014-09-16 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices having increased areas of storage contacts
US9570554B2 (en) 2014-04-04 2017-02-14 International Business Machines Corporation Robust gate spacer for semiconductor devices

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8835252B2 (en) 2012-06-21 2014-09-16 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices having increased areas of storage contacts
US9570554B2 (en) 2014-04-04 2017-02-14 International Business Machines Corporation Robust gate spacer for semiconductor devices
US9929255B2 (en) 2014-04-04 2018-03-27 International Business Machines Corporation Robust gate spacer for semiconductor devices

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