KR20080089998A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
- Publication number
- KR20080089998A KR20080089998A KR1020070032912A KR20070032912A KR20080089998A KR 20080089998 A KR20080089998 A KR 20080089998A KR 1020070032912 A KR1020070032912 A KR 1020070032912A KR 20070032912 A KR20070032912 A KR 20070032912A KR 20080089998 A KR20080089998 A KR 20080089998A
- Authority
- KR
- South Korea
- Prior art keywords
- spacer
- forming
- recess
- semiconductor device
- film
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 42
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 125000006850 spacer group Chemical group 0.000 claims abstract description 55
- 238000005530 etching Methods 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 8
- 239000010703 silicon Substances 0.000 claims abstract description 8
- 238000004140 cleaning Methods 0.000 claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 13
- 150000004767 nitrides Chemical class 0.000 claims description 7
- 239000012528 membrane Substances 0.000 abstract 5
- 229920001296 polysiloxane Polymers 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 31
- 238000000348 solid-phase epitaxy Methods 0.000 description 7
- 238000002955 isolation Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Memories (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
1A and 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
2A to 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
<Description of Symbols for Main Parts of Drawings>
100, 200:
110, 210:
120, 220: gate
130, 230:
237: first recess 240: second spacer layer
240a: second spacer 245: second recess
255: spacer for cell
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, comprising: forming a gate pattern on an upper surface of a semiconductor substrate, forming a first spacer on a sidewall of the gate pattern, and exposing the first spacer with a mask. Etching to form a first recess, forming a second spacer on the sidewall of the gate pattern provided with the first spacer, and etching the first recess further using the second spacer as a mask. Forming a second recess defining a landing plug contact region, and growing a silicon layer of the second recess to form a SEG film in the landing plug contact region, wherein the SEG film and the gate It prevents SAC failing between patterns, increases cell area, and improves interfacial properties of the SEG film.
In addition, a technique of improving the characteristics of the device by improving the area of the landing plug contact to improve the cell resistance characteristics is disclosed.
The landing plug contact of a semiconductor device is formed by filling a landing plug contact hole with a single layer of a polysilicon layer or an SPE film. However, as the device becomes highly integrated, a silicon epitaxial growth (SEG) film is formed by single crystal growth so that a natural oxide film does not exist. The cell resistance characteristics were improved by obtaining.
However, in the SEG film forming process, the throw-put is reduced and a single layer of the SEG film causes a problem in forming a landing plug contact. Thus, a polysilicon layer or a solid phase epitaxy having good throw foot characteristics is obtained. A film is formed on the SEG film to form a landing plug contact.
1A and 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
Referring to FIG. 1A, a gate recess (not shown) is formed by etching a
Next, a stacked structure of the
Next,
Referring to FIG. 1B, the
Next, the silicon layer of the
Next, a cleaning process is performed to improve the interfacial properties with the polysilicon layer or the SPE film formed in a subsequent process.
In this case, when the cleaning process is performed, the
In the above-described method of manufacturing a semiconductor device according to the related art, while the spacers of the gate pattern sidewalls are damaged, the SEG film used as the landing plug contact and the gate polysilicon layer of the gate pattern are contacted to generate a SAC fail. The problem occurs that the characteristics of.
In order to solve the above problem, by forming a first spacer and a second spacer on the sidewall of the gate pattern, by growing a SEG film between the gate pattern, to prevent the SAC failure occurring between the SEG film and the gate pattern, the cell area Increase the interface properties of the SEG film.
In addition, an object of the present invention is to provide a method for manufacturing a semiconductor device in which the area of a landing plug contact can be secured, thereby improving cell resistance characteristics and improving device characteristics.
Method for manufacturing a semiconductor device according to the present invention
Forming a gate pattern on the semiconductor substrate;
Forming a first spacer on sidewalls of the gate pattern;
Etching the semiconductor substrate exposed using the first spacer as a mask to form a first recess;
Forming a second spacer on sidewalls of the gate pattern provided with the first spacer;
Further etching the first recess using the second spacer as a mask to form a second recess defining a landing plug contact region;
Growing a silicon layer of the second recess to form an SEG film in the landing plug contact region;
The first spacer and the second spacer is a nitride film,
The thickness of the first spacer is 50 to 200Å,
The depth of the first recess is 50 to 150 microns;
Forming a capping oxide layer after performing the step of forming the second spacer;
The capping oxide film is a USG oxide film,
The thickness of the second spacer is 30 to 200Å,
The depth of the second recess is 50 to 400 microns;
Performing a cleaning process before forming the SEG film;
The cleaning process is performed using a 300: 1 BOE solution,
The cleaning process is carried out using a 50: 1 HF solution,
The thickness of the SEG film is 300 to 400Å,
After the forming of the SEG film is characterized in that it further comprises the step of forming a polysilicon layer or SPE film.
Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.
2A to 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
Referring to FIG. 2A, a gate recess (not shown) is formed by etching the active region of the
Next, a gate oxide layer (not shown) is formed inside the gate recess (not shown), and then the
Thereafter, the stacked structure is etched to form a
In addition, a nitride film having a predetermined thickness is formed on the entire surface including the
Here, the
Referring to FIG. 2B, the
Here, the depth of the
Referring to FIG. 2C, a
Next, a cleaning process is performed, and the capping oxide layer (not shown) on the sidewall of the
Next, an entire surface etching process is performed to form
Here, the
Referring to FIG. 2D, the
Here, the
Referring to FIG. 2E, a LET (Light Etch Treatment) process and a primary cleaning process are sequentially performed on the resultant.
Here, the primary cleaning process is preferably carried out using a BOE solution or HF solution.
In this case, the BOE (Buffer Oxide Etch) solution is preferably a ratio of DI water and HF is 250 ~ 350: 1, the HF solution is preferably a ratio of DI water and F is 45 ~ 55: 1.
Next, a silicon layer of the exposed
Here, the
At this time, by forming the
Referring to FIG. 2F, a nitride film having a predetermined thickness is formed on the resultant, and a front surface etching process is performed to form a
Next, a second cleaning process is performed, and a landing plug contact (not shown) is formed by forming a polysilicon layer or a solid phase epitaxy (SPE) film over the entire resultant.
In this case, the secondary cleaning process is preferably performed to improve the interface characteristics between the
The method of manufacturing a semiconductor device according to the present invention forms a first spacer and a second spacer on a sidewall of a gate pattern, and then grows an SEG film between the gate patterns, thereby preventing SAC failing between the SEG film and the gate pattern. The cell area is increased, and the interfacial properties of the SEG film are improved.
In addition, it is possible to secure the area of the landing plug contact to improve the cell resistance characteristics, thereby improving the characteristics of the device.
In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as being in scope.
Claims (13)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020070032912A KR20080089998A (en) | 2007-04-03 | 2007-04-03 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020070032912A KR20080089998A (en) | 2007-04-03 | 2007-04-03 | Method for manufacturing semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
KR20080089998A true KR20080089998A (en) | 2008-10-08 |
Family
ID=40151401
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020070032912A KR20080089998A (en) | 2007-04-03 | 2007-04-03 | Method for manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR20080089998A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8835252B2 (en) | 2012-06-21 | 2014-09-16 | Samsung Electronics Co., Ltd. | Methods of fabricating semiconductor devices having increased areas of storage contacts |
US9570554B2 (en) | 2014-04-04 | 2017-02-14 | International Business Machines Corporation | Robust gate spacer for semiconductor devices |
-
2007
- 2007-04-03 KR KR1020070032912A patent/KR20080089998A/en not_active Application Discontinuation
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8835252B2 (en) | 2012-06-21 | 2014-09-16 | Samsung Electronics Co., Ltd. | Methods of fabricating semiconductor devices having increased areas of storage contacts |
US9570554B2 (en) | 2014-04-04 | 2017-02-14 | International Business Machines Corporation | Robust gate spacer for semiconductor devices |
US9929255B2 (en) | 2014-04-04 | 2018-03-27 | International Business Machines Corporation | Robust gate spacer for semiconductor devices |
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