KR20020080912A - Method of forming trench type isolation layer in semiconductor device - Google Patents
Method of forming trench type isolation layer in semiconductor device Download PDFInfo
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- KR20020080912A KR20020080912A KR1020010020774A KR20010020774A KR20020080912A KR 20020080912 A KR20020080912 A KR 20020080912A KR 1020010020774 A KR1020010020774 A KR 1020010020774A KR 20010020774 A KR20010020774 A KR 20010020774A KR 20020080912 A KR20020080912 A KR 20020080912A
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- 238000002955 isolation Methods 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 title claims abstract description 26
- 239000004065 semiconductor Substances 0.000 title claims abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 33
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 33
- 239000010703 silicon Substances 0.000 claims abstract description 33
- 238000005530 etching Methods 0.000 claims abstract description 27
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 22
- 229920005591 polysilicon Polymers 0.000 claims abstract description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000005498 polishing Methods 0.000 claims abstract 2
- 239000000126 substance Substances 0.000 claims abstract 2
- 239000007789 gas Substances 0.000 claims description 10
- 238000001039 wet etching Methods 0.000 claims description 7
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 3
- 229910000041 hydrogen chloride Inorganic materials 0.000 claims description 3
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 claims description 3
- NLXLAEXVIDQMFP-UHFFFAOYSA-N Ammonium chloride Substances [NH4+].[Cl-] NLXLAEXVIDQMFP-UHFFFAOYSA-N 0.000 claims description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 2
- 235000011114 ammonium hydroxide Nutrition 0.000 claims description 2
- 239000000460 chlorine Substances 0.000 claims description 2
- 229910052801 chlorine Inorganic materials 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 5
- 238000000137 annealing Methods 0.000 abstract description 2
- 239000013078 crystal Substances 0.000 description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 230000002265 prevention Effects 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910019142 PO4 Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- NBIIXXVUZAFLBC-UHFFFAOYSA-K phosphate Chemical compound [O-]P([O-])([O-])=O NBIIXXVUZAFLBC-UHFFFAOYSA-K 0.000 description 1
- 239000010452 phosphate Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/763—Polycrystalline semiconductor regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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Abstract
Description
본 발명은 트렌치 소자 분리형 반도체 장치의 형성 방법에 관한 것으로, 보다 상세하게는 트렌치 소자 분리형 반도체 장치에서 트랜치 소자 분리막 내부에 실리콘을 채운 형태의 트렌치형 소자 분리막 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a trench isolation device, and more particularly, to a method of forming a trench isolation device in which silicon is filled in a trench isolation film in a trench isolation device.
트렌치 소자 분리는 종래의 LOCOS 계열의 소자 분리 방법에 비해 버즈 빅의 문제를 해결할 수 있으므로 근래에 고집적 반도체 장치에서 많이 선호되고 있다. 그러나, 소자 집적도가 높아지면서 트렌치 형성에 있어서 폭은 좁아지고, 소자 분리 기능을 위해 상대적으로 트렌치 깊어지므로 트렌치의 가로세로비는 점증하고 있다. 이런 트렌치에 소자 분리막을 공극(void)없이 채우기 위해 여러가지 방법이 모색되고 있다.Trench device isolation can solve the problem of Buzz Big, compared to the conventional LOCOS-based device isolation method, and thus has been widely used in highly integrated semiconductor devices. However, as the degree of device integration increases, the width of the trench becomes narrower, and the trench becomes relatively deep for the device isolation function. Therefore, the aspect ratio of the trench increases. Various methods have been sought to fill these trenches without voids.
미국특허번호 제 5,236,863 호에는 공극 없는 트렌치 소자 분리 방법의 한 예가 나타난다. 이 기술에 따르면 먼저, 통상의 트렌치 소자 분리 방법과 같이 기판에 식각 방지막 패턴을 형성하고 기판을 식각하여 기판에 트렌치를 형성한다. 트렌치 내벽에 열산화막과 질화막 라이너를 형성한다. 전면 이방성 식각을 통해 열산화막과 질화막 라이너로 이루어진 스페이서를 트렌치 측벽에 형성하고, 트렌치 저면에 실리콘 기판을 드러낸다. 선택적 결정 성장(SEG: Selective Epytaxial Growth)을 이용하여 트렌치 저면의 실리콘을 성장시켜 트렌치의 상당 부분을 채운다. 그리고, 잔여 트렌치에 실리콘 산화막을 CVD로 채운다.U. S. Patent No. 5,236, 863 shows an example of a method for isolation of trench elements without voids. According to this technology, first, as in the conventional trench isolation method, an etch stop layer pattern is formed on a substrate and the substrate is etched to form a trench in the substrate. A thermal oxide film and a nitride film liner are formed on the inner wall of the trench. Through anisotropic etching, spacers comprising a thermal oxide film and a nitride film liner are formed on the trench sidewalls, and the silicon substrate is exposed on the trench bottom. Selective Epytaxial Growth (SEG) is used to grow the silicon at the bottom of the trench to fill a significant portion of the trench. Then, the silicon oxide film is filled in the remaining trenches by CVD.
이런 구성에 따르면, 트렌치 측벽에 스페이서를 형성하는 열산화막이나 실리콘 질화막 라이너의 두께를 조절하고, 트렌치 깊이를 충분히 하여 스페이서의 평성 깊이를 조절하면, 소자 분리를 충분히 할 수 있는 것으로 생각된다.According to this configuration, it is considered that device isolation can be sufficiently achieved by adjusting the thickness of the thermal oxide film or silicon nitride film liner forming the spacers on the trench sidewalls, and adjusting the depth of the spacers with sufficient trench depth.
그런데, 이런 기술에 따르면, 트렌치(20) 저면의 기판층을 드러낸 뒤 선택적 결정 성장을 하는 과정에서 트렌치(20) 주변부에서 성장하는 성장막(19)은 측벽의 영향을 받아 트렌치의 중심부와 트렌치 주변부의 성장막의 성장 방향에 도1에 도시된 것과 같은 차이가 발생한다 (Facet). 따라서 두 영역 사이에는 결정 결함 (stacking fault)이 생기게 된다. 결정 결함부(22)는 전류 누출의 통로가 되므로 트렌치 소자 분리가 불완전하게 되는 문제가 발생한다.However, according to this technique, the growth layer 19 growing around the trench 20 during the selective crystal growth after exposing the substrate layer on the bottom of the trench 20 is influenced by sidewalls so that the center and the trench peripheral portion of the trench are affected. The difference as shown in Fig. 1 occurs in the growth direction of the growth film of (Facet). Thus, there is a stacking fault between the two regions. Since the crystal defect portion 22 becomes a passage for current leakage, a problem arises in that the trench element isolation is incomplete.
본 발명은 상술한 종래의 선택적 결정 성장을 이용한 트렌치형 소자 분리막형성 방법에서의 문제점을 해결하기 위한 것으로, 선택적 성장 기법을 이용하되 종래의 기술과 같은 성장막에서의 결정 결함과 그로 인한 소자간 전류 누출을 방지할 수 있는 트렌치형 소자 분리막 형성 방법을 제공하는 것을 목적으로 한다.The present invention is to solve the problems in the trench-type device isolation film formation method using the conventional selective crystal growth described above, using a selective growth technique, but the crystal defects in the growth film as in the prior art and the resulting inter-device current It is an object of the present invention to provide a trench type device isolation film formation method capable of preventing leakage.
도1은 선택적 결정 성장을 이용한 종래 트렌치형 소자 분리 방법의 문제점을 드러낸 공정 단면도,1 is a cross-sectional view illustrating a problem of a conventional trench type device isolation method using selective crystal growth;
도2 내지 도8은 본 발명 방법에 따른 트렌치형 소자 분리 방법의 각 단계를 나타내는 공정 단면도들이다.2 to 8 are process cross-sectional views showing each step of the trench type device isolation method according to the method of the present invention.
상기 목적을 달성하기 위한 본 발명에 따르면, 우선, 기판에 식각 방지막 패턴을 형성하여 트렌치를 식각한다. 식각 형성된 트렌치 내벽에 절연막을 형성한다. 절연막은 열산화막과 질화막 라이너로 통상 이루어진다. 트렌치 내벽에 절연막이 형성되면 실리콘막을 절연막 위에 형성한다. 다시, 실리콘막 위에 실리콘 산화막을 형성한다. CMP를 통해 실리콘 산화막을 제거하여 트렌치를 제외한 영역에 실리콘막 혹은 식각 방지막 패턴을 노출시킨다. 트렌치 영역에서 상부가 노출된 실리콘막에 대한 습식식각을 실시하되 트렌치 저부에만 실리콘막을 남긴다. 트렌치 내부의 실리콘 산화막을 등방성 식각으로 제거한다. 트렌치 저면의 실리콘막 위에 실리콘 소오스 가스를 주입하면서 실리콘막을 선택적으로 성장시켜 트렌치의 일정 부분을 채운다. 소자 분리용 절연막을 CVD로 적층하여 잔여 트랜치 공간을 채우게 된다.According to the present invention for achieving the above object, first, by forming an etching prevention film pattern on the substrate to etch the trench. An insulating film is formed on the etched trench inner wall. The insulating film usually consists of a thermal oxide film and a nitride film liner. When an insulating film is formed on the inner wall of the trench, a silicon film is formed on the insulating film. Again, a silicon oxide film is formed over the silicon film. The silicon oxide film is removed through the CMP to expose the silicon film or the etch stop layer pattern in the region excluding the trench. The wet etching is performed on the silicon film having the upper portion exposed in the trench area, but the silicon film is left only at the bottom of the trench. The silicon oxide film inside the trench is removed by isotropic etching. The silicon film is selectively grown while a silicon source gas is injected onto the silicon film on the bottom of the trench to fill a portion of the trench. The isolation layer for device isolation is deposited by CVD to fill the remaining trench space.
본 발명에서 실리콘막은 통상 폴리실리콘으로 이루어지며, 아몰퍼스 실리콘도 가능하다. 선택적 성장을 이용하여 트렌치에 실리콘막을 채우는 단계는 트렌치 잔여 깊이가 1000 내지 1500 옹스트롬에 이르기까지 진행하는 것이 바람직하다.In the present invention, the silicon film is usually made of polysilicon, and amorphous silicon is also possible. Filling the silicon film in the trench using selective growth preferably proceeds to a trench residual depth of 1000 to 1500 angstroms.
실리콘 소오스 가스를 주입하면서 실리콘막을 트렌치에 선택적으로 성장시키는 단계에서 여타 부분에는 실리콘막이 형성되지 않도록 소오스 가스와 함께 실리콘막에 대한 식각력을 가지는 염소 혹은 염화수소 가스를 함께 공급하는 것이 바람직하다.In the step of selectively growing the silicon film in the trench while injecting the silicon source gas, it is preferable to supply chlorine or hydrogen chloride gas having an etching power to the silicon film together with the source gas so that the silicon film is not formed in the other portions.
본 발명의 단계들에 이어 통상의 트렌치 소자 분리막 형성에서와 같은 후속 공정이 이루어진다. 즉, 트렌치를 채운 소자 분리용 절연막을 식각 마스크 패턴 상면에서 제거하기 위해 CMP 같은 평탄화 식각을 실시한다. 식각 마스크 패턴을 습식 식각을 통해 제거한다. 드러난 활성영역의 실리콘 기판에 게이트 절연막과 게이트 전극을 형성하고, 이온주입을 통해 소오스/드레인 영영을 형성한다.The steps of the present invention are followed by a subsequent process as in conventional trench device isolation. That is, planar etching such as CMP is performed to remove the trench isolation device isolation layer from the upper surface of the etching mask pattern. The etch mask pattern is removed by wet etching. A gate insulating film and a gate electrode are formed on the exposed silicon substrate in the active region, and source / drain regions are formed through ion implantation.
이하 도면을 참조하면서 실시예를 통해 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도2를 참조하여 설명하면, 통상의 트렌치형 소자 분리를 위한 초기 단계가 이루어진다. 기판(10)에 패드 산화막(11)과 실리콘 질화막으로 이루어진 식각 방지막을 형성한다. 식각 방지막 위에 포토리소그래피를 이용한 포토레지스트 패턴을 형성하고, 식각 방지막을 식각한다. 따라서, 트렌치 식각용 식각 방지막 패턴(13)이 형성된다. 포토레지스트 패턴을 제거한 상태에서, 실리콘 기판(10)을 선택적으로 식각하여 5000 옹스트롬 깊이의 트렌치(20)를 형성한다. 식각으로 인한 트렌치(20) 내벽의 결정 손상을 치유하기 위해 어닐링을 실시하여 트렌치(20) 내벽에 50 내지 300 옹스트롬의 열산화막(15)을 형성한다. 실리콘 질화막 라이너(17)를 50 내지 100 옹스트롬 두께로 열산화막(15) 위에 얇게 형성한다.Referring to Figure 2, an initial step for conventional trench isolation is performed. An etch stop layer formed of the pad oxide layer 11 and the silicon nitride layer is formed on the substrate 10. A photoresist pattern using photolithography is formed on the etch stop layer, and the etch stop layer is etched. Thus, the etching prevention film pattern 13 for trench etching is formed. With the photoresist pattern removed, the silicon substrate 10 is selectively etched to form trenches 20 to 5000 angstroms deep. Annealing is performed to cure the crystal damage of the inner wall of the trench 20 due to etching to form a thermal oxide film 15 of 300 to 300 angstroms on the inner wall of the trench 20. The silicon nitride film liner 17 is thinly formed on the thermal oxide film 15 to a thickness of 50 to 100 angstroms.
도3을 참조하면, 실리콘 질화막 라이너(17) 위에 기판 전면에 걸쳐 폴리실리콘층(31)이 얇게 형성된다. 그리고, 폴리실리콘층(31) 위에 실리콘 산화막(33)을 얇게 적층한다. 이들 막은 통상 CVD 방식으로 이루어진다. 폴리실리콘층(33) 대신 아몰퍼스 실리콘층으로 형성하는 것도 가능하다. 이때 형성되는 막들의 두께는 실리콘막이 50 내지 500 옹스트롬 정도, 실리콘 산화막이 100 내지 500 옹스트롬 정도로 이루어진다.Referring to FIG. 3, a thin polysilicon layer 31 is formed over the entire surface of the silicon nitride film liner 17. Then, a silicon oxide film 33 is laminated thinly on the polysilicon layer 31. These films are usually made by CVD. It is also possible to form an amorphous silicon layer instead of the polysilicon layer 33. In this case, the thicknesses of the formed films are about 50 to 500 angstroms of silicon and about 100 to 500 angstroms of silicon oxide.
도4를 참조하면, CMP를 통해 기판에서 실리콘 산화막을 제거한다. 이때 CMP 과정에서 폴리실리콘층(31)도 함게 제거되어 식각 방지막 패턴(13)이 드러날 수 있다. CMP를 이용한 식각이므로 오목한 트렌치 영역에서는 실리콘 산화막(331)과 폴리실리콘층(31)이 잔존하게 된다.4, the silicon oxide film is removed from the substrate through CMP. In this case, the polysilicon layer 31 may be removed together in the CMP process to expose the etch stop layer pattern 13. Since etching using CMP, the silicon oxide film 331 and the polysilicon layer 31 remain in the concave trench region.
도5를 참조하면, 기판에 폴리실리콘층을 제거하기 위한 식각을 실시한다. 단, 이때 트렌치 저면에 있는 폴리실리콘층(311)은 제거되지 않도록 식각 시간을 조절한다. 한편, 식각을 이방성으로 할 경우, 트렌치 내의 실리콘 산화막(331)이나 식각 방지막 패턴(13)과 선택비를 가지기 어렵다. 또한, 트렌치 측벽의 경사로 인하여 이방성 식각의 경우에는 도4의 폴리실리콘층(31)이 실리콘 산화막(331)에 의해 보호되므로 폴리실리콘층(31)을 선택적으로 제거하기 어렵다. 따라서, 본 단계에서 식각은 희석 암모니아 용액 같은 에천트를 이용한 습식 식각, 혹은 등방성 건식 식각으로 이루어지는 것이 바람직하다.Referring to Figure 5, the substrate is etched to remove the polysilicon layer. However, at this time, the etching time is adjusted so that the polysilicon layer 311 on the bottom of the trench is not removed. On the other hand, when etching is anisotropic, it is difficult to have a selectivity with the silicon oxide film 331 or the etching prevention film pattern 13 in a trench. In addition, in the case of anisotropic etching due to the inclination of the trench sidewalls, since the polysilicon layer 31 of FIG. 4 is protected by the silicon oxide layer 331, it is difficult to selectively remove the polysilicon layer 31. Therefore, in this step, the etching is preferably performed by wet etching using an etchant, such as dilute ammonia solution, or isotropic dry etching.
도6을 참조하면, 도5의 트렌치 내에 잔류된 실리콘 산화막(331)을 선택적으로 제거하기 위해 식각을 실시한다. 이때 실리콘 산화막(331)은 수직적으로 형성되어 있으므로 이방성 식각보다는 묽은 불산(HF) 등으로 습식 식각을 하여 제거하는 것이 바람직하다. 결과로, 도시된 바와 같이 트렌치 저면에 폴리실리콘층(311)만 남게 된다.Referring to FIG. 6, etching is performed to selectively remove the silicon oxide film 331 remaining in the trench of FIG. 5. In this case, since the silicon oxide layer 331 is vertically formed, the silicon oxide layer 331 is preferably removed by wet etching with dilute hydrofluoric acid (HF) rather than anisotropic etching. As a result, only the polysilicon layer 311 remains on the trench bottom as shown.
도7을 참조하면, 트렌치 저면에 잔류된 폴리실리콘층을 기반층(base or seedlayer)으로 실리콘 에피택셜층(epitaxial layer:313)을 선택적으로 성장시킨다. 이 과정에서 성장을 위한 소오스 가스로는 실레인, 다이실레인 (SiH4, Si2H6)와 같은 가스를 사용한다. 통상, 선택적 성장 공정은 580℃ 이상의 고온, 저압에서 이루어지고 베이스를 이루는 층이 폴리실리콘층이므로 성장층은 폴리실리콘층으로 이루어지게 된다. 이때, 기판의 다른 부분에도 폴리실리콘층이 적층될 수 있으므로 이를 방지하기 위해 소오스 가스와 함께 염화수소 혹은 염소 가스를 주입시킨다. 염소 가스는 베이스를 제외한 기판의 다른 부분에서 적층되는 실리콘층을 식각하여 제거하는 역할을 한다. 에피택셜층(313)의 선택적 성장은 트렌치의 상당 부분 가령, 트렌치 상부 1000 내지 1500 옹스트롬 정도를 제외한 나머지 부분을 채우도록 한다.Referring to FIG. 7, a silicon epitaxial layer 313 is selectively grown as a base or seed layer based on the polysilicon layer remaining on the bottom of the trench. In this process, as the source gas for growth, gases such as silane and disilane (SiH 4 , Si 2 H 6 ) are used. In general, the selective growth process is performed at a high temperature and low pressure of 580 ° C. or higher, and since the base layer is a polysilicon layer, the growth layer is made of a polysilicon layer. At this time, since the polysilicon layer may be stacked on other portions of the substrate, hydrogen chloride or chlorine gas is injected together with the source gas to prevent this. The chlorine gas serves to etch away and remove the silicon layer deposited on other parts of the substrate except the base. Selective growth of epitaxial layer 313 fills a significant portion of the trench, such as the top of the trench except for 1000 to 1500 angstroms.
도7 및 도8을 참조하면, 통상의 트렌치형 소자 분리 방법의 후 단계들이 이루어진다. 즉, 실리콘 산화막 같은 절연막(41)이 트렌치 잔여 공간을 채우게 된다. 트렌치 잔여 공간에 절연막(41)을 채우는 것은 통상 CVD 방식으로 이루어진다. 그리고, 식각 방지막 패턴(13) 위로 적층된 절연막은 CMP나 에치 백을 통해 제거된다. 이때 드러난 식각 방지막 패턴(13)도 인산 습식 식각을 통해 제거한다. 세정 공정을 거쳐 도8에 도시된 상태의 기판을 얻을 수 있다.7 and 8, post steps of a conventional trench type device isolation method are performed. That is, the insulating film 41 such as the silicon oxide film fills the remaining trench space. Filling the insulating film 41 in the remaining trench space is usually done by CVD. The insulating layer stacked on the etch stop layer pattern 13 is removed through CMP or etch back. In this case, the exposed etch barrier pattern 13 is also removed through phosphate wet etching. The substrate in the state shown in Fig. 8 can be obtained through the cleaning process.
후속적으로 도시된 것과 같이 소자 분리가 이루어진 기판에 게이트 절연막, 게이트 전극을 차례로 형성하고, 이온주입을 통하여 소오스/드레인 영역이 이루어져 MOS 트랜지스터를 구성하는 공정이 따르게 된다.Subsequently, a gate insulating film and a gate electrode are sequentially formed on the substrate on which the device is separated, and source / drain regions are formed through ion implantation to form a MOS transistor.
본 발명에 따르면, 트렌치 저부에 남겨진 아몰퍼스 실리콘 혹은 폴리 실리콘을 기반으로 선택적 성장이 이루어져 트렌치의 상당 부분을 채우게 된다. 따라서, 가로세로비가 큰 트렌치에 보이드 없이 소자 분리막을 형성시킬 수 있으며, 종래의 기술과 같은 트렌치 저면에서의 선택적 성장 과정에서 발생하는 결정 성장 방향의 차이 (facet)와 그로 인한 결정 결함 (stacking fault)이 방지되어 소자간 분리가 신뢰성 있게 이루어질 수 있다.According to the present invention, selective growth is based on amorphous silicon or polysilicon remaining in the bottom of the trench to fill a substantial portion of the trench. Therefore, it is possible to form a device isolation film without a void in a trench having a high aspect ratio, and the facet of the crystal growth direction occurring during the selective growth process in the trench bottom as in the prior art and the resulting stacking fault. This can be prevented so that isolation between the elements can be made reliably.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100502668B1 (en) * | 2003-07-22 | 2005-07-21 | 주식회사 하이닉스반도체 | Method of manufacturing semiconductor device |
| KR100829373B1 (en) * | 2002-12-30 | 2008-05-13 | 동부일렉트로닉스 주식회사 | Method for forming a active cell isolation layer of a semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100829373B1 (en) * | 2002-12-30 | 2008-05-13 | 동부일렉트로닉스 주식회사 | Method for forming a active cell isolation layer of a semiconductor device |
| KR100502668B1 (en) * | 2003-07-22 | 2005-07-21 | 주식회사 하이닉스반도체 | Method of manufacturing semiconductor device |
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