KR100502668B1 - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
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- KR100502668B1 KR100502668B1 KR10-2003-0050086A KR20030050086A KR100502668B1 KR 100502668 B1 KR100502668 B1 KR 100502668B1 KR 20030050086 A KR20030050086 A KR 20030050086A KR 100502668 B1 KR100502668 B1 KR 100502668B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000002955 isolation Methods 0.000 claims abstract description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 18
- 229920005591 polysilicon Polymers 0.000 claims abstract description 18
- 239000012535 impurity Substances 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 9
- 150000002500 ions Chemical class 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims abstract description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 9
- 238000001312 dry etching Methods 0.000 claims description 3
- 230000006866 deterioration Effects 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 10
- 238000005468 ion implantation Methods 0.000 description 8
- 239000011229 interlayer Substances 0.000 description 6
- 230000005684 electric field Effects 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Element Separation (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 소자분리 특성 열화를 방지하면서 리프레시 특성 및 동작속도를 개선할 수 있는 반도체 소자의 제조방법을 제공한다.The present invention provides a method of manufacturing a semiconductor device that can improve the refresh characteristics and operating speed while preventing deterioration of device isolation characteristics.
본 발명은 반도체 기판 상에 기판의 일부를 노출시키는 마스크 패턴을 형성하는 단계; 노출된 기판을 식각하여 트렌치를 형성하는 단계; 트렌치 표면에 제 1 산화막을 형성하는 단계; 트렌치 저부에만 고농도 불순물이온이 도핑된 도전막 패턴을 형성하는 단계; 및 트렌치에만 매립되도록 제 2 산화막을 증착하여 도전막 패턴 상에 소자분리막을 형성하는 단계를 포함한다. 바람직하게, 불순물이온은 P형이고, 도전막은 폴리실리콘막으로 이루어진다.The present invention includes forming a mask pattern on a semiconductor substrate to expose a portion of the substrate; Etching the exposed substrate to form a trench; Forming a first oxide film on the trench surface; Forming a conductive film pattern doped with a high concentration of impurity ions only at the bottom of the trench; And depositing a second oxide film so as to fill only the trench to form an isolation layer on the conductive film pattern. Preferably, the impurity ion is P-type, and the conductive film is made of a polysilicon film.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 리프레시 특성 및 동작속도를 개선할 수 있는 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device that can improve the refresh characteristics and operating speed.
일반적으로, 디램(DRAM; Dynamic Random Access Memory)과 같은 반도체 소자에서는 셀 트랜지스터를 P웰에 형성하고, 셀 영역내의 필드 트랜지스터에 의한 소자분리(isolation) 특성 열화에 의해 야기되는 접합간 누설(leakage)을 억제하기 위하여 필드산화막 하부에 필드스톱 이온주입에 의해 필드스톱(field stop) 이온주입층을 형성하고 있다.In general, in semiconductor devices such as DRAM (DRAM), cell transistors are formed in P wells, and inter-junction leakage caused by deterioration of isolation characteristics by field transistors in the cell region. A field stop ion implantation layer is formed under the field oxide film by field stop ion implantation in order to suppress the
그러나, 이러한 필드스톱 이온주입층은 필드산화막 뿐만 아니라 액티브 영역에도 형성되어, 셀 트랜지스터의 접합영역과 P웰 경계면의 P형 불순물, 예컨데 보론(boron; B)의 농도를 증가시켜 전계를 증가시킴으로써 리프레시(refresh) 특성을 열화시킬 뿐만 아니라 접합 캐패시턴스를 증가시켜 동작속도를 저하시킨다.However, the field stop ion implantation layer is formed not only in the field oxide film but also in the active region, and is refreshed by increasing the electric field by increasing the concentration of P-type impurities, such as boron (B), at the junction region of the cell transistor and the P well interface. Not only does it degrade the refresh characteristics, it also increases junction capacitance, which reduces operating speed.
본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 것으로, 소자분리 특성 열화를 방지하면서 리프레시 특성 및 동작속도를 개선할 수 반도체 소자의 제조방법을 제공하는데 그 목적이 있다. The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method of manufacturing a semiconductor device capable of improving refresh characteristics and operating speed while preventing deterioration of device isolation characteristics.
상기의 기술적 과제를 달성하기 위한 본 발명의 일 측면에 따르면, 상기의 본 발명의 목적은 반도체 기판 상에 기판의 일부를 노출시키는 마스크 패턴을 형성하는 단계; 노출된 기판을 식각하여 트렌치를 형성하는 단계; 트렌치 표면에 제 1 산화막을 형성하는 단계; 트렌치 저부에만 고농도 불순물이온이 도핑된 도전막 패턴을 형성하는 단계; 및 트렌치에만 매립되도록 제 2 산화막을 증착하여 도전막 패턴 상에 소자분리막을 형성하는 단계를 포함하는 반도체 소자의 제조방법에 의해 달성될 수 있다.According to an aspect of the present invention for achieving the above technical problem, an object of the present invention is to form a mask pattern for exposing a portion of the substrate on the semiconductor substrate; Etching the exposed substrate to form a trench; Forming a first oxide film on the trench surface; Forming a conductive film pattern doped with a high concentration of impurity ions only at the bottom of the trench; And forming a device isolation film on the conductive film pattern by depositing a second oxide film so as to be embedded only in the trench.
바람직하게, 불순물이온은 P형이고, 도전막은 폴리실리콘막으로 이루어진다.Preferably, the impurity ion is P-type, and the conductive film is made of a polysilicon film.
또한, 도전막 패턴을 형성하는 단계는 기판 상에 도전막을 증착하는 단계; 트렌치에만 매립되도록 포토레지스트 패턴을 형성하는 단계; 포토레지스트 패턴을 마스크로하여 도전막을 식각하는 단계; 및 포토레지스트 패턴을 제거하는 단계로 이루어지며, 도전막의 식각은 건식식각으로 수행하는 것이 바람직하다.The forming of the conductive film pattern may include depositing a conductive film on the substrate; Forming a photoresist pattern to fill the trench only; Etching the conductive film using the photoresist pattern as a mask; And removing the photoresist pattern, and the etching of the conductive film is preferably performed by dry etching.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
도 1a 내지 도 1i는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 단면도이고, 도 2는 도 1e의 Ⅱ-Ⅱ' 선에 따른 에너지 밴드 다이어그램이다.1A to 1I are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention, and FIG. 2 is an energy band diagram taken along line II-II ′ of FIG. 1E.
도 1a에 도시된 바와 같이, 반도체 기판(10) 상에 패드 산화막과 패드 질화막을 순차적으로 증착하고 패터닝하여 기판(10)의 일부를 노출시키는 소자분리용 마스크 패턴(11)을 형성한다. 그 다음, 마스크 패턴(11)에 의해 노출된 기판(10)을 소정 깊이만큼 식각하여 트렌치를 형성하고, 트렌치 표면에 비교적 얇게 제 1 산화막(12)을 형성한다.As shown in FIG. 1A, a pad oxide film and a pad nitride film are sequentially deposited and patterned on the semiconductor substrate 10 to form a device isolation mask pattern 11 exposing a portion of the substrate 10. Next, the substrate 10 exposed by the mask pattern 11 is etched to a predetermined depth to form a trench, and the first oxide film 12 is formed relatively thinly on the trench surface.
도 1b에 도시된 바와 같이, 트렌치를 포함하는 기판 전면 상에 P＋ 도핑된 도전막, 바람직하게 P＋ 폴리실리콘막(13)을 증착한다. 그 다음, 트렌치를 매립하도록 폴리실리콘막(13) 상부에 포토레지스트막을 도포하고 폴리실리콘막(13)이 노출되도록 에치백(Etch-back) 공정에 의해 포토레지스트막을 제거하여 트렌치에만 매립된 포토레지스트 패턴(14)을 형성한다.As shown in FIG. 1B, a P + doped conductive film, preferably a P + polysilicon film 13, is deposited on the entire surface of the substrate including the trench. Next, a photoresist film is applied on the polysilicon film 13 to fill the trench, and the photoresist film is removed by an etch-back process so that the polysilicon film 13 is exposed, thereby filling the photoresist embedded only in the trench. The pattern 14 is formed.
도 1c에 도시된 바와 같이, 포토레지스트 패턴(14)을 마스크로하여 건식식각에 의해 노출된 폴리실리콘막(13)을 식각하여 트렌치 저부에만 위치한 폴리실리콘막 패턴(13A)을 형성한다. 그 후, 공지된 방법에 의해 포토레지스트 패턴(14)을 제거한다.As illustrated in FIG. 1C, the polysilicon film 13 exposed by dry etching is etched using the photoresist pattern 14 as a mask to form a polysilicon film pattern 13A positioned only at the bottom of the trench. Thereafter, the photoresist pattern 14 is removed by a known method.
도 1d에 도시된 바와 같이, 트렌치를 매립하도록 기판 전면 상에 제 2 산화막을 증착하고 화학기계연마(Chemial Mechanical Polishing; CMP) 공정에 의해 마스크 패턴(11)이 노출되도록 제 2 산화막을 제거하여 폴리실리콘막 패턴(13A) 상부에 소자분리막(15)을 형성함과 동시에 기판을 평탄화한 후, 마스크 패턴(11)을 제거한다. 그 다음, 기판(10)의 셀영역에 딥 N웰(16)을 형성하고, 셀영역 및 주변영역의 PMOS 영역에는 N웰(17A, 17B)을 각각 형성하고 NMOS 영역에는 P웰(18A, 18B)을 각각 형성한 후, 기판 전면 상에 게이트 산화막(19)을 형성한다.As shown in FIG. 1D, a second oxide film is deposited on the entire surface of the substrate to fill the trench, and the second oxide film is removed to expose the mask pattern 11 by a chemical mechanical polishing (CMP) process. After forming the device isolation film 15 on the silicon film pattern 13A and planarizing the substrate, the mask pattern 11 is removed. Next, a deep N well 16 is formed in the cell region of the substrate 10, and N wells 17A and 17B are formed in the PMOS regions of the cell region and the peripheral region, respectively, and P wells 18A and 18B in the NMOS region. ) Are formed, and then a gate oxide film 19 is formed on the entire substrate.
도 1e에 도시된 바와 같이, 게이트 산화막(19) 상에 게이트(20) 및 게이트 스페이서(22)를 형성하고, 셀영역의 P웰(18A)에는 N- 소오스/드레인 접합영역(21), 주변영역의 P웰(18B) 및 N웰(17B)에는 LDD(Lightly Doped Drain) 구조의 N＋ 및 P＋소오스/드레인 접합영역(23, 24)을 각각 형성하여, PMOS 및 NMOS 트랜지스터를 형성한다.As shown in FIG. 1E, the gate 20 and the gate spacer 22 are formed on the gate oxide film 19, and the N − source / drain junction region 21 is surrounded by the P well 18A of the cell region. N + and P + source / drain junction regions 23 and 24 having a LDD (Lightly Doped Drain) structure are formed in the P wells 18B and N well 17B in the region, respectively, to form PMOS and NMOS transistors.
즉, 소자분리막(15) 하부에 P＋ 폴리실리콘막 패턴(13A)을 형성함에 따라, 도 2에 도시된 바와 같이, P웰(13A)과 P＋ 폴리실리콘막 패턴(13A) 사이의 내부 전위 (built-in potential)에 의해 전위장벽차가 발생하여 필드스톱 이온주입을 수행하는 것 없이 우수한 소자분리특성을 확보할 수 있을 뿐만 아니라 셀 트랜지스터의 접합영역(21)과 P웰(13A) 사이의 전계 감소에 의해 향상된 리프레시 특성을 얻을 수 있게 된다.That is, as the P + polysilicon film pattern 13A is formed under the device isolation film 15, as shown in FIG. 2, the internal potential between the P well 13A and the P + polysilicon film pattern 13A is shown. (potential barrier difference is generated by the built-in potential, which ensures excellent device isolation characteristics without performing fieldstop ion implantation, as well as an electric field between the junction region 21 and the P well 13A of the cell transistor. The reduction makes it possible to obtain improved refresh characteristics.
한편, 주변영역의 PMOS 영역인 N웰(17B)에서는 P형 불순물, 예컨대 B의 농도 증가에 의해 소자분리 특성이 저하되지만, 이후 N웰(17B)의 P＋ 폴리실리콘막 패턴 (13A)에 Vdd 보다 높은 Vpp를 인가하면 소자분리막(15) 하부가 반전(inversion)되어 소자분리 특성 확보가 가능해진다. 여기서, Vdd는 디램에서 하이레벨(H)의 데이터 판독(write)시 데이터를 저장노드(storage node)에 완전히 충전시키기 위하여 셀 트랜지스터의 게이트에 인가되는 전압이다.On the other hand, in the N well 17B, which is the PMOS region of the peripheral region, device isolation characteristics are deteriorated due to an increase in the concentration of P-type impurities, for example, B, but then Vdd is applied to the P + polysilicon film pattern 13A of the N well 17B. When a higher Vpp is applied, the lower portion of the device isolation layer 15 is inverted to secure device isolation characteristics. Here, Vdd is a voltage applied to the gate of the cell transistor in order to completely charge the data to the storage node during the data write of the high level H in the DRAM.
도 1f에 도시된 바와 같이, 기판 전면 상에 제 1 층간절연막(25)을 증착하고 평탄화 시킨 후, 제 1 층간절연막(25)을 식각하여 셀영역의 접합영역(21)을 노출시키는 제 1 콘택홀을 형성한다. 그 다음, 제 1 콘택홀을 통하여 노출된 접합영역 (21)으로 P형 불순물, 바람직하게 P(Phosphorous) 이온을 이온주입(26) 하여 접합영역(21)과 P웰(18A) 사이의 전계를 감소시킨다.As shown in FIG. 1F, after depositing and planarizing the first interlayer insulating layer 25 on the entire surface of the substrate, the first contact exposing the junction region 21 of the cell region by etching the first interlayer insulating layer 25. Form a hole. P-type impurities, preferably P (phosphorous) ions, are implanted into the junction region 21 exposed through the first contact hole, thereby forming an electric field between the junction region 21 and the P well 18A. Decrease.
도 1g에 도시된 바와 같이, 제 1 콘택홀에 매립되도록 N＋ 폴리실리콘막을 증착하고 에치백에 의해 분리시켜 접합영역(21)과 콘택하는 플러그(27)를 형성한다. 그 후, 기판 전면 상에 제 2 층간절연막(27)을 증착하고 식각하여 플러그(27)의 일부를 노출시키는 비트라인(bit line; BL)용 제 2 콘택홀(28)을 형성한다.As shown in FIG. 1G, an N + polysilicon film is deposited to be filled in the first contact hole and separated by etch back to form a plug 27 that contacts the junction region 21. Thereafter, a second interlayer insulating layer 27 is deposited and etched on the entire surface of the substrate to form a second contact hole 28 for a bit line BL to expose a portion of the plug 27.
도 1h에 도시된 바와 같이, 제 2 및 제 1 층간절연막(27, 25)과 소자분리막(15)을 식각하여 주변영역의 접합영역(23, 24)을 노출시키는 제 3 콘택홀과 폴리실리콘막 패턴(13A)을 노출시키는 제 4 콘택홀을 각각 형성한다. 그 다음, 주변영역의 N웰(17B)을 오픈시키는 마스크 패턴(29)을 형성하고, 오픈된 N웰 (17B)의 접합영역(24) 및 폴리실리콘막 패턴(13A)으로 P형 불순물이온을 이온주입 (30)하여 숏키배리어(schotky barrier)를 제거하여 콘택저항을 감소시킨 후다.As shown in FIG. 1H, the third contact hole and the polysilicon film exposing the junction regions 23 and 24 of the peripheral region by etching the second and first interlayer insulating layers 27 and 25 and the device isolation layer 15. Fourth contact holes exposing the pattern 13A are formed, respectively. Next, a mask pattern 29 is formed to open the N well 17B in the peripheral region, and P-type impurity ions are formed into the junction region 24 and the polysilicon film pattern 13A of the open N well 17B. After ion implantation (30), the Schottky barrier is removed to reduce the contact resistance.
도 1i에 도시된 바와 같이, 공지된 방법에 의해 마스크 패턴(29)을 제거하고, 제 2 내지 제 4 콘택홀을 매립하도록 제 2 층간절연막(27) 상에 텅스텐막과 같은 금속막을 증착하고 패터닝하여 셀영역의 플러그(27) 일부와 콘택하는 비트라인 (31A), 폴리실리콘막 패턴(13A)과 콘택하는 배선(31B1, 31B2, 31B3) 및 주변영역의 접합영역(23, 24)과 콘택하는 배선(31C1, 31C2, 31C3, 31C4)를 형성한다. 여기서, 배선(31B1, 31B2, 31C2)에는 Vss(GND), 배선(31C4)에는 Vdd, 배선(31B3)에는 Vpp가 각각 인가된다.As shown in FIG. 1I, the mask pattern 29 is removed by a known method, and a metal film such as a tungsten film is deposited and patterned on the second interlayer insulating film 27 to fill the second to fourth contact holes. Contacting the bit line 31A, the polysilicon film pattern 13A, and the wirings 31B1, 31B2, 31B3 and the junction regions 23, 24 of the peripheral region. The wirings 31C1, 31C2, 31C3, and 31C4 are formed. Here, Vss (GND) is applied to the wirings 31B1, 31B2, and 31C2, Vdd is applied to the wiring 31C4, and Vpp is applied to the wiring 31B3, respectively.
상기 실시예에 의하면, 소자분리막 하부에 P＋ 폴리실리콘막 패턴을 형성하는 것에 의해, 필드스톱 이온주입을 수행하는 것 없이 소자분리 특성을 향상시킬 수 있을 뿐만 아니라 셀 트랜지스터의 접합영역과 P웰 사이의 전계 감소에 의해 우수한 리프레시 특성을 얻을 수 있게 된다. 또한, 필드스톱 이온주입층 배제에 의해 접합영역과 웰 사이의 접합 캐패시턴스를 감소시킬 수 있으므로 빠른 동작 속도를 얻을 수 있게 된다.According to the above embodiment, by forming a P + polysilicon film pattern under the device isolation film, it is possible to improve device isolation characteristics without performing fieldstop ion implantation, as well as between the junction region of the cell transistor and the P well. An excellent refresh characteristic can be obtained by reducing the electric field of. In addition, by eliminating the field stop ion implantation layer, the junction capacitance between the junction region and the well can be reduced, thereby achieving a high operating speed.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
전술한 본 발명은 디램 소자의 제조 시 소자분리 특성 열화를 방지하여 우수한 소자분리 특성을 얻을 수 있다.The present invention described above can obtain excellent device isolation characteristics by preventing deterioration of device isolation characteristics during fabrication of DRAM devices.
또한, 셀 트랜지스터의 접합영역과 P웰 사이의 전계를 감소시킬 수 있으므로 우수한 리프레시 특성을 얻을 수 있다.In addition, since the electric field between the junction region of the cell transistor and the P well can be reduced, excellent refresh characteristics can be obtained.
또한, 접합영역과 웰 사이의 접합 캐패시턴스를 감소시킬 수 있으므로 역과 방지할 수 있으므로 빠른 동작 속도를 얻을 수 있다.In addition, since the junction capacitance between the junction region and the well can be reduced, conversely and can be prevented, a fast operation speed can be obtained.
도 1a 내지 도 1i는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 단면도.1A to 1I are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
도 2는 도 1e의 Ⅱ-Ⅱ' 선에 따른 에너지 밴드 다이어그램.FIG. 2 is an energy band diagram taken along line II-II 'of FIG. 1E. FIG.
※도면의 주요부분에 대한 부호의 설명※ Explanation of symbols for main parts of drawing
10 : 반도체 기판 11, 29 : 마스크 패턴10: semiconductor substrate 11, 29: mask pattern
12 : 산화막 13 : P＋ 폴리실리콘막12: oxide film 13: P + polysilicon film
13A : P＋ 폴리실리콘막 패턴 14 : 포토레지스트 패턴13A: P + polysilicon film pattern 14: photoresist pattern
15 : 소자분리막 16 : 딥 N웰15 device isolation layer 16 deep N well
17A, 17B : N웰 18A, 18B : P웰17A, 17B: N well 18A, 18B: P well
19 : 게이트 산화막 20 : 게이트19: gate oxide film 20: gate
21 : N- 소오스/드레인 접합영역 22 : 스페이서21: N - source / drain junction region 22: spacer
23 : N＋ 소오스/드레인 접합영역 24 : P＋ 소오스/드레인 접합영역23: N + source / drain junction region 24: P + source / drain junction region
25, 27 ; 층간절연막 26, 30 : 이온주입25, 27; Interlayer insulating film 26, 30: ion implantation
28 : 콘택홀 31A : 비트라인28: contact hole 31A: bit line
31B1, 31B2, 31B3, 31C1, 31C2, 31C3, 31C4 : 배선31B1, 31B2, 31B3, 31C1, 31C2, 31C3, 31C4: Wiring
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61176133A (en) * | 1985-01-31 | 1986-08-07 | Toshiba Corp | Manufacture of semiconductor device |
| KR20010061047A (en) * | 1999-12-28 | 2001-07-07 | 박종섭 | A method for forming trench type isolation layer using ceria-based slurry |
| KR20020042275A (en) * | 2000-11-30 | 2002-06-05 | 윤종용 | Shallow trench isolation type semiconductor device and method of forming the same |
| KR20020080912A (en) * | 2001-04-18 | 2002-10-26 | 삼성전자 주식회사 | Method of forming trench type isolation layer in semiconductor device |
| KR20030002703A (en) * | 2001-06-29 | 2003-01-09 | 주식회사 하이닉스반도체 | Method of forming an isolation layer in a semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61176133A (en) * | 1985-01-31 | 1986-08-07 | Toshiba Corp | Manufacture of semiconductor device |
| KR20010061047A (en) * | 1999-12-28 | 2001-07-07 | 박종섭 | A method for forming trench type isolation layer using ceria-based slurry |
| KR20020042275A (en) * | 2000-11-30 | 2002-06-05 | 윤종용 | Shallow trench isolation type semiconductor device and method of forming the same |
| KR20020080912A (en) * | 2001-04-18 | 2002-10-26 | 삼성전자 주식회사 | Method of forming trench type isolation layer in semiconductor device |
| KR20030002703A (en) * | 2001-06-29 | 2003-01-09 | 주식회사 하이닉스반도체 | Method of forming an isolation layer in a semiconductor device |
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